/************************************************************************* * * FILE NAME : pci-amazon_s.c * PROJECT : Danube * MODULES : PCI * * DATE : 19th July 2007 * AUTHOR : Teh Kok How * * DESCRIPTION : PCI Host Controller Driver * COPYRIGHT : Copyright (c) 2006 * Infineon Technologies AG * Am Campeon 1-12, 85579 Neubiberg, Germany * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * HISTORY * $Version $Date $Author $Comment * 1.0 19/07/2007 Teh Kok How * 2.0 15/11/2007 Teh Kok How Fixes Interrupts and byte-swapping *************************************************************************/ #include #include #include #include #include #include #include #include #include #include #include #include //#define PCI_DEBUG #undef BSP_PCI_TEST #ifdef CONFIG_AMAZON_S_PCI_HW_SWAP #define CONFIG_BSP_PCI_HW_SWAP #else #undef CONFIG_BSP_PCI_HW_SWAP #endif #define CFGOFFSET(bus,devfn,where) (((bus)<<16) + ((devfn)<<8) + (where)) #define BSP_PCI_REG32( addr ) (*(volatile u32 *)(addr)) #define BSP_CGU_IFCCR AMAZON_S_CGU_IFCCR #define BSP_CGU_PCICR AMAZON_S_CGU_PCICR #define BSP_PCI_CFG_BASE AMAZON_S_PCI_CFG_BASE #define BSP_EBU_PCC_CON AMAZON_S_EBU_PCC_CON #define BSP_EBU_PCC_IEN AMAZON_S_EBU_PCC_IEN #define PCI_BRIDGE_DEVICE 0 #define PCI_BUS_ENABLED 1 extern unsigned long physical_memsize; extern struct pci_ops amazon_s_pci_ops; extern int amazon_s_pci_bus_status; extern void __iomem *cfg_space; /* * * Read/write 32-bit values in config space. * */ extern u32 READCFG32 (u32 addr); extern void WRITECFG32 (u32 addr, u32 data); int pci_bus_error_flag; extern struct pci_controller amazon_s_pci_controller; static void __init amazon_s_pci_startup (void) { /*initialize the first PCI device--amazon_s itself */ u32 temp_buffer; /* make sure PCI clock is slower than FPI clock */ //extern unsigned int bsp_get_fpi_hz (void); //if ( bsp_get_fpi_hz() < CLOCK_60M){ /*use 33.3M */ /*TODO: trigger reset */ BSP_PCI_REG32 (BSP_CGU_IFCCR) &= (~(0x01f00000)); #ifdef CONFIG_AMAZON_S_PCI_INTERNAL_CLK_SRC_60 // 62.5MHz internal clock BSP_PCI_REG32 (BSP_CGU_IFCCR) |= ((0x00700000)); #else // 33.3MHz internal clock BSP_PCI_REG32 (BSP_CGU_IFCCR) |= ((0x00e00000)); #endif //printk("PCI clock 33.3MHz\n"); //} /* PCIS of IF_CLK of CGU : 1 =>PCI Clock output 0 =>clock input PADsel of PCI_CR of CGU : 1 =>From CGU : 0 =>From pad */ #ifdef CONFIG_AMAZON_S_PCI_EXTERNAL_CLK_SRC BSP_PCI_REG32 (BSP_CGU_IFCCR) &= ~(1 << 16); #else BSP_PCI_REG32 (BSP_CGU_IFCCR) |= ((1 << 16)); #endif //BSP_PCI_REG32(BSP_CGU_PCICR) = (1<<31); #if !defined(CONFIG_AMAZON_S_PCI_CLOCK_DELAY) || CONFIG_AMAZON_S_PCI_CLOCK_DELAY < 0 || CONFIG_AMAZON_S_PCI_CLOCK_DELAY > 7 #error please define CONFIG_AMAZON_S_PCI_CLOCK_DELAY properly #endif BSP_PCI_REG32 (BSP_CGU_PCICR) = ((1 << 31) | (1 << 30)) | ((CONFIG_AMAZON_S_PCI_CLOCK_DELAY & 0x07) << 21); #if 0 // TODO: use GPIO driver #define BSP_GPIO_P1_OUT AMAZON_S_GPIO_P1_OUT #define BSP_GPIO_P1_OD AMAZON_S_GPIO_P1_OD #define BSP_GPIO_P1_DIR AMAZON_S_GPIO_P1_DIR #define BSP_GPIO_P1_ALTSEL1 AMAZON_S_GPIO_P1_ALTSEL1 #define BSP_GPIO_P1_ALTSEL0 AMAZON_S_GPIO_P1_ALTSEL0 #ifndef CONFIG_AMAZON_S_PCI_WORKAROUND_2GPIO /* prepare GPIO */ /* PCI_RST: P1.5 ALT 01 */ *BSP_GPIO_P1_OUT |= ((1 << 5)); *BSP_GPIO_P1_OD |= ((1 << 5)); *BSP_GPIO_P1_DIR |= ((1 << 5)); *BSP_GPIO_P1_ALTSEL1 &= (~(1 << 5)); *BSP_GPIO_P1_ALTSEL0 &= (~(1 << 5)); /* PCI_REQ1: P1.13 ALT 01 */ /* PCI_GNT1: P1.14 ALT 01 */ *BSP_GPIO_P1_DIR &= (~(0x2000)); *BSP_GPIO_P1_DIR |= ((0x4000)); *BSP_GPIO_P1_ALTSEL1 &= (~(0x6000)); *BSP_GPIO_P1_ALTSEL0 |= ((0x6000)); /* PCI_REQ2: P1.15 ALT 10 */ /* PCI_GNT2: P1.7 ALT 10 */ #else /* prepare GPIO */ /* PCI_RST: P1.14 ALT 00 */ *BSP_GPIO_P1_OUT |= ((1 << 14)); *BSP_GPIO_P1_OD |= ((1 << 14)); *BSP_GPIO_P1_DIR |= ((1 << 14)); *BSP_GPIO_P1_ALTSEL1 &= (~(1 << 14)); *BSP_GPIO_P1_ALTSEL0 &= (~(1 << 14)); /* PCI_REQ1: P1.13 ALT 01 */ /* PCI_GNT1 (ignore): P1.14 ALT 01 */ *BSP_GPIO_P1_DIR &= (~(0x2000)); *BSP_GPIO_P1_ALTSEL1 &= (~(0x2000)); *BSP_GPIO_P1_ALTSEL0 |= ((0x2000)); /* PCI_REQ2: P1.15 ALT 10 */ /* PCI_GNT2: P1.7 ALT 10 */ #endif #else #ifndef CONFIG_AMAZON_S_PCI_WORKAROUND_2GPIO /* PCI_RST: P1.5 ALT 01 */ if ( !bsp_port_reserve_pin(1, 5, PORT_MODULE_PCI) ) { bsp_port_set_output(1, 5, PORT_MODULE_PCI); bsp_port_set_open_drain(1, 5, PORT_MODULE_PCI); bsp_port_set_dir_out(1, 5, PORT_MODULE_PCI); bsp_port_clear_altsel1(1, 5, PORT_MODULE_PCI); bsp_port_clear_altsel0(1, 5, PORT_MODULE_PCI); } #ifdef CONFIG_AMAZON_S_DUAL_MINI_PCI /* PCI_REQ1: P1.13 ALT 01 */ if ( !bsp_port_reserve_pin(1, 13, PORT_MODULE_PCI) ) { bsp_port_set_dir_in(1, 13, PORT_MODULE_PCI); bsp_port_clear_altsel1(1, 13, PORT_MODULE_PCI); bsp_port_set_altsel0(1, 13, PORT_MODULE_PCI); } /* PCI_GNT1: P1.14 ALT 01 */ if ( !bsp_port_reserve_pin(1, 14, PORT_MODULE_PCI) ) { bsp_port_set_dir_out(1, 14, PORT_MODULE_PCI); bsp_port_clear_altsel1(1, 14, PORT_MODULE_PCI); bsp_port_set_altsel0(1, 14, PORT_MODULE_PCI); bsp_port_set_open_drain(1, 14, PORT_MODULE_PCI); } #endif #else /* PCI_RST: P1.14 ALT 00 */ if ( !bsp_port_reserve_pin(1, 14, PORT_MODULE_PCI) ) { bsp_port_set_output(1, 14, PORT_MODULE_PCI); bsp_port_set_open_drain(1, 14, PORT_MODULE_PCI); bsp_port_set_dir_out(1, 14, PORT_MODULE_PCI); bsp_port_clear_altsel1(1, 14, PORT_MODULE_PCI); bsp_port_clear_altsel0(1, 14, PORT_MODULE_PCI); } /* PCI_REQ1: P1.13 ALT 01 */ if ( !bsp_port_reserve_pin(1, 13, PORT_MODULE_PCI) ) { bsp_port_set_dir_in(1, 13, PORT_MODULE_PCI); bsp_port_clear_altsel1(1, 13, PORT_MODULE_PCI); bsp_port_set_altsel0(1, 13, PORT_MODULE_PCI); } #endif #endif #ifdef CONFIG_USE_EMULATOR /*change to internal reset */ *BSP_CGU_PCICR = *BSP_CGU_PCICR | 0x40000000; /* GPIO21 PCI reset */ /* PCI reset:1 */ #ifndef BSP_GPIO_P1_OUT #define BSP_GPIO_P1_OUT AMAZON_S_GPIO_P1_OUT #endif *BSP_GPIO_P1_OUT = *BSP_GPIO_P1_OUT & (~(0x20)); *BSP_GPIO_P1_OUT = *BSP_GPIO_P1_OUT | ((0x20)); #endif /* enable auto-switching between PCI and EBU */ BSP_PCI_REG32 (PCI_CR_CLK_CTRL_REG) = 0xA; /* busy, i.e. configuration is not done, PCI access has to be retried */ BSP_PCI_REG32 (PCI_CR_PCI_MOD_REG) &= (~(1 << 24)); wmb (); /* BUS Master/IO/MEM access */ BSP_PCI_REG32 (PCI_CS_STS_CMD_REG) |= (7); temp_buffer = BSP_PCI_REG32 (PCI_CR_PC_ARB_REG); #ifdef CONFIG_AMAZON_S_DUAL_MINI_PCI /* enable external 2 PCI masters */ temp_buffer &= (~(0x3 << 16)); #else /* enable external 1 PCI masters */ temp_buffer &= (~(0x1 << 16)); #endif /* enable internal arbiter */ temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); /* enable internal PCI master reqest */ temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS)); #ifdef EBU_PCI_SOFTWARE_ARBITOR temp_buffer |= ((3 << PCI_MASTER1_REQ_MASK_2BITS)); #else /* enable EBU reqest */ temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS)); #endif /* enable all external masters request */ temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS)); BSP_PCI_REG32 (PCI_CR_PC_ARB_REG) = temp_buffer; wmb (); /* FPI ==> PCI MEM address mapping */ /* base: 0xb8000000 == > 0x18000000 */ /* size: 8x4M = 32M */ BSP_PCI_REG32 (PCI_CR_FCI_ADDR_MAP0_REG) = BSP_PCI_MEM_BASE; BSP_PCI_REG32 (PCI_CR_FCI_ADDR_MAP1_REG) = BSP_PCI_MEM_BASE + 0x00400000; BSP_PCI_REG32 (PCI_CR_FCI_ADDR_MAP2_REG) = BSP_PCI_MEM_BASE + 0x00800000; BSP_PCI_REG32 (PCI_CR_FCI_ADDR_MAP3_REG) = BSP_PCI_MEM_BASE + 0x00c00000; BSP_PCI_REG32 (PCI_CR_FCI_ADDR_MAP4_REG) = BSP_PCI_MEM_BASE + 0x01000000; BSP_PCI_REG32 (PCI_CR_FCI_ADDR_MAP5_REG) = BSP_PCI_MEM_BASE + 0x01400000; BSP_PCI_REG32 (PCI_CR_FCI_ADDR_MAP6_REG) = BSP_PCI_MEM_BASE + 0x01800000; BSP_PCI_REG32 (PCI_CR_FCI_ADDR_MAP7_REG) = BSP_PCI_MEM_BASE + 0x01c00000; /* FPI ==> PCI IO address mapping */ /* base: 0xbAE00000 == > 0xbAE00000 */ /* size: 2M */ BSP_PCI_REG32 (PCI_CR_FCI_ADDR_MAP11hg_REG) = BSP_PCI_IO_BASE; /* PCI ==> FPI address mapping */ /* base: 0x0 ==> 0x0 */ /* size: 32M/64M */ /* BAR1 32M map to SDR address */ // BSP_PCI_REG32 (PCI_CR_BAR11MASK_REG) = 0x0E000008; BSP_PCI_REG32 (PCI_CR_BAR11MASK_REG) = (~(physical_memsize - 1) & 0x0FFFFFF0) | 0x08; BSP_PCI_REG32 (PCI_CR_PCI_ADDR_MAP11_REG) = 0x0; BSP_PCI_REG32 (PCI_CS_BASE_ADDR1_REG) = 0x0; #ifdef CONFIG_BSP_PCI_HW_SWAP /* both TX and RX endian swap are enabled */ BSP_PCI_REG32 (PCI_CR_PCI_EOI_REG) |= 3; wmb (); #endif /*TODO: disable BAR2 & BAR3 */ BSP_PCI_REG32 (PCI_CR_BAR12MASK_REG) |= 0x80000000; BSP_PCI_REG32 (PCI_CR_BAR13MASK_REG) |= 0x80000000; /*use 8 dw burse length */ BSP_PCI_REG32 (PCI_CR_FCI_BURST_LENGTH_REG) = 0x303; BSP_PCI_REG32 (PCI_CR_PCI_MOD_REG) |= ((1 << 24)); wmb (); mdelay (1); #if 0 #ifndef CONFIG_AMAZON_S_PCI_WORKAROUND_2GPIO // TODO: use GPIO driver *BSP_GPIO_P1_OUT &= (~(1 << 5)); #else *BSP_GPIO_P1_OUT &= (~(1 << 14)); #endif #else #ifndef CONFIG_AMAZON_S_PCI_WORKAROUND_2GPIO bsp_port_clear_output(1, 5, PORT_MODULE_PCI); #else bsp_port_clear_output(1, 14, PORT_MODULE_PCI); #endif #endif wmb (); mdelay (1); #if 0 #ifndef CONFIG_AMAZON_S_PCI_WORKAROUND_2GPIO // TODO: use GPIO driver *BSP_GPIO_P1_OUT |= (1 << 5); #else *BSP_GPIO_P1_OUT |= (1 << 14); #endif #else #ifndef CONFIG_AMAZON_S_PCI_WORKAROUND_2GPIO bsp_port_set_output(1, 5, PORT_MODULE_PCI); #else bsp_port_set_output(1, 14, PORT_MODULE_PCI); #endif #endif wmb (); mdelay (1); } #ifdef BSP_PCI_TEST static void dump_cs (u32 base) { int i; u32 data; printk(KERN_INFO "[%s %s %d]: Dumping %08x\n", __FILE__, __func__, __LINE__, base); for (i = 0; i < 64; i++) { data = le32_to_cpu(BSP_PCI_REG32 (((base) | (i * 4)))); printk ("%08x: %08x\n", base | (i*4), data); } printk ("\n"); } #endif static int __init amazon_s_pcibios_init (void) { u32 cmdreg; printk ("PCI: Probing PCI hardware on host bus 0.\n"); pci_bus_error_flag = 1; /* CFE will assign PCI resources */ // pci_probe_only = 1; #if 0 /* Avoid ISA compat ranges. */ PCIBIOS_MIN_IO = 0x00008000UL; PCIBIOS_MIN_MEM = 0x01000000UL; #endif /* Set I/O resource limits. */ #if 0 ioport_resource.start = 0; /* 1MB accessible by sb1250 */ ioport_resource.end = -1; /* 1MB accessible by sb1250 */ iomem_resource.start = 0; /* no HT support yet */ iomem_resource.end = -1; /* no HT support yet */ #endif #ifdef CONFIG_USE_EMULATOR #ifndef BSP_GPIO_P1_ALTSEL0 #define BSP_GPIO_P1_ALTSEL0 AMAZON_S_GPIO_P1_ALTSEL0 #define BSP_GPIO_P1_ALTSEL1 AMAZON_S_GPIO_P1_ALTSEL1 #define BSP_GPIO_P1_DIR AMAZON_S_GPIO_P1_DIR #define BSP_GPIO_P1_OD AMAZON_S_GPIO_P1_OD #endif *BSP_GPIO_P1_ALTSEL0 = *BSP_GPIO_P1_ALTSEL0 & ~(1 << 7); *BSP_GPIO_P1_ALTSEL1 = *BSP_GPIO_P1_ALTSEL1 & ~(1 << 7); *BSP_GPIO_P1_DIR = *BSP_GPIO_P1_DIR | (1 << 7); *BSP_GPIO_P1_OD = *BSP_GPIO_P1_OD | (1 << 7); *BSP_GPIO_P1_OUT = *BSP_GPIO_P1_OUT | (1 << 7); #define BSP_GPIO_P0_ALTSEL0 AMAZON_S_GPIO_P0_ALTSEL0 #define BSP_GPIO_P0_ALTSEL1 AMAZON_S_GPIO_P0_ALTSEL1 #define BSP_GPIO_P0_DIR AMAZON_S_GPIO_P0_DIR #define BSP_GPIO_P0_OUT AMAZON_S_GPIO_P0_OUT *BSP_GPIO_P0_ALTSEL0 = *BSP_GPIO_P0_ALTSEL0 & (~0x1); *BSP_GPIO_P0_ALTSEL1 = *BSP_GPIO_P0_ALTSEL1 & (~0x1); //*BSP_GPIO_P0_DIR |= 0x81; *BSP_GPIO_P0_DIR |= 0x01; *BSP_GPIO_P0_OUT |= 0x1; *BSP_GPIO_P1_DIR = *BSP_GPIO_P1_DIR | 0x20; *BSP_GPIO_P1_OD = *BSP_GPIO_P1_OD | 0x20; /* GPIO 0 reset amazon */ *BSP_GPIO_P0_OUT = *BSP_GPIO_P0_OUT & (~(1 << 0)); *BSP_GPIO_P0_OUT = *BSP_GPIO_P0_OUT | ((1 << 0)); /* PCI reset:1 */ *BSP_GPIO_P1_OUT = *BSP_GPIO_P1_OUT | (0x20); #endif amazon_s_pci_startup (); cfg_space = ioremap(BSP_PCI_CFG_BASE, 16*1024*1024); if (!cfg_space) panic("Could not ioremap BSP_PCI_CFG_BASE!\n"); #ifdef PCI_DEBUG printk(KERN_INFO "[%s %s %d]: cfg_space %p\n", __FILE__, __func__, __LINE__, cfg_space); #endif cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), PCI_COMMAND)); if (!(cmdreg & PCI_COMMAND_MASTER)) { printk(KERN_INFO "PCI: Skipping PCI probe. Bus is not initialized.\n"); iounmap(cfg_space); return 0; } amazon_s_pci_bus_status |= PCI_BUS_ENABLED; /* turn on ExpMemEn */ cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40)); WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40), cmdreg | 0x10); cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40)); #ifdef BSP_PCI_TEST dump_cs (EXT_PCI14_CONFIG_SPACE_BASE_ADDR); #endif BSP_PCI_REG32 (PCI_CR_CLK_CTRL_REG) &= (~8); /* machine dependent fixups: void __init pcibios_fixup(void) */ #ifdef PCI_DEBUG printk (KERN_INFO "[%s %s %d]: mem_resource @%p, io_resource @%p\n", __FILE__, __func__, __LINE__, &amazon_s_pci_controller.mem_resource, &amazon_s_pci_controller.io_resource); #endif register_pci_controller (&amazon_s_pci_controller); #ifdef PCI_DEBUG printk (KERN_INFO "pcibios_init finished!\n"); #endif #if 0 printk(KERN_INFO "[%s %d]: PCI Config:\n", __func__, __LINE__); for (cmdreg = 0, ptr = 0xB7000000; ptr < 0xB8000000; ) { // for (cmdreg = 0, ptr = 0xB7007000; ptr < 0xB8000000; ) { printk(KERN_INFO "\t%p: ", ptr); ret = get_dbe(busno, ptr); if(ret) // if(get_dbe(busno, (u32*)ptr)) { printk("-1\n"); else printk("%#x\n", busno); cmdreg += 4; if (cmdreg == 0x100) { cmdreg = 0; (u32)ptr &= ~0xFFFF; (u32)ptr += 0x800; } else ptr++; } #endif #if 0 printk(KERN_INFO "[%s %d]: PCI Config:\n", __func__, __LINE__); for (cmdreg = 0x7000; cmdreg < 0x7100; cmdreg+=4) { printk(KERN_INFO "\t%#x: ", (u32)cfg_space | cmdreg); printk("%#x\n", le32_to_cpu(READCFG32(cmdreg))); } printk(KERN_INFO "[%s %d]: Do it again\n", __func__, __LINE__); for (cmdreg = 0x7000; cmdreg < 0x7100; cmdreg+=4) { printk(KERN_INFO "\t%#x: ", (u32)cfg_space | cmdreg); printk("%#x\n", le32_to_cpu(READCFG32(cmdreg))); } #endif return 0; } #ifdef USE_FIX_FOR_PCI_PPE /** Brief: disable external pci aribtor request * Details: blocking call, i.e. only return when there is no external PCI bus activities */ void amazon_s_disable_external_pci (void) { BSP_PCI_REG32 (PCI_CR_PC_ARB_REG) |= ((3 << PCI_MASTER2_REQ_MASK_2BITS)); wmb (); /* make sure EBUSY is low && Frame Ird is high) */ while ((BSP_PCI_REG32 (PCI_CR_PC_ARB_REG) & 0x700000) != 0x300000); } /** Brief: enable external pci aribtor request * Details: non-blocking call */ void amazon_s_enable_external_pci (void) { /* enable all external masters request */ BSP_PCI_REG32 (PCI_CR_PC_ARB_REG) &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS)); wmb (); } #endif #if 0 static void __init pci_fixup_amazon_s(struct pci_dev *d) { // pci_bus_error_flag = 0; return; } #endif static void __devinit pcibios_fixup_resources(struct pci_dev *dev) { struct pci_controller* hose = (struct pci_controller *)dev->sysdata; int i; unsigned long offset; #define IFX_PCI_DRV_VERSION "1.0.0" printk(KERN_INFO "Infineon Technologies PCI driver version %s \n", IFX_PCI_DRV_VERSION); if (!hose) { printk(KERN_ERR "No hose for PCI dev %s!\n", pci_name(dev)); return; } for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { struct resource *res = dev->resource + i; if (!res->flags) continue; if (res->end == 0xffffffff) { printk(KERN_INFO "PCI:%s Resource %d [%016llx-%016llx] is unassigned\n", pci_name(dev), i, (u64)res->start, (u64)res->end); res->end -= res->start; res->start = 0; res->flags |= IORESOURCE_UNSET; continue; } offset = 0; if (res->flags & IORESOURCE_MEM) { offset = hose->mem_offset; } else if (res->flags & IORESOURCE_IO) { offset = hose->io_offset; } if (offset != 0) { res->start += offset; res->end += offset; printk(KERN_INFO "Fixup res %d (%lx) of dev %s: %llx -> %llx\n", i, res->flags, pci_name(dev), (u64)res->start - offset, (u64)res->start); } } #ifdef PCI_DEBUG printk(KERN_INFO "[%s %s %d]: %s\n", __FILE__, __func__, __LINE__, pci_name(dev)); #endif /* Enable I/O, MEM, Bus Master, Special Cycles SERR, Fast back-to-back */ pci_write_config_word(dev, PCI_COMMAND, 0x30F); } void __devinit pcibios_fixup_irqs (struct pci_dev *dev) { u8 pin; dev->irq = -1; pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin); switch (pin) { case 0: break; case 1: printk(KERN_INFO "dev %s: interrupt pin 1\n", pci_name(dev)); //PCI_INTA--shared with EBU //falling edge level triggered:0x4, low level:0xc, rising edge:0x2 *BSP_EBU_PCC_CON |= 0xc; /* enable interrupt only */ *BSP_EBU_PCC_IEN |= 0x10; dev->irq = INT_NUM_IM0_IRL22; pci_write_config_byte (dev, PCI_INTERRUPT_LINE, dev->irq); break; case 2: case 3: break; default: printk (KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); break; } } arch_initcall (amazon_s_pcibios_init); DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_irqs);