/*****************************************************************************
 **   FILE NAME       : amazon_s_afe.c
 **   PROJECT         : 
 **   MODULES         : 
 **   SRC VERSION     : 1.0
 **   DATE            : 1/March/2008
 **   AUTHOR          : 
 **   DESCRIPTION     : DSL AFE API
 **   FUNCTIONS       :
 **   COMPILER        : 
 **   REFERENCE       :
 **   COPYRIGHT       :
 **  Version Control Section  **
 **   $Author$
 **   $Date$
 **   $Revisions$
 **   $Log$       Revision history
*****************************************************************************/

/*! \file amamzon_s_afe.c
    \brief DSL AFE API.
*/

#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/ioport.h>

#define ADSL_BASE 0x20000
#define CRI_BASE          0x31F00
#define CRI_CCR0          CRI_BASE + 0x00
#define CRI_CCR1          CRI_BASE + 0x01*4
#define CRI_CDC0          CRI_BASE + 0x02*4
#define CRI_CDC1          CRI_BASE + 0x03*4
#define CRI_RST           CRI_BASE + 0x04*4
#define CRI_MASK0         CRI_BASE + 0x05*4
#define CRI_MASK1         CRI_BASE + 0x06*4
#define CRI_MASK2         CRI_BASE + 0x07*4
#define CRI_STATUS0       CRI_BASE + 0x08*4
#define CRI_STATUS1       CRI_BASE + 0x09*4
#define CRI_STATUS2       CRI_BASE + 0x0A*4
#define CRI_AMASK0        CRI_BASE + 0x0B*4
#define CRI_AMASK1        CRI_BASE + 0x0C*4
#define CRI_UPDCTL        CRI_BASE + 0x0D*4
#define CRI_MADST         CRI_BASE + 0x0E*4
// 0x0f is missing
#define CRI_EVENT0        CRI_BASE + 0x10*4
#define CRI_EVENT1        CRI_BASE + 0x11*4
#define CRI_EVENT2        CRI_BASE + 0x12*4

#define IRI_I_ENABLE    0x32000
#define STY_SMODE       0x3c004
#define AFE_TCR_0       0x3c0dc
#define AFE_ADDR_ADDR   0x3c0e8
#define AFE_RDATA_ADDR  0x3c0ec
#define AFE_WDATA_ADDR  0x3c0f0
#define AFE_CONFIG      0x3c0f4
#define AFE_SERIAL_CFG  0x3c0fc

#define DFE_BASE_ADDR         0xBE116000
//#define DFE_BASE_ADDR         0x9E116000

#define MEI_FR_ARCINT_C       (DFE_BASE_ADDR + 0x0000001C)
#define MEI_DBG_WADDR_C       (DFE_BASE_ADDR + 0x00000024)
#define MEI_DBG_RADDR_C       (DFE_BASE_ADDR + 0x00000028)
#define MEI_DBG_DATA_C        (DFE_BASE_ADDR + 0x0000002C)
#define MEI_DBG_DECO_C        (DFE_BASE_ADDR + 0x00000030)
#define MEI_DBG_MASTER_C      (DFE_BASE_ADDR + 0x0000003C)

/**
   \brief Reads the content of a register.

   \param _reg address of register to read.
   \return contents of the register.

   \code
   Usage:
   uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);
   \endcode
 */
static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *_reg)
{
        return (*(_reg));
};

void WriteARCmem(uint32_t addr, uint32_t data)
{
	writel(1    ,(volatile uint32_t *)MEI_DBG_MASTER_C);
	writel(1    ,(volatile uint32_t *)MEI_DBG_DECO_C  );
	writel(addr ,(volatile uint32_t *)MEI_DBG_WADDR_C  );
	writel(data ,(volatile uint32_t *)MEI_DBG_DATA_C  );
	while( (dwc_read_reg32((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){};
	writel(0    ,(volatile uint32_t *)MEI_DBG_MASTER_C);
	//printk(KERN_INFO "WriteARCmem %08x %08x\n",addr,data);
};

uint32_t ReadARCmem(uint32_t addr)
{
	u32 data;
	writel(1    ,(volatile uint32_t *)MEI_DBG_MASTER_C);
	writel(1    ,(volatile uint32_t *)MEI_DBG_DECO_C  );
	writel(addr ,(volatile uint32_t *)MEI_DBG_RADDR_C  );
	while( (dwc_read_reg32((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){};
	data = dwc_read_reg32((volatile uint32_t *)MEI_DBG_DATA_C  );
	writel(0    ,(volatile uint32_t *)MEI_DBG_MASTER_C);
	//printk(KERN_INFO "ReadARCmem %08x %08x\n",addr,data);
	return data;
};

void ifx_enable_afe_oc(void)
{
	/* Start the clock */
	WriteARCmem(CRI_UPDCTL    ,0x00000008);
	WriteARCmem(CRI_CCR0      ,0x00000014);
	WriteARCmem(CRI_CCR1      ,0x00000500);
	WriteARCmem(AFE_CONFIG    ,0x000001c8);
	WriteARCmem(AFE_SERIAL_CFG,0x00000016); // (DANUBE_PCI_CFG_BASE+(1<<addrline))AFE serial interface clock & data latch edge
	WriteARCmem(AFE_TCR_0     ,0x00000002);
	//Take afe out of reset
	WriteARCmem(AFE_CONFIG    ,0x000000c0);
	WriteARCmem(IRI_I_ENABLE  ,0x00000101);
	WriteARCmem(STY_SMODE     ,0x00001980);

	ReadARCmem(CRI_UPDCTL    );
	ReadARCmem(CRI_CCR0      );
	ReadARCmem(CRI_CCR1      );
	ReadARCmem(AFE_CONFIG    );
	ReadARCmem(AFE_SERIAL_CFG); // (DANUBE_PCI_CFG_BASE+(1<<addrline))AFE serial interface clock & data latch edge
	ReadARCmem(AFE_TCR_0     );
	ReadARCmem(AFE_CONFIG    );
	ReadARCmem(IRI_I_ENABLE  );
	ReadARCmem(STY_SMODE     );
}
EXPORT_SYMBOL(ifx_enable_afe_oc);

int __init afe_init(void)
{
    ifx_enable_afe_oc();

	return 0;
}

void __exit afe_exit(void)
{
}

module_init(afe_init);
module_exit(afe_exit);