#ifndef _TFFS_DIRECT_NAND_EBU_H_ #define _TFFS_DIRECT_NAND_EBU_H_ union _ebu_clc { volatile unsigned int Register; struct __ebu_clc { volatile unsigned int reserved : 30; volatile unsigned int diss : 1; volatile unsigned int disr : 1; } Bits; }; union _ebu_id { volatile unsigned int Register; struct __ebu_id { volatile unsigned int modnum : 24; volatile unsigned int revnum : 8; } Bits; }; union _ebu_con { volatile unsigned int Register; struct __ebu_con { volatile unsigned int reserved : 3; volatile unsigned int clk_dly : 6; volatile unsigned int dtacs : 3; volatile unsigned int reserved1 : 1; volatile unsigned int dtarw : 3; volatile unsigned int toutc : 8; volatile unsigned int arbmode : 2; volatile unsigned int arbsync : 1; volatile unsigned int reserved2 : 5; } Bits; }; union _ebu_addr_sel { volatile unsigned int Register; struct __ebu_addr_sel { volatile unsigned int base : 20; volatile unsigned int reserved : 4; volatile unsigned int mask : 4; volatile unsigned int reserved1 : 2; volatile unsigned int mrme : 1; volatile unsigned int regen : 1; #define AR9_EBU_ADDRESS_SELECT_REGISTER_MRME (1 << 1 ) #define AR9_EBU_ADDRESS_SELECT_REGISTER_REGEN (1 << 0 ) #define AR9_EBU_ADDRESS_SELECT_REGISTER_BASE(x) ((x) << 12) #define AR9_EBU_ADDRESS_SELECT_REGISTER_MASK(x) ((x) << 4 ) } Bits; }; union _ebu_conf { volatile unsigned int Register; struct __ebu_conf { volatile unsigned int wrdis : 1; volatile unsigned int adswp : 1; volatile unsigned int pg_en : 1; volatile unsigned int reserved : 2; volatile unsigned int agen : 3; volatile unsigned int reserved1 : 1; volatile unsigned int setup : 1; volatile unsigned int wait : 2; volatile unsigned int winv : 1; volatile unsigned int vn_en : 1; volatile unsigned int pw : 2; volatile unsigned int alec : 2; volatile unsigned int bcgen : 2; volatile unsigned int reserved2 : 1; volatile unsigned int waitwrc : 3; volatile unsigned int waitrdc : 2; volatile unsigned int holdc : 2; volatile unsigned int recovc : 2; volatile unsigned int cmult : 2; } Bits; #define AR9_EBU_CONFIGURATION_REGISTER_WRDIS (1 << 31) #define AR9_EBU_CONFIGURATION_REGISTER_ADSWP (1 << 30) #define AR9_EBU_CONFIGURATION_REGISTER_PG_EN (1 << 29) #define AR9_EBU_CONFIGURATION_REGISTER_SETUP (1 << 22) #define AR9_EBU_CONFIGURATION_REGISTER_WINV (1 << 19) #define AR9_EBU_CONFIGURATION_REGISTER_VN_EN (1 << 18) #define AR9_EBU_CONFIGURATION_REGISTER_AGEN(x) ((x) << 24) #define AR9_EBU_CONFIGURATION_REGISTER_WAIT(x) ((x) << 20) #define AR9_EBU_CONFIGURATION_REGISTER_PW(x) ((x) << 16) #define AR9_EBU_CONFIGURATION_REGISTER_ALEC(x) ((x) << 14) #define AR9_EBU_CONFIGURATION_REGISTER_BCGEN(x) ((x) << 12) #define AR9_EBU_CONFIGURATION_REGISTER_WAITWRC(x) ((x) << 8 ) #define AR9_EBU_CONFIGURATION_REGISTER_WAITRDC(x) ((x) << 6 ) #define AR9_EBU_CONFIGURATION_REGISTER_HOLDC(x) ((x) << 4 ) #define AR9_EBU_CONFIGURATION_REGISTER_RECOVC(x) ((x) << 2 ) #define AR9_EBU_CONFIGURATION_REGISTER_CMULT(x) ((x) << 0 ) }; union _ebu_syn_conf { volatile unsigned int Register; struct __ebu_syn_conf { volatile unsigned int cs3_mm : 1; volatile unsigned int sync3_rl : 4; volatile unsigned int sync3_wl : 4; volatile unsigned int sync3sz : 2; volatile unsigned int sync3eg : 2; volatile unsigned int sync3_clk : 2; volatile unsigned int ebusync3 : 1; volatile unsigned int cs2_mm : 1; volatile unsigned int sync2_rl : 4; volatile unsigned int sync2_wl : 4; volatile unsigned int sync2sz : 2; volatile unsigned int sync2eg : 2; volatile unsigned int syn0_clk : 2; volatile unsigned int ebusync2 : 1; } Bits; }; union _ebu_nand_con { volatile unsigned int Register; struct __ebu_nand_con { volatile unsigned int ecc_on : 1; volatile unsigned int reserved : 7; volatile unsigned int lat_en : 6; volatile unsigned int reserved1 : 6; volatile unsigned int out_cs_s : 2; volatile unsigned int in_cs_s : 2; volatile unsigned int pre_p : 1; volatile unsigned int wp_p : 1; volatile unsigned int se_p : 1; volatile unsigned int cs_p : 1; volatile unsigned int cle_p : 1; volatile unsigned int ale_p : 1; volatile unsigned int csmux_e : 1; volatile unsigned int nandm : 1; } Bits; }; union _ebu_nand_wait { volatile unsigned int Register; struct __ebu_nand_wait { volatile unsigned int reserved : 28; volatile unsigned int wr_c : 1; volatile unsigned int rd_e : 1; volatile unsigned int by_e : 1; volatile unsigned int rd_by : 1; } Bits; }; union _ebu_nand_ecc { volatile unsigned int Register; struct __ebu_nand_ecc { volatile unsigned int reserved : 8; volatile unsigned int ecc_b2 : 8; volatile unsigned int ecc_b1 : 8; volatile unsigned int ecc_b0 : 8; } Bits; }; union _ebu_nand_ecc_ac { volatile unsigned int Register; struct __ebu_nand_ecc_ac { volatile unsigned int reserved : 23; volatile unsigned int ecc_ac : 9; } Bits; }; union _ebu_nand_ecc_cr { volatile unsigned int Register; struct __ebu_nand_ecc_cr { volatile unsigned int ecc_crm : 1; volatile unsigned int reserved : 15; volatile unsigned int ecc_pg : 2; volatile unsigned int ecc_crr : 9; volatile unsigned int ecc_crb : 3; volatile unsigned int ecc_cr : 2; } Bits; }; struct ebu_register { union _ebu_clc clc; unsigned int reserved_0x4; /*--- 0x04 ---*/ union _ebu_id id; unsigned int reserved_0xc; /*--- 0x0c ---*/ union _ebu_con con; unsigned int reserved_0x14[3]; /*--- 0x0c ---*/ union _ebu_addr_sel addr_sel0; union _ebu_addr_sel addr_sel1; union _ebu_addr_sel addr_sel2; union _ebu_addr_sel addr_sel3; unsigned int reserved_0x30[(0x60-0x30)/4]; /*--- 0x0C ---*/ union _ebu_conf con0; union _ebu_conf con1; union _ebu_conf con2; union _ebu_conf con3; unsigned int reserved_0x70[(0x8C-0x70)/4]; /*--- 0x0C ---*/ union _ebu_syn_conf syn_con; unsigned int reserved_0x90[(0xB0-0x90)/4]; /*--- 0x0C ---*/ union _ebu_nand_con nand_con; union _ebu_nand_wait nand_wait; union _ebu_nand_ecc nand_ecc; union _ebu_nand_ecc_ac nand_ecc_ac; union _ebu_nand_ecc_cr nand_ecc_cr; }; #endif /*--- #ifndef _TFFS_DIRECT_NAND_EBU_H_ ---*/