/*-------------------------------------------------------------------------------------*\

    $Header$

    $Id$

    $Log$

\*-------------------------------------------------------------------------------------*/
#include <linux/kernel.h>
#include <linux/delay.h>
#include <asm/arch/puma5_hardware.h>
#include <asm/arch/puma5.h>
#include <mach/gpio.h>
#include "cpswhalcommon_stddef.h"
#include "cpswhalcommon_miimdio_regs.h"
#include "cslr_cpgmac_f.h"
#include "mdio.h"
#include "ath_phy.h"
#if defined(CONFIG_AVM_CPMAC) && CONFIG_AVM_CPMAC
#include "../avm_cpmac/cpmac_puma_if.h"
#endif /*--- #if defined(CONFIG_AVM_CPMAC) && CONFIG_AVM_CPMAC ---*/

/*--- #define DEBUG_CPMAC ---*/
/*--- #define DBG_CPMAC(args...)      printk(args) ---*/
#define DBG_CPMAC(args...)

#define CONFIG_SWITCH_8316 1

typedef struct _phy_device PHY_DEVICE;
extern bit32u _cpswHalCommonMiiMdioUserAccessRead (PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr);
extern void   _cpswHalCommonMiiMdioUserAccessWrite(PHY_DEVICE *PhyDev, bit32u regadr, bit32u phyadr, bit32u data);

/*--- ein paar Register- Definitionen ---*/
struct mdio_regs         *MDIO       = (struct mdio_regs *)&(*(volatile unsigned int *)AVALANCHE_MDIO_BASE);
/*--- struct cpgmac_f_regs     *CPGMAC_F   = NULL; ---*/


#define ARM_PLLDIV4_OFFSET 0x160
#define MHZ(x) ((x) * 1000 * 1000)
#define AVALANCHE_ARM_PLL_BASE (IO_ADDRESS(0x08620000))
#define ARM_PLLM_OFFSET 0x110
/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
unsigned int GetPLLClock(unsigned int pll_offset) {
    unsigned int pllmul = *((volatile unsigned int *)(AVALANCHE_ARM_PLL_BASE+ARM_PLLM_OFFSET)) & 0x3F;
    unsigned int plldiv = *((volatile unsigned int *)(AVALANCHE_ARM_PLL_BASE+pll_offset)) & 0x1F;
    return (((pllmul+1) * MHZ(25)) / (plldiv+1));
}

/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
unsigned int GetSystem_Clock(void) {
    return GetPLLClock(ARM_PLLDIV4_OFFSET);
}

extern void cpmac_puma_printk(const char *text, unsigned int line);
/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
void puma_mdio_write(void *phy_dev, 
                     unsigned short regadr,
                     unsigned short phyadr,
                     unsigned short value) {
    _cpswHalCommonMiiMdioUserAccessWrite((PHY_DEVICE *) phy_dev,
                                         (bit32u) regadr,
                                         (bit32u) phyadr,
                                         (bit32u) value);
}

/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
unsigned int puma_mdio_read(void *phy_dev, unsigned short address, unsigned short phy) {
    return _cpswHalCommonMiiMdioUserAccessRead((PHY_DEVICE *) phy_dev, 
                                               (bit32u)       address, 
                                               (bit32u)       phy);
}


/*------------------------------------------------------------------------------------------*\
 * Performs output voltage amplitude adjustments as per ET1011C errata. 
 * Note : Expects PHY to be in FOUND state
\*------------------------------------------------------------------------------------------*/
#if !defined(CONFIG_SWITCH_8316)
void _fixup_et1011c_phy (unsigned int PhyNum) {

    unsigned short tmp;
    DBG_CPMAC("Setting PHY %d registers as per ET1011C errata...\n", PhyNum);

    /*--- MdioSetBits (PhyNum, 0, 11); ---*/
    tmp = puma_mdio_read(PhyNum, 0);
    puma_mdio_write(PhyNum, 0, tmp | 11);

    /*--- MdioSetBits (PhyNum, 18, (1<<2)); ---*/
    tmp = puma_mdio_read(PhyNum, 18);
    puma_mdio_write(PhyNum, 18, tmp | (1<<2));

    puma_mdio_write(PhyNum, 16, 0x8805);
    puma_mdio_write(PhyNum, 17, 0xF03E);
    puma_mdio_write(PhyNum, 16, 0x8806);
    puma_mdio_write(PhyNum, 17, 0x003E);
    puma_mdio_write(PhyNum, 16, 0x8807);
    puma_mdio_write(PhyNum, 17, 0x1F00);

    /*--- MdioClearBits (PhyNum, 18, (1<<2)); ---*/
    tmp = puma_mdio_read(PhyNum, 18);
    puma_mdio_write(PhyNum, 18, tmp & ~(1<<2));

    /*--- MdioClearBits (PhyNum, 0, 11); ---*/
    tmp = puma_mdio_read(PhyNum, 0);
    puma_mdio_write(PhyNum, 0, tmp & ~11);

    return;
}
#endif /*--- #if !defined(CONFIG_SWITCH_8316) ---*/


/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
void cpmac_puma_set_port_speed(unsigned char port,
                               unsigned char speed,
                               unsigned char fullduplex) {
    CSL_Cpgmac_f_RegsOvly regs;
    switch(port) {
        case 0:
            regs = (CSL_Cpgmac_f_RegsOvly) AVALANCHE_LOW_CPMAC_BASE;
            break;
        case 1:
            regs = (CSL_Cpgmac_f_RegsOvly) AVALANCHE_HIGH_CPMAC_BASE;
            break;
        default:
            printk(KERN_ERR "[%s] There are only two ports on Puma!\n", __FUNCTION__);
            break;
    }
    switch(speed) {
        case 0:
        case 1:
            regs->MacControl &= ~(CSL_CPMAC_MACCONTROL_GIGABITEN_MASK);
            regs->MacControl &= ~(CSL_CPMAC_MACCONTROL_GIGFORCE_MASK);
            break;
        case 2:
        default:
            regs->MacControl |= CSL_CPMAC_MACCONTROL_GIGABITEN_MASK;
            regs->MacControl |= CSL_CPMAC_MACCONTROL_GIGFORCE_MASK;
            break;
    }
}