/****************************************************************************

                              Copyright (c) 2010
                            Lantiq Deutschland GmbH
                     Am Campeon 3; 85579 Neubiberg, Germany

  For licensing information, see the file 'LICENSE' in the root folder of
  this software module.

 *****************************************************************************
   \file ifx_ethsw_flow_ll_table.c
   \remarks
             Switch API low level function tables.
             Maps the IOCTL commands on the low level functions.
*****************************************************************************/
#include "ifx_types.h"
#include "switch_api/ifx_ethsw_flow_ll.h"
#include "switch_api/ifx_ethsw_ll_fkt.h"

IFX_ll_fkt ifx_ethsw_FLOW_fkt_ptr_tbl [] =
{
   (IFX_ll_fkt) IFX_NULL, /* 0x00 */
   (IFX_ll_fkt) IFX_FLOW_MAC_TableEntryRead, /* 0x01 */
   (IFX_ll_fkt) IFX_FLOW_MAC_TableEntryAdd, /* 0x02 */
   (IFX_ll_fkt) IFX_FLOW_MAC_TableEntryRemove, /* 0x03 */
   (IFX_ll_fkt) IFX_FLOW_MAC_TableClear, /* 0x04 */
   (IFX_ll_fkt) IFX_FLOW_PortCfgGet, /* 0x05 */
   (IFX_ll_fkt) IFX_FLOW_PortCfgSet, /* 0x06 */
   (IFX_ll_fkt) IFX_FLOW_STP_PortCfgSet, /* 0x07 */
   (IFX_ll_fkt) IFX_FLOW_STP_PortCfgGet, /* 0x08 */
   (IFX_ll_fkt) IFX_FLOW_STP_BPDU_RuleSet, /* 0x09 */
   (IFX_ll_fkt) IFX_FLOW_STP_BPDU_RuleGet, /* 0x0A */
   (IFX_ll_fkt) IFX_FLOW_VLAN_ReservedAdd, /* 0x0B */
   (IFX_ll_fkt) IFX_FLOW_VLAN_ReservedRemove, /* 0x0C */
   (IFX_ll_fkt) IFX_FLOW_VLAN_PortCfgGet, /* 0x0D */
   (IFX_ll_fkt) IFX_FLOW_VLAN_PortCfgSet, /* 0x0E */
   (IFX_ll_fkt) IFX_FLOW_VLAN_IdCreate, /* 0x0F */
   (IFX_ll_fkt) IFX_FLOW_VLAN_IdDelete, /* 0x10 */
   (IFX_ll_fkt) IFX_FLOW_VLAN_PortMemberAdd, /* 0x11 */
   (IFX_ll_fkt) IFX_FLOW_VLAN_PortMemberRemove, /* 0x12 */
   (IFX_ll_fkt) IFX_FLOW_VLAN_IdGet, /* 0x13 */
   (IFX_ll_fkt) IFX_FLOW_QoS_PortCfgSet, /* 0x14 */
   (IFX_ll_fkt) IFX_FLOW_QoS_PortCfgGet, /* 0x15 */
   (IFX_ll_fkt) IFX_FLOW_QoS_DSCP_ClassSet, /* 0x16 */
   (IFX_ll_fkt) IFX_FLOW_QoS_DSCP_ClassGet, /* 0x17 */
   (IFX_ll_fkt) IFX_FLOW_QoS_PCP_ClassSet, /* 0x18 */
   (IFX_ll_fkt) IFX_FLOW_QoS_PCP_ClassGet, /* 0x19 */
   (IFX_ll_fkt) IFX_FLOW_QoS_DSCP_DropPrecedenceCfgSet, /* 0x1A */
   (IFX_ll_fkt) IFX_FLOW_QoS_DSCP_DropPrecedenceCfgGet, /* 0x1B */
   (IFX_ll_fkt) IFX_FLOW_QoS_PortRemarkingCfgSet, /* 0x1C */
   (IFX_ll_fkt) IFX_FLOW_QoS_PortRemarkingCfgGet, /* 0x1D */
   (IFX_ll_fkt) IFX_FLOW_QoS_ClassDSCP_Set, /* 0x1E */
   (IFX_ll_fkt) IFX_FLOW_QoS_ClassDSCP_Get, /* 0x1F */
   (IFX_ll_fkt) IFX_FLOW_QoS_ClassPCP_Set, /* 0x20 */
   (IFX_ll_fkt) IFX_FLOW_QoS_ClassPCP_Get, /* 0x21 */
   (IFX_ll_fkt) IFX_FLOW_QoS_ShaperCfgSet, /* 0x22 */
   (IFX_ll_fkt) IFX_FLOW_QoS_ShaperCfgGet, /* 0x23 */
   (IFX_ll_fkt) IFX_FLOW_QoS_ShaperQueueAssign, /* 0x24 */
   (IFX_ll_fkt) IFX_FLOW_QoS_ShaperQueueDeassign, /* 0x25 */
   (IFX_ll_fkt) IFX_FLOW_QoS_WredCfgSet, /* 0x26 */
   (IFX_ll_fkt) IFX_FLOW_QoS_WredCfgGet, /* 0x27 */
   (IFX_ll_fkt) IFX_FLOW_QoS_WredQueueCfgSet, /* 0x28 */
   (IFX_ll_fkt) IFX_FLOW_QoS_WredQueueCfgGet, /* 0x29 */
   (IFX_ll_fkt) IFX_FLOW_QoS_MeterCfgSet, /* 0x2A */
   (IFX_ll_fkt) IFX_FLOW_QoS_MeterCfgGet, /* 0x2B */
   (IFX_ll_fkt) IFX_FLOW_QoS_MeterPortAssign, /* 0x2C */
   (IFX_ll_fkt) IFX_FLOW_QoS_MeterPortDeassign, /* 0x2D */
   (IFX_ll_fkt) IFX_FLOW_QoS_MeterPortGet, /* 0x2E */
   (IFX_ll_fkt) IFX_FLOW_QoS_StormAdd, /* 0x2F */
   (IFX_ll_fkt) IFX_FLOW_QoS_StormRemove, /* 0x30 */
   (IFX_ll_fkt) IFX_FLOW_QoS_StormCfgGet, /* 0x31 */
   (IFX_ll_fkt) IFX_FLOW_QoS_SchedulerCfgSet, /* 0x32 */
   (IFX_ll_fkt) IFX_FLOW_QoS_SchedulerCfgGet, /* 0x33 */
   (IFX_ll_fkt) IFX_FLOW_QoS_QueuePortSet, /* 0x34 */
   (IFX_ll_fkt) IFX_FLOW_QoS_QueuePortGet, /* 0x35 */
   (IFX_ll_fkt) IFX_FLOW_MulticastSnoopCfgSet, /* 0x36 */
   (IFX_ll_fkt) IFX_FLOW_MulticastSnoopCfgGet, /* 0x37 */
   (IFX_ll_fkt) IFX_FLOW_MulticastRouterPortAdd, /* 0x38 */
   (IFX_ll_fkt) IFX_FLOW_MulticastRouterPortRemove, /* 0x39 */
   (IFX_ll_fkt) IFX_FLOW_MulticastRouterPortRead, /* 0x3A */
   (IFX_ll_fkt) IFX_FLOW_MulticastTableEntryAdd, /* 0x3B */
   (IFX_ll_fkt) IFX_FLOW_MulticastTableEntryRemove, /* 0x3C */
   (IFX_ll_fkt) IFX_FLOW_MulticastTableEntryRead, /* 0x3D */
   (IFX_ll_fkt) IFX_FLOW_HW_Init, /* 0x3E */
   (IFX_ll_fkt) IFX_FLOW_VersionGet, /* 0x3F */
   (IFX_ll_fkt) IFX_FLOW_CapGet, /* 0x40 */
   (IFX_ll_fkt) IFX_FLOW_CfgSet, /* 0x41 */
   (IFX_ll_fkt) IFX_FLOW_CfgGet, /* 0x42 */
   (IFX_ll_fkt) IFX_FLOW_Enable, /* 0x43 */
   (IFX_ll_fkt) IFX_FLOW_Disable, /* 0x44 */
   (IFX_ll_fkt) IFX_FLOW_CPU_PortCfgSet, /* 0x45 */
   (IFX_ll_fkt) IFX_FLOW_CPU_PortCfgGet, /* 0x46 */
   (IFX_ll_fkt) IFX_FLOW_CPU_PortExtendCfgSet, /* 0x47 */
   (IFX_ll_fkt) IFX_FLOW_CPU_PortExtendCfgGet, /* 0x48 */
   (IFX_ll_fkt) IFX_FLOW_PortLinkCfgGet, /* 0x49 */
   (IFX_ll_fkt) IFX_FLOW_PortLinkCfgSet, /* 0x4A */
   (IFX_ll_fkt) IFX_FLOW_PortRGMII_ClkCfgSet, /* 0x4B */
   (IFX_ll_fkt) IFX_FLOW_PortRGMII_ClkCfgGet, /* 0x4C */
   (IFX_ll_fkt) IFX_FLOW_PortPHY_Query, /* 0x4D */
   (IFX_ll_fkt) IFX_FLOW_PortPHY_AddrGet, /* 0x4E */
   (IFX_ll_fkt) IFX_FLOW_PortRedirectGet, /* 0x4F */
   (IFX_ll_fkt) IFX_FLOW_PortRedirectSet, /* 0x50 */
   (IFX_ll_fkt) IFX_FLOW_MonitorPortCfgGet, /* 0x51 */
   (IFX_ll_fkt) IFX_FLOW_MonitorPortCfgSet, /* 0x52 */
   (IFX_ll_fkt) IFX_FLOW_RMON_Get, /* 0x53 */
   (IFX_ll_fkt) IFX_FLOW_RMON_Clear, /* 0x54 */
   (IFX_ll_fkt) IFX_FLOW_MDIO_CfgGet, /* 0x55 */
   (IFX_ll_fkt) IFX_FLOW_MDIO_CfgSet, /* 0x56 */
   (IFX_ll_fkt) IFX_FLOW_MDIO_DataRead, /* 0x57 */
   (IFX_ll_fkt) IFX_FLOW_MDIO_DataWrite, /* 0x58 */
   (IFX_ll_fkt) IFX_FLOW_WoL_CfgSet, /* 0x59 */
   (IFX_ll_fkt) IFX_FLOW_WoL_CfgGet, /* 0x5A */
   (IFX_ll_fkt) IFX_FLOW_WoL_PortCfgSet, /* 0x5B */
   (IFX_ll_fkt) IFX_FLOW_WoL_PortCfgGet, /* 0x5C */
   (IFX_ll_fkt) IFX_FLOW_8021X_EAPOL_RuleGet, /* 0x5D */
   (IFX_ll_fkt) IFX_FLOW_8021X_EAPOL_RuleSet, /* 0x5E */
   (IFX_ll_fkt) IFX_FLOW_8021X_PortCfgGet, /* 0x5F */
   (IFX_ll_fkt) IFX_FLOW_8021X_PortCfgSet /* 0x60 */
};

#if 0
IFX_uint32_t ifx_ethsw_FLOW_ioctl_tbl [] =
{
   (IFX_uint32_t) 0, /* 0x00 */
   (IFX_uint32_t) IFX_ETHSW_MAC_TABLE_ENTRY_READ, /* 0x01 */
   (IFX_uint32_t) IFX_ETHSW_MAC_TABLE_ENTRY_ADD, /* 0x02 */
   (IFX_uint32_t) IFX_ETHSW_MAC_TABLE_ENTRY_REMOVE, /* 0x03 */
   (IFX_uint32_t) IFX_ETHSW_MAC_TABLE_CLEAR, /* 0x04 */
   (IFX_uint32_t) IFX_ETHSW_PORT_CFG_GET, /* 0x05 */
   (IFX_uint32_t) IFX_ETHSW_PORT_CFG_SET, /* 0x06 */
   (IFX_uint32_t) IFX_ETHSW_STP_PORT_CFG_SET, /* 0x07 */
   (IFX_uint32_t) IFX_ETHSW_STP_PORT_CFG_GET, /* 0x08 */
   (IFX_uint32_t) IFX_ETHSW_STP_BPDU_RULE_SET, /* 0x09 */
   (IFX_uint32_t) IFX_ETHSW_STP_BPDU_RULE_GET, /* 0x0A */
   (IFX_uint32_t) IFX_ETHSW_VLAN_RESERVED_ADD, /* 0x0B */
   (IFX_uint32_t) IFX_ETHSW_VLAN_RESERVED_REMOVE, /* 0x0C */
   (IFX_uint32_t) IFX_ETHSW_VLAN_PORT_CFG_GET, /* 0x0D */
   (IFX_uint32_t) IFX_ETHSW_VLAN_PORT_CFG_SET, /* 0x0E */
   (IFX_uint32_t) IFX_ETHSW_VLAN_ID_CREATE, /* 0x0F */
   (IFX_uint32_t) IFX_ETHSW_VLAN_ID_DELETE, /* 0x10 */
   (IFX_uint32_t) IFX_ETHSW_VLAN_PORT_MEMBER_ADD, /* 0x11 */
   (IFX_uint32_t) IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE, /* 0x12 */
   (IFX_uint32_t) IFX_ETHSW_VLAN_ID_GET, /* 0x13 */
   (IFX_uint32_t) IFX_ETHSW_QOS_PORT_CFG_SET, /* 0x14 */
   (IFX_uint32_t) IFX_ETHSW_QOS_PORT_CFG_GET, /* 0x15 */
   (IFX_uint32_t) IFX_ETHSW_QOS_DSCP_CLASS_SET, /* 0x16 */
   (IFX_uint32_t) IFX_ETHSW_QOS_DSCP_CLASS_GET, /* 0x17 */
   (IFX_uint32_t) IFX_ETHSW_QOS_PCP_CLASS_SET, /* 0x18 */
   (IFX_uint32_t) IFX_ETHSW_QOS_PCP_CLASS_GET, /* 0x19 */
   (IFX_uint32_t) IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_SET, /* 0x1A */
   (IFX_uint32_t) IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_GET, /* 0x1B */
   (IFX_uint32_t) IFX_ETHSW_QOS_PORT_REMARKING_CFG_SET, /* 0x1C */
   (IFX_uint32_t) IFX_ETHSW_QOS_PORT_REMARKING_CFG_GET, /* 0x1D */
   (IFX_uint32_t) IFX_ETHSW_QOS_CLASS_DSCP_SET, /* 0x1E */
   (IFX_uint32_t) IFX_ETHSW_QOS_CLASS_DSCP_GET, /* 0x1F */
   (IFX_uint32_t) IFX_ETHSW_QOS_CLASS_PCP_SET, /* 0x20 */
   (IFX_uint32_t) IFX_ETHSW_QOS_CLASS_PCP_GET, /* 0x21 */
   (IFX_uint32_t) IFX_ETHSW_QOS_SHAPER_CFG_SET, /* 0x22 */
   (IFX_uint32_t) IFX_ETHSW_QOS_SHAPER_CFG_GET, /* 0x23 */
   (IFX_uint32_t) IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN, /* 0x24 */
   (IFX_uint32_t) IFX_ETHSW_QOS_SHAPER_QUEUE_DEASSIGN, /* 0x25 */
   (IFX_uint32_t) IFX_ETHSW_QOS_WRED_CFG_SET, /* 0x26 */
   (IFX_uint32_t) IFX_ETHSW_QOS_WRED_CFG_GET, /* 0x27 */
   (IFX_uint32_t) IFX_ETHSW_QOS_WRED_QUEUE_CFG_SET, /* 0x28 */
   (IFX_uint32_t) IFX_ETHSW_QOS_WRED_QUEUE_CFG_GET, /* 0x29 */
   (IFX_uint32_t) IFX_ETHSW_QOS_METER_CFG_SET, /* 0x2A */
   (IFX_uint32_t) IFX_ETHSW_QOS_METER_CFG_GET, /* 0x2B */
   (IFX_uint32_t) IFX_ETHSW_QOS_METER_PORT_ASSIGN, /* 0x2C */
   (IFX_uint32_t) IFX_ETHSW_QOS_METER_PORT_DEASSIGN, /* 0x2D */
   (IFX_uint32_t) IFX_ETHSW_QOS_METER_PORT_GET, /* 0x2E */
   (IFX_uint32_t) IFX_ETHSW_QOS_STORM_ADD, /* 0x2F */
   (IFX_uint32_t) IFX_ETHSW_QOS_STORM_REMOVE, /* 0x30 */
   (IFX_uint32_t) IFX_ETHSW_QOS_STORM_CFG_GET, /* 0x31 */
   (IFX_uint32_t) IFX_ETHSW_QOS_SCHEDULER_CFG_SET, /* 0x32 */
   (IFX_uint32_t) IFX_ETHSW_QOS_SCHEDULER_CFG_GET, /* 0x33 */
   (IFX_uint32_t) IFX_ETHSW_QOS_QUEUE_PORT_SET, /* 0x34 */
   (IFX_uint32_t) IFX_ETHSW_QOS_QUEUE_PORT_GET, /* 0x35 */
   (IFX_uint32_t) IFX_ETHSW_MULTICAST_SNOOP_CFG_SET, /* 0x36 */
   (IFX_uint32_t) IFX_ETHSW_MULTICAST_SNOOP_CFG_GET, /* 0x37 */
   (IFX_uint32_t) IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD, /* 0x38 */
   (IFX_uint32_t) IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE, /* 0x39 */
   (IFX_uint32_t) IFX_ETHSW_MULTICAST_ROUTER_PORT_READ, /* 0x3A */
   (IFX_uint32_t) IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD, /* 0x3B */
   (IFX_uint32_t) IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE, /* 0x3C */
   (IFX_uint32_t) IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ, /* 0x3D */
   (IFX_uint32_t) IFX_ETHSW_HW_INIT, /* 0x3E */
   (IFX_uint32_t) IFX_ETHSW_VERSION_GET, /* 0x3F */
   (IFX_uint32_t) IFX_ETHSW_CAP_GET, /* 0x40 */
   (IFX_uint32_t) IFX_ETHSW_CFG_SET, /* 0x41 */
   (IFX_uint32_t) IFX_ETHSW_CFG_GET, /* 0x42 */
   (IFX_uint32_t) IFX_ETHSW_ENABLE, /* 0x43 */
   (IFX_uint32_t) IFX_ETHSW_DISABLE, /* 0x44 */
   (IFX_uint32_t) IFX_ETHSW_CPU_PORT_CFG_SET, /* 0x45 */
   (IFX_uint32_t) IFX_ETHSW_CPU_PORT_CFG_GET, /* 0x46 */
   (IFX_uint32_t) IFX_ETHSW_CPU_PORT_EXTEND_CFG_SET, /* 0x47 */
   (IFX_uint32_t) IFX_ETHSW_CPU_PORT_EXTEND_CFG_GET, /* 0x48 */
   (IFX_uint32_t) IFX_ETHSW_PORT_LINK_CFG_GET, /* 0x49 */
   (IFX_uint32_t) IFX_ETHSW_PORT_LINK_CFG_SET, /* 0x4A */
   (IFX_uint32_t) IFX_ETHSW_PORT_RGMII_CLK_CFG_SET, /* 0x4B */
   (IFX_uint32_t) IFX_ETHSW_PORT_RGMII_CLK_CFG_GET, /* 0x4C */
   (IFX_uint32_t) IFX_ETHSW_PORT_PHY_QUERY, /* 0x4D */
   (IFX_uint32_t) IFX_ETHSW_PORT_PHY_ADDR_GET, /* 0x4E */
   (IFX_uint32_t) IFX_ETHSW_PORT_REDIRECT_GET, /* 0x4F */
   (IFX_uint32_t) IFX_ETHSW_PORT_REDIRECT_SET, /* 0x50 */
   (IFX_uint32_t) IFX_ETHSW_MONITOR_PORT_CFG_GET, /* 0x51 */
   (IFX_uint32_t) IFX_ETHSW_MONITOR_PORT_CFG_SET, /* 0x52 */
   (IFX_uint32_t) IFX_ETHSW_RMON_GET, /* 0x53 */
   (IFX_uint32_t) IFX_ETHSW_RMON_CLEAR, /* 0x54 */
   (IFX_uint32_t) IFX_ETHSW_MDIO_CFG_GET, /* 0x55 */
   (IFX_uint32_t) IFX_ETHSW_MDIO_CFG_SET, /* 0x56 */
   (IFX_uint32_t) IFX_ETHSW_MDIO_DATA_READ, /* 0x57 */
   (IFX_uint32_t) IFX_ETHSW_MDIO_DATA_WRITE, /* 0x58 */
   (IFX_uint32_t) IFX_ETHSW_WOL_CFG_SET, /* 0x59 */
   (IFX_uint32_t) IFX_ETHSW_WOL_CFG_GET, /* 0x5A */
   (IFX_uint32_t) IFX_ETHSW_WOL_PORT_CFG_SET, /* 0x5B */
   (IFX_uint32_t) IFX_ETHSW_WOL_PORT_CFG_GET, /* 0x5C */
   (IFX_uint32_t) IFX_ETHSW_8021X_EAPOL_RULE_GET, /* 0x5D */
   (IFX_uint32_t) IFX_ETHSW_8021X_EAPOL_RULE_SET, /* 0x5E */
   (IFX_uint32_t) IFX_ETHSW_8021X_PORT_CFG_GET, /* 0x5F */
   (IFX_uint32_t) IFX_ETHSW_8021X_PORT_CFG_SET /* 0x60 */
};
#endif

IFX_ETHSW_lowLevelFkts_t ifx_ethsw_FLOW_fkt_tbl =
{
   IFX_NULL , /* pNext */
   (IFX_uint16_t) IFX_ETHSW_MAGIC , /* nType */
   97 , /* nNumFkts */
 //  ifx_ethsw_FLOW_ioctl_tbl , /* IOCTL Table */
   ifx_ethsw_FLOW_fkt_ptr_tbl /* pFkts */
};

IFX_ll_fkt ifx_flow_fkt_ptr_tbl [] =
{
   (IFX_ll_fkt) IFX_NULL, /* 0x00 */
   (IFX_ll_fkt) IFX_FLOW_RegisterSet, /* 0x01 */
   (IFX_ll_fkt) IFX_FLOW_RegisterGet, /* 0x02 */
   (IFX_ll_fkt) IFX_FLOW_IrqMaskGet, /* 0x03 */
   (IFX_ll_fkt) IFX_FLOW_IrqMaskSet, /* 0x04 */
   (IFX_ll_fkt) IFX_FLOW_IrqGet, /* 0x05 */
   (IFX_ll_fkt) IFX_FLOW_IrqStatusClear, /* 0x06 */
   (IFX_ll_fkt) IFX_FLOW_PceRuleWrite, /* 0x07 */
   (IFX_ll_fkt) IFX_FLOW_PceRuleRead, /* 0x08 */
   (IFX_ll_fkt) IFX_FLOW_PceRuleDelete, /* 0x09 */
   (IFX_ll_fkt) IFX_FLOW_BootGet, /* 0x0A */
   (IFX_ll_fkt) IFX_FLOW_BootSet, /* 0x0B */
   (IFX_ll_fkt) IFX_FLOW_ClockCfgSet, /* 0x0C */
   (IFX_ll_fkt) IFX_FLOW_ClockCfgGet, /* 0x0D */
   (IFX_ll_fkt) IFX_FLOW_LED_Get, /* 0x0E */
   (IFX_ll_fkt) IFX_FLOW_LED_Set, /* 0x0F */
   (IFX_ll_fkt) IFX_FLOW_Reset, /* 0x10 */
   (IFX_ll_fkt) IFX_FLOW_RMON_ExtendClear, /* 0x11 */
   (IFX_ll_fkt) IFX_FLOW_RMON_ExtendGet, /* 0x12 */
   (IFX_ll_fkt) IFX_FLOW_RMON_ExtendSet /* 0x13 */
};

#if 0
IFX_uint32_t ifx_flow_ioctl_tbl [] =
{
   (IFX_uint32_t) 0, /* 0x00 */
   (IFX_uint32_t) IFX_FLOW_REGISTER_SET, /* 0x01 */
   (IFX_uint32_t) IFX_FLOW_REGISTER_GET, /* 0x02 */
   (IFX_uint32_t) IFX_FLOW_IRQ_MASK_GET, /* 0x03 */
   (IFX_uint32_t) IFX_FLOW_IRQ_MASK_SET, /* 0x04 */
   (IFX_uint32_t) IFX_FLOW_IRQ_GET, /* 0x05 */
   (IFX_uint32_t) IFX_FLOW_IRQ_STATUS_CLEAR, /* 0x06 */
   (IFX_uint32_t) IFX_FLOW_PCE_RULE_WRITE, /* 0x07 */
   (IFX_uint32_t) IFX_FLOW_PCE_RULE_READ, /* 0x08 */
   (IFX_uint32_t) IFX_FLOW_PCE_RULE_DELETE, /* 0x09 */
   (IFX_uint32_t) IFX_FLOW_BOOT_GET, /* 0x0A */
   (IFX_uint32_t) IFX_FLOW_BOOT_SET, /* 0x0B */
   (IFX_uint32_t) IFX_FLOW_CLOCK_CFG_SET, /* 0x0C */
   (IFX_uint32_t) IFX_FLOW_CLOCK_CFG_GET, /* 0x0D */
   (IFX_uint32_t) IFX_FLOW_LED_GET, /* 0x0E */
   (IFX_uint32_t) IFX_FLOW_LED_SET, /* 0x0F */
   (IFX_uint32_t) IFX_FLOW_RESET, /* 0x10 */
   (IFX_uint32_t) IFX_FLOW_RMON_EXTEND_CLEAR, /* 0x11 */
   (IFX_uint32_t) IFX_FLOW_RMON_EXTEND_GET, /* 0x12 */
   (IFX_uint32_t) IFX_FLOW_RMON_EXTEND_SET /* 0x13 */
};
#endif

IFX_ETHSW_lowLevelFkts_t ifx_flow_fkt_tbl =
{
   & ifx_ethsw_FLOW_fkt_tbl , /* pNext */
   (IFX_uint16_t) IFX_FLOW_MAGIC , /* nType */
   20 , /* nNumFkts */
//   ifx_flow_ioctl_tbl , /* IOCTL Table */
   ifx_flow_fkt_ptr_tbl /* pFkts */
};