--- zzzz-none-000/linux-2.6.28.10/arch/mips/kernel/traps.c	2009-05-02 18:54:43.000000000 +0000
+++ puma5-6360-529/linux-2.6.28.10/arch/mips/kernel/traps.c	2011-12-06 12:37:23.000000000 +0000
@@ -946,9 +946,12 @@
 	 */
 	if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
 		mips_read_watch_registers();
+ 		local_irq_enable();
 		force_sig(SIGTRAP, current);
-	} else
+	} else {
 		mips_clear_watch_registers();
+ 		local_irq_enable();
+    }
 }
 
 asmlinkage void do_mcheck(struct pt_regs *regs)
@@ -1208,14 +1211,49 @@
 /*
  * NMI exception handler.
  */
+#include <asm/current.h>
+#include <linux/sched.h>
 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
 {
+    struct task_struct *curr;
+    unsigned int status;
+    extern void ar7wdt_hw_trigger(void);
+
+    regs->cp0_epc = read_c0_errorepc();
+
 	bust_spinlocks(1);
-	printk("NMI taken!!!!\n");
+    ar7wdt_hw_trigger();
+	printk("HardwareWatchDog - NMI taken!!!!\n");
+
+    status = read_c0_status();
+    status &= ~(1 << 0);  /* disable all interrupts */
+    status &= ~(1 << 19); /* reset NMI status */
+    status &= ~(1 << 22); /* bootstap bit BEV zurücksetzen */
+    write_c0_status(status);
+
+#if defined(CONFIG_MACH_FUSIV)
+    curr = get_current();
+    if (curr) {
+	    printk("<current pid %d name %s>\n", curr->pid, curr->comm);
+    } else {
+        printk("<no current found>\n");
+    }
+
+    restore_printk();
+
+	show_stacktrace(curr, &regs);
+
+    panic("HardwareWatchDog");
+#endif
+
 	die("NMI", regs);
 }
 
+#if defined(CONFIG_AMAZON_S) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
+#define VECTORSPACING 0x200	/* for EI/VI mode */
+#else /*--- #if defined(CONFIG_AMAZON_S) || defined(CONFIG_AR9) || defined(CONFIG_VR9) ---*/
 #define VECTORSPACING 0x100	/* for EI/VI mode */
+#endif /*--- #else ---*/ /*--- #if defined(CONFIG_AMAZON_S) || defined(CONFIG_AR9) || defined(CONFIG_VR9) ---*/
 
 unsigned long ebase;
 unsigned long exception_handlers[32];
@@ -1496,7 +1534,12 @@
 		write_c0_ebase(ebase);
 		/* Setting vector spacing enables EI/VI mode  */
 		change_c0_intctl(0x3e0, VECTORSPACING);
+#if defined(CONFIG_FUSIV_VX180)
+    } else {
+		write_c0_ebase (ebase);
+#endif /*--- #if defined(CONFIG_FUSIV_VX180) ---*/
 	}
+
 	if (cpu_has_divec) {
 		if (cpu_has_mipsmt) {
 			unsigned int vpflags = dvpe();
@@ -1571,8 +1614,6 @@
 #ifdef CONFIG_64BIT
 	unsigned long uncached_ebase = TO_UNCAC(ebase);
 #endif
-	if (cpu_has_mips_r2)
-		ebase += (read_c0_ebase() & 0x3ffff000);
 
 	if (!addr)
 		panic(panic_null_cerr);
@@ -1604,12 +1645,33 @@
 		return;	/* Already done */
 #endif
 
-	if (cpu_has_veic || cpu_has_vint)
-		ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
-	else {
-		ebase = CAC_BASE;
-		if (cpu_has_mips_r2)
-			ebase += (read_c0_ebase() & 0x3ffff000);
+	if (cpu_has_veic ) printk("[%s] cpu_has_veic \n", __FUNCTION__);
+	if (cpu_has_vint) printk("[%s] cpu_has_vint\n", __FUNCTION__);
+	if (cpu_has_ejtag ) printk("[%s] cpu_has_ejtag \n", __FUNCTION__);
+	if (cpu_has_watch) printk("[%s] cpu_has_watch\n", __FUNCTION__);
+	if (cpu_has_divec) printk("[%s] cpu_has_divec\n", __FUNCTION__);
+	if (cpu_has_vtag_icache ) printk("[%s] cpu_has_vtag_icache \n", __FUNCTION__);
+	if (cpu_has_fpu ) printk("[%s] cpu_has_fpu \n", __FUNCTION__);
+	if (cpu_has_nofpuex) printk("[%s] cpu_has_nofpuex\n", __FUNCTION__);
+	if (cpu_has_mcheck) printk("[%s] cpu_has_mcheck\n", __FUNCTION__);
+	if (cpu_has_mipsmt) printk("[%s] cpu_has_mipsmt\n", __FUNCTION__);
+	if (cpu_has_vce) printk("[%s] cpu_has_vce\n", __FUNCTION__);
+	if (cpu_has_4kex) printk("[%s] cpu_has_4kex\n", __FUNCTION__);
+
+ 	if (cpu_has_veic || cpu_has_vint) {
+ 		unsigned long size = 0x200 + VECTORSPACING*64;
+ 		ebase = (unsigned long)
+ 			__alloc_bootmem(size, 1 << fls(size), 0);
+ 	} else {
+		/*--- ebase = CAC_BASE; ---*/
+ 		unsigned long size = 0x200 + VECTORSPACING;
+ 		ebase = (unsigned long)__alloc_bootmem(size, 1 << 16, 0);
+
+        /*--------------------------------------------------------------------------------------*\
+         * MaPom: was sollte dieser Code ?????????????
+         \*--------------------------------------------------------------------------------------*/
+		/*--- if (cpu_has_mips_r2) ---*/
+			/*--- ebase += (read_c0_ebase() & 0x3ffff000); ---*/
 	}
 
 	per_cpu_trap_init();
@@ -1647,9 +1709,9 @@
 		int nvec = cpu_has_veic ? 64 : 8;
 		for (i = 0; i < nvec; i++)
 			set_vi_handler(i, NULL);
-	}
-	else if (cpu_has_divec)
+	} else if (cpu_has_divec) {
 		set_handler(0x200, &except_vec4, 0x8);
+    }
 
 	/*
 	 * Some CPUs can enable/disable for cache parity detection, but does