--- zzzz-none-000/linux-2.6.28.10/arch/mips/mm/c-r4k.c	2009-05-02 18:54:43.000000000 +0000
+++ puma5-6360-529/linux-2.6.28.10/arch/mips/mm/c-r4k.c	2011-08-31 13:25:00.000000000 +0000
@@ -1049,7 +1049,7 @@
 	unsigned long flags, addr, begin, end, pow2;
 	unsigned int config = read_c0_config();
 	struct cpuinfo_mips *c = &current_cpu_data;
-	int tmp;
+	/*--- int tmp; ---*/
 
 	if (config & CONF_SC)
 		return 0;
@@ -1082,7 +1082,7 @@
 
 	/* Now search for the wrap around point. */
 	pow2 = (128 * 1024);
-	tmp = 0;
+	/*--- tmp = 0; ---*/
 	for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
 		cache_op(Index_Load_Tag_SD, addr);
 		__asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
@@ -1321,7 +1321,25 @@
 
 __setup("coherentio", setcoherentio);
 #endif
-
+/*--- #define DISPLAY_CACHE_ENTRIES ---*/
+#if defined(DISPLAY_CACHE_ENTRIES)
+#define CACHE_DISPLAY(a) printk("%s waysize: %d, sets: %d, ways: %d, linesz: %d, waybit: %d, flags: %d\n", #a, \
+                                                                    current_cpu_data.a.waysize, \
+                                                                    current_cpu_data.a.sets, \
+                                                                    current_cpu_data.a.ways, \
+                                                                    current_cpu_data.a.linesz, \
+                                                                    current_cpu_data.a.waybit, \
+                                                                    current_cpu_data.a.flags \
+                            );
+/*--------------------------------------------------------------------------------*\
+\*--------------------------------------------------------------------------------*/
+static void display_cache_value(void) {
+    CACHE_DISPLAY(scache);
+    CACHE_DISPLAY(icache);
+    CACHE_DISPLAY(dcache);
+    CACHE_DISPLAY(tcache);
+}
+#endif/*--- #if defined(DISPLAY_CACHE_ENTRIES) ---*/
 void __cpuinit r4k_cache_init(void)
 {
 	extern void build_clear_page(void);
@@ -1330,6 +1348,14 @@
 	extern char __weak except_vec2_sb1;
 	struct cpuinfo_mips *c = &current_cpu_data;
 
+    /*--------------------------------------------------------------------------------------*\
+     * ENABLE for write back allocate
+    \*--------------------------------------------------------------------------------------*/
+#ifdef CONFIG_VR9
+	_page_cachable_default = _CACHE_CACHABLE_NONCOHERENT;
+	change_c0_config(CONF_CM_CMASK, _page_cachable_default >> _CACHE_SHIFT);
+#endif /*--- #ifdef CONFIG_VR9 ---*/
+
 	switch (c->cputype) {
 	case CPU_SB1:
 	case CPU_SB1A:
@@ -1400,4 +1426,7 @@
 	local_r4k___flush_cache_all(NULL);
 #endif
 	coherency_setup();
+#if defined(DISPLAY_CACHE_ENTRIES)
+    display_cache_value();
+#endif/*--- #if defined(DISPLAY_CACHE_ENTRIES) ---*/
 }