--- zzzz-none-000/linux-2.6.39.4/arch/x86/include/asm/pci.h	2011-08-03 19:43:28.000000000 +0000
+++ puma6-arm-6490-729/linux-2.6.39.4/arch/x86/include/asm/pci.h	2021-11-10 13:23:10.000000000 +0000
@@ -83,7 +83,7 @@
 
 #ifdef CONFIG_PCI
 extern void early_quirks(void);
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
+static inline void pci_dma_burst_advice(struct pci_dev *pdev __attribute__((unused)),
 					enum pci_dma_burst_strategy *strat,
 					unsigned long *strategy_parameter)
 {
@@ -164,4 +164,71 @@
 }
 #endif
 
+#ifdef CONFIG_ARCH_GEN3
+
+
+#define INTELCE_EMMC_PCI_DEVICE_ID       0x070b
+#define INTELCE_SFLASH_PCI_DEVICE_ID     0x08a0
+#define INTELCE_HWMUTEX_PCI_DEVICE_ID    0x0949
+#define INTELCE_GPIO_PCI_DEVICE_ID       0x2e67
+#define INTELCE_CP_TOP_PCI_DEVICE_ID     0x2e52
+#define INTELCE_DOCSIS_PCI_DEVICE_ID     0x0946
+#define INTELCE_DOCSIS_DMA_PCI_DEVICE_ID     0x0948
+#define INTELCE_L2_SWITCH_PCI_DEVICE_ID      0x0947
+
+
+#define CE3100_SOC_DEVICE_ID 0x2E50
+#define CE4100_SOC_DEVICE_ID 0x0708
+#define CE4200_SOC_DEVICE_ID 0x0709
+#define CE5300_SOC_DEVICE_ID 0x0C40
+#define CE2600_SOC_DEVICE_ID 0x0931
+
+int intelce_get_soc_info(unsigned int *id, unsigned int *rev);
+
+int intelce_set_board_type(unsigned int board_type);
+int intelce_get_board_type(unsigned int *board_type);
+int intelce_set_board_rev(unsigned int board_rev);
+int intelce_get_board_rev(unsigned int *board_rev);
+void intelce_set_flash_layout_table(struct setup_data *sdata);
+int intelce_get_flash_layout_table(unsigned char **table, int *len);
+
+/** This enum defines the board types that can have CE2600 
+ * These values should be exactly same what defined in CEFDK */
+typedef enum ce2600_board_type {
+   HP_BOARD_TYPE = 0,
+   HP_MG_BOARD_TYPE,
+   FM_BOARD_TYPE,
+   CAT_ISLAND_BOARD_TYPE,
+   GS_BOARD_TYPE,
+   CR_BOARD_TYPE,
+   BL_BOARD_TYPE
+}ce2600_board_type_t;
+
+/** This enum defines the intelce board revisions.
+ * These values should be exactly same what defined in CEFDK */
+typedef enum intelce_board_revision {
+   BOARD_REVISION_0_0 = 0,
+   BOARD_REVISION_0_1 = 1,
+   BOARD_REVISION_0_2 = 2,
+   BOARD_REVISION_1_0 = 10,
+   BOARD_REVISION_1_1 = 11,
+   BOARD_REVISION_1_2 = 12,
+   BOARD_REVISION_2_0 = 20,
+   BOARD_REVISION_2_1 = 21,
+   BOARD_REVISION_2_2 = 22,
+   BOARD_REVISION_3_0 = 30,
+   BOARD_REVISION_3_1 = 31,
+   BOARD_REVISION_3_2 = 32,
+   BOARD_REVISION_4_0 = 40,
+   BOARD_REVISION_4_1 = 41,
+   BOARD_REVISION_4_2 = 42,
+   BOARD_REVISION_5_0 = 50,
+   BOARD_REVISION_5_1 = 51,
+   BOARD_REVISION_5_2 = 52,
+
+   BOARD_REVISION_UNKNOWN = 1000
+}intelce_board_revision_t;
+
+#endif
+
 #endif /* _ASM_X86_PCI_H */