/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface * * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or (at * your option) any later version. * * Thanks to the following companies for their support: * * - JMicron (hardware and technical support) */ /****************************************************************** Includes Intel Corporation's changes/modifications dated: 07/2012. Changed/modified portions - Copyright(c) 2011-2012, Intel Corporation. ******************************************************************/ #include #include #include #include #include #include #include #include #include #if defined(CONFIG_ARCH_GEN3) && defined(CONFIG_HW_MUTEXES) #include #if defined(CONFIG_CE_MAILBOX) #include #endif #endif #include "sdhci.h" /* * PCI registers */ #define PCI_SDHCI_IFPIO 0x00 #define PCI_SDHCI_IFDMA 0x01 #define PCI_SDHCI_IFVENDOR 0x02 #define PCI_SLOT_INFO 0x40 /* 8 bits */ #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7) #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07 #define MAX_SLOTS 8 #ifdef CONFIG_ARCH_GEN3 int scan_thread_done = 0; extern int intelce_boot_mode; #endif struct sdhci_pci_chip; struct sdhci_pci_slot; struct sdhci_pci_fixes { unsigned int quirks; int (*probe)(struct sdhci_pci_chip*); int (*probe_slot)(struct sdhci_pci_slot*); void (*remove_slot)(struct sdhci_pci_slot*, int); int (*suspend)(struct sdhci_pci_chip*, pm_message_t); int (*resume)(struct sdhci_pci_chip*); }; struct sdhci_pci_slot { struct sdhci_pci_chip *chip; struct sdhci_host *host; int pci_bar; }; struct sdhci_pci_chip { struct pci_dev *pdev; unsigned int quirks; const struct sdhci_pci_fixes *fixes; int num_slots; /* Slots on controller */ struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */ }; /*****************************************************************************\ * * * Hardware specific quirk handling * * * \*****************************************************************************/ static int ricoh_probe(struct sdhci_pci_chip *chip) { if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; return 0; } static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) { slot->host->caps = ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT) & SDHCI_TIMEOUT_CLK_MASK) | ((0x21 << SDHCI_CLOCK_BASE_SHIFT) & SDHCI_CLOCK_BASE_MASK) | SDHCI_TIMEOUT_CLK_UNIT | SDHCI_CAN_VDD_330 | SDHCI_CAN_DO_SDMA; return 0; } static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) { /* Apply a delay to allow controller to settle */ /* Otherwise it becomes confused if card state changed during suspend */ msleep(500); return 0; } static const struct sdhci_pci_fixes sdhci_ricoh = { .probe = ricoh_probe, .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_FORCE_DMA | SDHCI_QUIRK_CLOCK_BEFORE_RESET, }; static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { .probe_slot = ricoh_mmc_probe_slot, .resume = ricoh_mmc_resume, .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_CLOCK_BEFORE_RESET | SDHCI_QUIRK_NO_CARD_NO_RESET | SDHCI_QUIRK_MISSING_CAPS }; static const struct sdhci_pci_fixes sdhci_ene_712 = { .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_BROKEN_DMA, }; static const struct sdhci_pci_fixes sdhci_ene_714 = { .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | SDHCI_QUIRK_BROKEN_DMA, }; static const struct sdhci_pci_fixes sdhci_cafe = { .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, }; /* * ADMA operation is disabled for Moorestown platform due to * hardware bugs. */ static int mrst_hc_probe(struct sdhci_pci_chip *chip) { /* * slots number is fixed here for MRST as SDIO3/5 are never used and * have hardware bugs. */ chip->num_slots = 1; return 0; } static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, }; static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, .probe = mrst_hc_probe, }; static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, }; static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc_sdio = { .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, }; /* O2Micro extra registers */ #define O2_SD_LOCK_WP 0xD3 #define O2_SD_MULTI_VCC3V 0xEE #define O2_SD_CLKREQ 0xEC #define O2_SD_CAPS 0xE0 #define O2_SD_ADMA1 0xE2 #define O2_SD_ADMA2 0xE7 #define O2_SD_INF_MOD 0xF1 static int o2_probe(struct sdhci_pci_chip *chip) { int ret; u8 scratch; switch (chip->pdev->device) { case PCI_DEVICE_ID_O2_8220: case PCI_DEVICE_ID_O2_8221: case PCI_DEVICE_ID_O2_8320: case PCI_DEVICE_ID_O2_8321: /* This extra setup is required due to broken ADMA. */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch &= 0x7f; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); /* Set Multi 3 to VCC3V# */ pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08); /* Disable CLK_REQ# support after media DET */ ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch); if (ret) return ret; scratch |= 0x20; pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch); /* Choose capabilities, enable SDMA. We have to write 0x01 * to the capabilities register first to unlock it. */ ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch); if (ret) return ret; scratch |= 0x01; pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch); pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73); /* Disable ADMA1/2 */ pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39); pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08); /* Disable the infinite transfer mode */ ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch); if (ret) return ret; scratch |= 0x08; pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch); /* Lock WP */ ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); if (ret) return ret; scratch |= 0x80; pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); } return 0; } static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) { u8 scratch; int ret; ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); if (ret) return ret; /* * Turn PMOS on [bit 0], set over current detection to 2.4 V * [bit 1:2] and enable over current debouncing [bit 6]. */ if (on) scratch |= 0x47; else scratch &= ~0x47; ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); if (ret) return ret; return 0; } static int jmicron_probe(struct sdhci_pci_chip *chip) { int ret; u16 mmcdev = 0; if (chip->pdev->revision == 0) { chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE | SDHCI_QUIRK_RESET_AFTER_REQUEST | SDHCI_QUIRK_BROKEN_SMALL_PIO; } /* * JMicron chips can have two interfaces to the same hardware * in order to work around limitations in Microsoft's driver. * We need to make sure we only bind to one of them. * * This code assumes two things: * * 1. The PCI code adds subfunctions in order. * * 2. The MMC interface has a lower subfunction number * than the SD interface. */ if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; if (mmcdev) { struct pci_dev *sd_dev; sd_dev = NULL; while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, mmcdev, sd_dev)) != NULL) { if ((PCI_SLOT(chip->pdev->devfn) == PCI_SLOT(sd_dev->devfn)) && (chip->pdev->bus == sd_dev->bus)) break; } if (sd_dev) { pci_dev_put(sd_dev); dev_info(&chip->pdev->dev, "Refusing to bind to " "secondary interface.\n"); return -ENODEV; } } /* * JMicron chips need a bit of a nudge to enable the power * output pins. */ ret = jmicron_pmos(chip, 1); if (ret) { dev_err(&chip->pdev->dev, "Failure enabling card power\n"); return ret; } return 0; } static void jmicron_enable_mmc(struct sdhci_host *host, int on) { u8 scratch; scratch = readb(host->ioaddr + 0xC0); if (on) scratch |= 0x01; else scratch &= ~0x01; writeb(scratch, host->ioaddr + 0xC0); } static int jmicron_probe_slot(struct sdhci_pci_slot *slot) { if (slot->chip->pdev->revision == 0) { u16 version; version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); version = (version & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT; /* * Older versions of the chip have lots of nasty glitches * in the ADMA engine. It's best just to avoid it * completely. */ if (version < 0xAC) slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; } /* JM388 MMC doesn't support 1.8V while SD supports it */ if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_165_195; /* allow 1.8V */ slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ } /* * The secondary interface requires a bit set to get the * interrupts. */ if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) jmicron_enable_mmc(slot->host, 1); slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; return 0; } static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) { if (dead) return; if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) jmicron_enable_mmc(slot->host, 0); } static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state) { int i; if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { for (i = 0;i < chip->num_slots;i++) jmicron_enable_mmc(chip->slots[i]->host, 0); } return 0; } static int jmicron_resume(struct sdhci_pci_chip *chip) { int ret, i; if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { for (i = 0;i < chip->num_slots;i++) jmicron_enable_mmc(chip->slots[i]->host, 1); } ret = jmicron_pmos(chip, 1); if (ret) { dev_err(&chip->pdev->dev, "Failure enabling card power\n"); return ret; } return 0; } static const struct sdhci_pci_fixes sdhci_o2 = { .probe = o2_probe, }; static const struct sdhci_pci_fixes sdhci_jmicron = { .probe = jmicron_probe, .probe_slot = jmicron_probe_slot, .remove_slot = jmicron_remove_slot, .suspend = jmicron_suspend, .resume = jmicron_resume, }; /* SysKonnect CardBus2SDIO extra registers */ #define SYSKT_CTRL 0x200 #define SYSKT_RDFIFO_STAT 0x204 #define SYSKT_WRFIFO_STAT 0x208 #define SYSKT_POWER_DATA 0x20c #define SYSKT_POWER_330 0xef #define SYSKT_POWER_300 0xf8 #define SYSKT_POWER_184 0xcc #define SYSKT_POWER_CMD 0x20d #define SYSKT_POWER_START (1 << 7) #define SYSKT_POWER_STATUS 0x20e #define SYSKT_POWER_STATUS_OK (1 << 0) #define SYSKT_BOARD_REV 0x210 #define SYSKT_CHIP_REV 0x211 #define SYSKT_CONF_DATA 0x212 #define SYSKT_CONF_DATA_1V8 (1 << 2) #define SYSKT_CONF_DATA_2V5 (1 << 1) #define SYSKT_CONF_DATA_3V3 (1 << 0) static int syskt_probe(struct sdhci_pci_chip *chip) { if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { chip->pdev->class &= ~0x0000FF; chip->pdev->class |= PCI_SDHCI_IFDMA; } return 0; } static int syskt_probe_slot(struct sdhci_pci_slot *slot) { int tm, ps; u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " "board rev %d.%d, chip rev %d.%d\n", board_rev >> 4, board_rev & 0xf, chip_rev >> 4, chip_rev & 0xf); if (chip_rev >= 0x20) slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); udelay(50); tm = 10; /* Wait max 1 ms */ do { ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); if (ps & SYSKT_POWER_STATUS_OK) break; udelay(100); } while (--tm); if (!tm) { dev_err(&slot->chip->pdev->dev, "power regulator never stabilized"); writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); return -ENODEV; } return 0; } static const struct sdhci_pci_fixes sdhci_syskt = { .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, .probe = syskt_probe, .probe_slot = syskt_probe_slot, }; static int via_probe(struct sdhci_pci_chip *chip) { if (chip->pdev->revision == 0x10) chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; return 0; } static const struct sdhci_pci_fixes sdhci_via = { .probe = via_probe, }; static const struct pci_device_id pci_ids[] __devinitdata = { { .vendor = PCI_VENDOR_ID_RICOH, .device = PCI_DEVICE_ID_RICOH_R5C822, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ricoh, }, { .vendor = PCI_VENDOR_ID_RICOH, .device = 0x843, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, }, { .vendor = PCI_VENDOR_ID_RICOH, .device = 0xe822, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, }, { .vendor = PCI_VENDOR_ID_RICOH, .device = 0xe823, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc, }, { .vendor = PCI_VENDOR_ID_ENE, .device = PCI_DEVICE_ID_ENE_CB712_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ene_712, }, { .vendor = PCI_VENDOR_ID_ENE, .device = PCI_DEVICE_ID_ENE_CB712_SD_2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ene_712, }, { .vendor = PCI_VENDOR_ID_ENE, .device = PCI_DEVICE_ID_ENE_CB714_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ene_714, }, { .vendor = PCI_VENDOR_ID_ENE, .device = PCI_DEVICE_ID_ENE_CB714_SD_2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_ene_714, }, { .vendor = PCI_VENDOR_ID_MARVELL, .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_cafe, }, { .vendor = PCI_VENDOR_ID_JMICRON, .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_jmicron, }, { .vendor = PCI_VENDOR_ID_JMICRON, .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_jmicron, }, { .vendor = PCI_VENDOR_ID_JMICRON, .device = PCI_DEVICE_ID_JMICRON_JMB388_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_jmicron, }, { .vendor = PCI_VENDOR_ID_JMICRON, .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_jmicron, }, { .vendor = PCI_VENDOR_ID_SYSKONNECT, .device = 0x8000, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_syskt, }, { .vendor = PCI_VENDOR_ID_VIA, .device = 0x95d0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_via, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MRST_SD0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MRST_SD1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MRST_SD2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MFD_SD, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio, }, { .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8120, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8220, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8221, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8320, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { .vendor = PCI_VENDOR_ID_O2, .device = PCI_DEVICE_ID_O2_8321, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .driver_data = (kernel_ulong_t)&sdhci_o2, }, { /* Generic SD host controller */ PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00) }, { /* end: all zeroes */ }, }; MODULE_DEVICE_TABLE(pci, pci_ids); /*****************************************************************************\ * * * SDHCI core callbacks * * * \*****************************************************************************/ static int sdhci_pci_enable_dma(struct sdhci_host *host) { struct sdhci_pci_slot *slot; struct pci_dev *pdev; int ret; slot = sdhci_priv(host); pdev = slot->chip->pdev; if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && (host->flags & SDHCI_USE_SDMA)) { dev_warn(&pdev->dev, "Will use DMA mode even though HW " "doesn't fully claim to support it.\n"); } ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); if (ret) return ret; pci_set_master(pdev); return 0; } #ifdef CONFIG_ARCH_GEN3 /* AEP only supports dword read and write */ static inline u8 sdhci_puma6_readb(struct sdhci_host *host, int reg) { int align_reg; u32 align_val; u8 val; /* Align the register to 32 bit boundary */ align_reg = reg & ~0x3; align_val = readl(host->ioaddr + align_reg); val = (align_val >> ((reg % 4) * 8)) & 0xFF; return val; } static inline u16 sdhci_puma6_readw(struct sdhci_host *host, int reg) { int align_reg; u32 align_val; u16 val; /* Align the register to 32 bit boundary */ align_reg = reg & ~0x3; align_val = readl(host->ioaddr + align_reg); val = (align_val >> ((reg % 4) * 8)) & 0xFFFF; return val; } static inline void sdhci_puma6_writeb(struct sdhci_host *host, u8 val, int reg) { int align_reg; u32 align_val; /* Align the register to 32 bit boundary */ align_reg = reg & ~0x3; align_val = readl(host->ioaddr + align_reg); /* Clear wanted byte and set with new value */ align_val = align_val &~ (0xFF << ((reg % 4) * 8)); align_val = align_val | val << ((reg % 4) * 8); writel(align_val, host->ioaddr + align_reg); } static inline void sdhci_puma6_writew(struct sdhci_host *host, u16 val, int reg) { int align_reg; u32 align_val; static u32 shadow_value; static u32 shadow_valid = 0; /* In Puma6, we must write to HC Registers within width of 32 bits (4 bytes alingment) * Solution: Read the 32 bit register, modify the High Word (16 bit), or Low Word, and write back 32 bits * * A special case is wiriting to TRANSFER MODE register. * Writing to TRANSFER MODE Register with Read/modify/write solution (as above), will trigger the * COMMAND Register, to send a message to eMMC card. * Solution: write the value of TRANSFER MODE to 'a shadow' register, and next time the user write * to COMMAND Register, then write the shadow register to TRANSFER MODE register. * * Note: According to spec after each writing to TRANSFER MODE register, and user will also write * to COMMAND Register. */ /* Align the register to 32 bit boundary */ align_reg = reg & ~0x3; /* Save Transfer Mode to a shadow register */ if (unlikely(reg == SDHCI_TRANSFER_MODE)) { shadow_value = val; shadow_valid = 1; return; } /* Restore the Transfer Mode from a shadow register */ if (unlikely((reg == SDHCI_COMMAND) && (shadow_valid == 1))) { align_val = shadow_value; shadow_valid = 0; } else align_val = readl(host->ioaddr + align_reg); /* Clear wanted word and set with new value */ align_val = align_val &~ (0xFFFF << ((reg % 4) * 8)); align_val = align_val | val << ((reg % 4) * 8); writel(align_val, host->ioaddr + align_reg); } #endif static struct sdhci_ops sdhci_pci_ops = { .enable_dma = sdhci_pci_enable_dma, }; /*****************************************************************************\ * * * Suspend/resume * * * \*****************************************************************************/ #ifdef CONFIG_PM static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state) { struct sdhci_pci_chip *chip; struct sdhci_pci_slot *slot; mmc_pm_flag_t slot_pm_flags; mmc_pm_flag_t pm_flags = 0; int i, ret; chip = pci_get_drvdata(pdev); if (!chip) return 0; #ifdef CONFIG_ARCH_GEN3 if (chip->quirks & SDHCI_QUIRK_NO_SUSPEND) return 0; #endif for (i = 0;i < chip->num_slots;i++) { slot = chip->slots[i]; if (!slot) continue; ret = sdhci_suspend_host(slot->host, state); if (ret) { for (i--;i >= 0;i--) sdhci_resume_host(chip->slots[i]->host); return ret; } slot_pm_flags = slot->host->mmc->pm_flags; if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ) sdhci_enable_irq_wakeups(slot->host); pm_flags |= slot_pm_flags; } if (chip->fixes && chip->fixes->suspend) { ret = chip->fixes->suspend(chip, state); if (ret) { for (i = chip->num_slots - 1;i >= 0;i--) sdhci_resume_host(chip->slots[i]->host); return ret; } } pci_save_state(pdev); if (pm_flags & MMC_PM_KEEP_POWER) { if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) { pci_pme_active(pdev, true); pci_enable_wake(pdev, PCI_D3hot, 1); } pci_set_power_state(pdev, PCI_D3hot); } else { pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); pci_disable_device(pdev); pci_set_power_state(pdev, pci_choose_state(pdev, state)); } return 0; } static int sdhci_pci_resume (struct pci_dev *pdev) { struct sdhci_pci_chip *chip; struct sdhci_pci_slot *slot; int i, ret; chip = pci_get_drvdata(pdev); if (!chip) return 0; #ifdef CONFIG_ARCH_GEN3 if (chip->quirks & SDHCI_QUIRK_NO_SUSPEND) return 0; #endif pci_set_power_state(pdev, PCI_D0); pci_restore_state(pdev); ret = pci_enable_device(pdev); if (ret) return ret; if (chip->fixes && chip->fixes->resume) { ret = chip->fixes->resume(chip); if (ret) return ret; } for (i = 0;i < chip->num_slots;i++) { slot = chip->slots[i]; if (!slot) continue; ret = sdhci_resume_host(slot->host); if (ret) return ret; } return 0; } #else /* CONFIG_PM */ #define sdhci_pci_suspend NULL #define sdhci_pci_resume NULL #endif /* CONFIG_PM */ /*****************************************************************************\ * * * Device probing/removal * * * \*****************************************************************************/ extern void sync_printk(void); static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot( struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar) { struct sdhci_pci_slot *slot; struct sdhci_host *host; int ret; #ifdef CONFIG_ARCH_GEN3 int tmp; int id; int aep_region = 0; struct pci_dev *tmp_dev = NULL; struct pci_dev *aep_pdev = NULL; #endif if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); return ERR_PTR(-ENODEV); } if (pci_resource_len(pdev, bar) != 0x100) { dev_err(&pdev->dev, "Invalid iomem size. You may " "experience problems.\n"); } if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); return ERR_PTR(-ENODEV); } if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); return ERR_PTR(-ENODEV); } host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot)); if (IS_ERR(host)) { dev_err(&pdev->dev, "cannot allocate host\n"); return ERR_CAST(host); } slot = sdhci_priv(host); slot->chip = chip; slot->host = host; slot->pci_bar = bar; host->hw_name = "PCI"; host->ops = &sdhci_pci_ops; host->quirks = chip->quirks; host->irq = pdev->irq; #ifdef CONFIG_ARCH_GEN3 /* Should not fail SDHCI probe, even if AEP is not supported */ aep_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0956, NULL); if (!aep_pdev) dev_info(&pdev->dev, "AEP device is not found\n"); else { ret = pci_request_region(aep_pdev, bar, mmc_hostname(host->mmc)); if (ret) dev_info(&pdev->dev, "cannot request AEP region\n"); else { aep_region = 1; host->aep_base = pci_ioremap_bar(aep_pdev, bar); if (!host->aep_base) { dev_info(&pdev->dev, "failed to remap AEP registers\n"); pci_release_region(aep_pdev, bar); aep_region = 0; } else { if (readl(host->aep_base + PV_CONTROL) & PV_CNTL_AEP_EN) host->aep_enabled = true; else host->aep_enabled = false; } } pci_dev_put(aep_pdev); } /* Virtual emmc controller locates at offset 0x1000 of AEP base */ if (host->aep_enabled) { host->ioaddr = host->aep_base + 0x1000; /* AEP only supports DWORD register access */ sdhci_pci_ops.read_b = sdhci_puma6_readb; sdhci_pci_ops.read_w = sdhci_puma6_readw; sdhci_pci_ops.write_b = sdhci_puma6_writeb; sdhci_pci_ops.write_w = sdhci_puma6_writew; } else { #endif ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc)); if (ret) { dev_err(&pdev->dev, "cannot request region\n"); goto free; } host->ioaddr = pci_ioremap_bar(pdev, bar); if (!host->ioaddr) { dev_err(&pdev->dev, "failed to remap registers\n"); ret = -ENOMEM; goto release; } #ifdef CONFIG_ARCH_GEN3 } #endif if (chip->fixes && chip->fixes->probe_slot) { ret = chip->fixes->probe_slot(slot); if (ret) goto unmap; } host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ; #ifdef CONFIG_ARCH_GEN3 intelce_get_soc_info(&id, NULL); if (id != CE2600_SOC_DEVICE_ID) { if(pdev->revision >= 0x2) host->flags |= SDHCI_SUPPORT_DDR; } #endif #if defined(CONFIG_ARCH_GEN3) && defined(CONFIG_HW_MUTEXES) /* If there's HW Mutex controller exist, then we'll need to use HW Mutex to make sure exclusive controller access from different processors */ tmp_dev = pci_get_device(0x8086, HW_MUTEX_DEV_ID,NULL); if (tmp_dev) { host->flags |= SDHCI_SUPPORT_HW_MUTEX; pci_dev_put(tmp_dev); } #if 0 // AVM/TKL: we already synchronized kernel start up on event x_EVENT_KERNEL_STARTED #if defined(CONFIG_CE_MAILBOX) if (sdhci_host_has_HWMTX(host) && (intelce_boot_mode == 0)) { /* Wait till ARM doesn't use eMMC in legacy mode */ printk(KERN_INFO "waiting for eMMC legacy mode exit notification from NPCPU ... ...\n"); for (;;) { tmp = npcpu_appcpu_mbx_receive_event_notification(NPCPU_EVENT_EMMC_INIT_EXIT,NULL); if (tmp) { dev_err(&pdev->dev, "can not receive legacy mode exit notification from NPCPU, retrying ... \n"); } else break; } tmp = npcpu_appcpu_mbx_send_ack(NPCPU_EVENT_EMMC_INIT_EXIT); if (tmp) { dev_err(&pdev->dev, "can not send NPCPU_EVENT_EMMC_INIT_EXIT ACK message to NPCPU \n"); } } #endif /*CONFIG_CE_MAILBOX */ #endif LOCK_EMMC_HW_MUTEX(host->mmc); ret = sdhci_add_host(host); if (intelce_boot_mode == 1) { while (!scan_thread_done) { schedule_timeout(10); } } UNLOCK_EMMC_HW_MUTEX(host->mmc); #if defined(CONFIG_CE_MAILBOX) if (sdhci_host_has_HWMTX(host) && (intelce_boot_mode == 0)) { if (!ret) { for (;;) { printk(KERN_INFO "waiting for eMMC advanced mode exit notification from NPCPU ... ...\n"); tmp = npcpu_appcpu_mbx_receive_event_notification(NPCPU_EVENT_EMMC_ADVANCE_INIT_EXIT,NULL); if (tmp) { dev_err(&pdev->dev, "can not receive advanced mode exit notification from NPCPU, retrying ... \n"); } else break; } sync_printk(); } } #endif /*CONFIG_CE_MAILBOX */ #else ret = sdhci_add_host(host); #endif if (ret) goto remove; return slot; remove: if (chip->fixes && chip->fixes->remove_slot) chip->fixes->remove_slot(slot, 0); unmap: iounmap(host->ioaddr); release: pci_release_region(pdev, bar); free: #ifdef CONFIG_ARCH_GEN3 if (host->aep_base) iounmap(host->aep_base); if (aep_region) pci_release_region(aep_pdev, bar); #endif sdhci_free_host(host); return ERR_PTR(ret); } static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) { int dead; u32 scratch; dead = 0; scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); if (scratch == (u32)-1) dead = 1; sdhci_remove_host(slot->host, dead); if (slot->chip->fixes && slot->chip->fixes->remove_slot) slot->chip->fixes->remove_slot(slot, dead); pci_release_region(slot->chip->pdev, slot->pci_bar); sdhci_free_host(slot->host); } static int __devinit sdhci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { struct sdhci_pci_chip *chip; struct sdhci_pci_slot *slot; u8 slots, first_bar; int ret, i; #ifdef CONFIG_ARCH_GEN3 unsigned int id; intelce_get_soc_info(&id, NULL); #endif BUG_ON(pdev == NULL); BUG_ON(ent == NULL); dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); if (ret) return ret; slots = PCI_SLOT_INFO_SLOTS(slots) + 1; dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); if (slots == 0) return -ENODEV; BUG_ON(slots > MAX_SLOTS); ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); if (ret) return ret; first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; if (first_bar > 5) { dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); return -ENODEV; } ret = pci_enable_device(pdev); if (ret) return ret; chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL); if (!chip) { ret = -ENOMEM; goto err; } chip->pdev = pdev; chip->fixes = (const struct sdhci_pci_fixes*)ent->driver_data; if (chip->fixes) chip->quirks = chip->fixes->quirks; chip->num_slots = slots; #ifdef CONFIG_ARCH_GEN3 if (CE2600_SOC_DEVICE_ID == id) chip->quirks |= SDHCI_QUIRK_NO_SUSPEND; #endif pci_set_drvdata(pdev, chip); if (chip->fixes && chip->fixes->probe) { ret = chip->fixes->probe(chip); if (ret) goto free; } slots = chip->num_slots; /* Quirk may have changed this */ for (i = 0;i < slots;i++) { slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i); if (IS_ERR(slot)) { for (i--;i >= 0;i--) sdhci_pci_remove_slot(chip->slots[i]); ret = PTR_ERR(slot); goto free; } chip->slots[i] = slot; } return 0; free: pci_set_drvdata(pdev, NULL); kfree(chip); err: pci_disable_device(pdev); return ret; } static void __devexit sdhci_pci_remove(struct pci_dev *pdev) { int i; struct sdhci_pci_chip *chip; chip = pci_get_drvdata(pdev); if (chip) { for (i = 0;i < chip->num_slots; i++) sdhci_pci_remove_slot(chip->slots[i]); pci_set_drvdata(pdev, NULL); kfree(chip); } pci_disable_device(pdev); } static struct pci_driver sdhci_driver = { .name = "sdhci-pci", .id_table = pci_ids, .probe = sdhci_pci_probe, .remove = __devexit_p(sdhci_pci_remove), .suspend = sdhci_pci_suspend, .resume = sdhci_pci_resume, }; /*****************************************************************************\ * * * Driver init/exit * * * \*****************************************************************************/ static int __init sdhci_drv_init(void) { return pci_register_driver(&sdhci_driver); } static void __exit sdhci_drv_exit(void) { pci_unregister_driver(&sdhci_driver); } module_init(sdhci_drv_init); module_exit(sdhci_drv_exit); MODULE_AUTHOR("Pierre Ossman "); MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); MODULE_LICENSE("GPL");