--- zzzz-none-000/linux-2.6.39.4/drivers/net/e1000/e1000_hw.c	2011-08-03 19:43:28.000000000 +0000
+++ puma6-atom-6490-729/linux-2.6.39.4/drivers/net/e1000/e1000_hw.c	2021-11-10 13:38:15.000000000 +0000
@@ -25,11 +25,16 @@
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
  */
+/*******************************************************************************
+  Includes Intel Corporation's changes/modifications dated: 01/2013.
+  Changed/modified portions - Copyright(c) 2011 - 2013, Intel Corporation. 
+*******************************************************************************/
 
 /* e1000_hw.c
  * Shared functions for accessing and configuring the MAC
  */
 
+#include <linux/bug.h>
 #include "e1000.h"
 
 static s32 e1000_check_downshift(struct e1000_hw *hw);
@@ -75,9 +80,9 @@
 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
-				  u16 phy_data);
+				  u16 phy_data, int32_t mdio_addr);
 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
-				 u16 *phy_data);
+				 u16 *phy_data, int32_t mdio_addr);
 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
 static void e1000_release_eeprom(struct e1000_hw *hw);
@@ -136,10 +141,26 @@
 		break;
 	case RTL8211B_PHY_ID:
 		hw->phy_type = e1000_phy_8211;
+#ifdef CONFIG_ARCH_GEN3
+		if (hw->phy_revision == RTL8211D_PHY_REV_ID)
+			hw->phy_type = e1000_phy_8211d;
+		else if (hw->phy_revision == RTL8211E_PHY_REV_ID)
+			hw->phy_type = e1000_phy_8211e;
+#endif
 		break;
 	case RTL8201N_PHY_ID:
 		hw->phy_type = e1000_phy_8201;
 		break;
+#ifdef CONFIG_ARCH_GEN3
+	case RTL8201E_PHY_ID:
+		hw->phy_type = e1000_phy_8201e;
+		if (hw->phy_revision == RTL8201FR_PHY_REV_ID)
+			hw->phy_type = e1000_phy_8201fr;
+		break;
+	case LAN8720A_PHY_ID:
+		hw->phy_type = e1000_phy_lan8720a;
+		break;
+#endif
 	default:
 		/* Should never have loaded on this device */
 		hw->phy_type = e1000_phy_undefined;
@@ -166,6 +187,7 @@
 		/* Save off the current value of register 0x2F5B to be restored at
 		 * the end of this routine. */
 		ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
+		WARN_ON(ret_val);
 
 		/* Disabled the PHY transmitter */
 		e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
@@ -398,6 +420,23 @@
 	}
 }
 
+#ifdef CONFIG_ARCH_GEN3
+static DEFINE_SPINLOCK(gbe_cru_lock);
+unsigned long cru_irqlocal;
+
+void gbe_cru_lock_acquire(unsigned long *irqlocal)
+{
+	spin_lock_irqsave(&gbe_cru_lock, *irqlocal);
+}
+EXPORT_SYMBOL(gbe_cru_lock_acquire);
+
+void gbe_cru_lock_release(unsigned long *irqlocal)
+{
+	spin_unlock_irqrestore(&gbe_cru_lock, *irqlocal);
+}
+EXPORT_SYMBOL(gbe_cru_lock_release);
+#endif
+
 /**
  * e1000_reset_hw: reset the hardware completely
  * @hw: Struct containing variables accessed by shared code
@@ -408,7 +447,7 @@
 {
 	u32 ctrl;
 	u32 ctrl_ext;
-	u32 icr;
+	u32 icr __maybe_unused;
 	u32 manc;
 	u32 led_ctrl;
 	s32 ret_val;
@@ -472,7 +511,16 @@
 		/* Reset is performed on a shadow of the control register */
 		ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
 		break;
+#ifdef CONFIG_ARCH_GEN3
 	case e1000_ce4100:
+		/* Reset should synchronize with AVSync register accessed */
+		gbe_cru_lock_acquire(&cru_irqlocal);
+		ndelay(1000);
+		ew32(CTRL, (er32(CTRL) | E1000_CTRL_RST));
+		ndelay(1000);
+		gbe_cru_lock_release(&cru_irqlocal);
+		break;
+#endif
 	default:
 		ew32(CTRL, (ctrl | E1000_CTRL_RST));
 		break;
@@ -988,6 +1036,9 @@
 {
 	s32 ret_val;
 	u32 ctrl_aux;
+#ifdef CONFIG_ARCH_GEN3
+	u16 phy_data;
+#endif
 
 	switch (hw->phy_type) {
 	case e1000_phy_8211:
@@ -996,7 +1047,34 @@
 			e_dbg("e1000_copper_link_rtl_setup failed!\n");
 			return ret_val;
 		}
+#ifdef CONFIG_ARCH_GEN3		
+		switch (hw->phy_mode) {
+			case FAKE_PHY_INTERNAL:
+				ctrl_aux = er32(CTL_AUX);
+				ctrl_aux |= 0x2;
+				ew32(CTL_AUX, ctrl_aux);
+				break;
+			case FAKE_PHY_EXTERNAL:
+				/* e1000_write_phy_reg_ex(hw, 0x1, 0xC003);
+				   e1000_write_phy_reg_ex(hw, 0x0, 0x96A1); // the external switch is configured in CEFDK
+				*/
+				break;
+			case REAL_PHY:
+			default:
+				break;
+		}
+#endif		
 		break;
+#ifdef CONFIG_ARCH_GEN3
+	case e1000_phy_8211d:
+	case e1000_phy_8211e:
+		ret_val = e1000_copper_link_rtl_setup(hw);
+		if(ret_val){
+			printk(" e1000_copper_link_rtl_setup failed!\n");
+			return ret_val;
+		}
+		break;		
+#endif		
 	case e1000_phy_8201:
 		/* Set RMII mode */
 		ctrl_aux = er32(CTL_AUX);
@@ -1016,7 +1094,87 @@
 			e_dbg("e1000_copper_link_rtl_setup failed!\n");
 			return ret_val;
 		}
+		/* RMII mode setting in 8201N PHY chip */
+		ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+		if (ret_val)
+			return ret_val;
+
+		phy_data |= 0x01;
+		ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+		if (ret_val){
+			printk(" 8201N RMII mode setup failed!\n");
+		}
+		break;
+#ifdef CONFIG_ARCH_GEN3
+	case e1000_phy_8201e:
+		/* Set RMII mode */
+		ctrl_aux = er32(CTL_AUX);
+		ctrl_aux |= E1000_CTL_AUX_RMII;
+		ew32(CTL_AUX, ctrl_aux);
+		E1000_WRITE_FLUSH();
+		/* Disable the J/K bits requried for recieve */
+		ctrl_aux = er32(CTL_AUX);
+		ctrl_aux |= 0x4;
+		ctrl_aux &= ~0x2;
+		ew32(CTL_AUX, ctrl_aux);
+		E1000_WRITE_FLUSH();
+		ret_val = e1000_copper_link_rtl_setup(hw);
+		if(ret_val){
+			printk(" e1000_copper_link_rtl_setup failed!\n");
+			return ret_val;
+		}
+		/* RMII mode setting in 8201E PHY chip */
+		ret_val = e1000_read_phy_reg(hw, PHY_TEST_REG, &phy_data);
+		if (ret_val)
+		return ret_val;
+
+		phy_data |= RMII_MODE_SET;
+		ret_val = e1000_write_phy_reg(hw, PHY_TEST_REG, phy_data);
+		if (ret_val){
+			printk(" 8201E RMII mode setup failed!\n");
+			return ret_val;
+		}
+		break;
+#endif
+#ifdef CONFIG_ARCH_GEN3
+	case e1000_phy_8201fr:
+		/* Set RMII mode */
+		ctrl_aux = er32(CTL_AUX);
+		ctrl_aux |= E1000_CTL_AUX_RMII;
+		ew32(CTL_AUX, ctrl_aux);
+		E1000_WRITE_FLUSH();
+		/* enable the J/K bits requried for recieve */
+		ctrl_aux = er32(CTL_AUX);
+		ctrl_aux &= ~0x4;
+		ctrl_aux &= ~0x2;
+		ew32(CTL_AUX, ctrl_aux);
+		E1000_WRITE_FLUSH();
+		ret_val = e1000_copper_link_rtl_setup(hw);
+		if(ret_val){
+			printk(" e1000_copper_link_rtl_setup failed!\n");
+			return ret_val;
+		}
+		break;
+	case e1000_phy_lan8720a:
+		/* Set RMII mode */
+		ctrl_aux = er32(CTL_AUX);
+		ctrl_aux |= E1000_CTL_AUX_RMII;
+		ew32(CTL_AUX, ctrl_aux);
+		E1000_WRITE_FLUSH();
+		/* enable RX/TX the J/K bits requried for recieve */
+		ctrl_aux = er32(CTL_AUX);
+		ctrl_aux |= 0x8;
+		ctrl_aux &= ~0x4;
+		ctrl_aux &= ~0x2;
+		ew32(CTL_AUX, ctrl_aux);
+		E1000_WRITE_FLUSH();
+		ret_val = e1000_copper_link_rtl_setup(hw);
+		if(ret_val){
+			printk(" e1000_copper_link_rtl_setup failed!\n");
+			return ret_val;
+		}
 		break;
+#endif
 	default:
 		e_dbg("Error Resetting the PHY\n");
 		return E1000_ERR_PHY_TYPE;
@@ -1361,7 +1519,12 @@
 		hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 
 	/* IFE/RTL8201N PHY only supports 10/100 */
+#ifdef CONFIG_ARCH_GEN3	
+	if ((hw->phy_type == e1000_phy_8201) || (hw->phy_type == e1000_phy_8201e) || \
+		(hw->phy_type == e1000_phy_8201fr) || (hw->phy_type == e1000_phy_lan8720a)) 
+#else
 	if (hw->phy_type == e1000_phy_8201)
+#endif		
 		hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
 
 	e_dbg("Reconfiguring auto-neg advertisement params\n");
@@ -1509,6 +1672,9 @@
 		if (ret_val)
 			return ret_val;
 
+#ifdef CONFIG_ARCH_GEN3
+		hw->cegbe_is_link_up = ((phy_data & MII_SR_LINK_STATUS) != 0);
+#endif
 		if (phy_data & MII_SR_LINK_STATUS) {
 			/* Config the MAC and PHY after link is up */
 			ret_val = e1000_copper_link_postconfig(hw);
@@ -1545,11 +1711,22 @@
 		return ret_val;
 
 	/* Read the MII 1000Base-T Control Register (Address 9). */
+#ifdef CONFIG_ARCH_GEN3
+	if ((hw->phy_type == e1000_phy_8201) || (hw->phy_type == e1000_phy_8201e) || \
+		(hw->phy_type == e1000_phy_8201fr) || (hw->phy_type == e1000_phy_lan8720a)) {
+		mii_1000t_ctrl_reg = 0;
+	} else {
+		ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
+		if (ret_val)
+			return ret_val;
+	}
+#else
 	ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
 	if (ret_val)
 		return ret_val;
 	else if (hw->phy_type == e1000_phy_8201)
 		mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
+#endif
 
 	/* Need to parse both autoneg_advertised and fc and set up
 	 * the appropriate PHY registers.  First we will parse for
@@ -1662,7 +1839,12 @@
 
 	e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
 
+#ifdef CONFIG_ARCH_GEN3
+	if ((hw->phy_type == e1000_phy_8201) || (hw->phy_type == e1000_phy_8201e)|| \
+		(hw->phy_type == e1000_phy_8201fr) || (hw->phy_type == e1000_phy_lan8720a)) {
+#else
 	if (hw->phy_type == e1000_phy_8201) {
+#endif
 		mii_1000t_ctrl_reg = 0;
 	} else {
 		ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
@@ -1978,6 +2160,24 @@
 
 		e1000_config_collision_dist(hw);
 		break;
+#ifdef CONFIG_ARCH_GEN3
+	case e1000_phy_8201e:
+	case e1000_phy_8201fr:
+	case e1000_phy_lan8720a:
+			   ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+			   if (ret_val)
+				   return ret_val;
+			   if (phy_data & RTL_PHY_CTRL_FD)
+				   ctrl |= E1000_CTRL_FD;
+			   else
+				   ctrl &= ~E1000_CTRL_FD;
+			   if (phy_data & RTL_PHY_CTRL_SPD_100)
+				   ctrl |= E1000_CTRL_SPD_100;
+			   else
+				   ctrl |= E1000_CTRL_SPD_10;
+			   e1000_config_collision_dist(hw);
+			   break;
+#endif
 	default:
 		/* Set up duplex in the Device Control and Transmit Control
 		 * registers depending on negotiated values.
@@ -2414,8 +2614,8 @@
  */
 s32 e1000_check_for_link(struct e1000_hw *hw)
 {
-	u32 rxcw = 0;
-	u32 ctrl;
+	u32 rxcw __always_unused = 0;
+	u32 ctrl __always_unused;
 	u32 status;
 	u32 rctl;
 	u32 icr;
@@ -2440,6 +2640,7 @@
 			signal =
 			    (hw->mac_type >
 			     e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
+			e_dbg("%s: signal: %u\n", __func__, signal);
 			if (status & E1000_STATUS_LU)
 				hw->get_link_status = false;
 		}
@@ -2464,6 +2665,10 @@
 		if (ret_val)
 			return ret_val;
 
+#ifdef CONFIG_ARCH_GEN3		
+		hw->cegbe_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0;
+#endif
+
 		if (phy_data & MII_SR_LINK_STATUS) {
 			hw->get_link_status = false;
 			/* Check if there was DownShift, must be checked immediately after
@@ -2817,6 +3022,79 @@
 	return data;
 }
 
+#if defined(CONFIG_AVM_CPMAC)
+DEFINE_SPINLOCK(mdio_lock);
+
+int e1000_avmnet_mdio_read(struct avmnet_master_dev *master, uint32_t addr, uint32_t reg, uint16_t *data)
+{
+	struct e1000_hw *hw = (struct e1000_hw *) master->priv;
+	int result;
+
+	result = e1000_read_phy_reg_ex(hw, reg, data, addr);
+
+	return result;
+}
+
+int e1000_avmnet_mdio_write(struct avmnet_master_dev *master, uint32_t addr, uint32_t reg, uint16_t data)
+{
+	struct e1000_hw *hw = (struct e1000_hw *) master->priv;
+	int result;
+
+	result = e1000_write_phy_reg_ex(hw, reg, data, addr);
+
+	return result;
+}
+#endif
+
+#ifdef CONFIG_ARCH_GEN3
+static s32 e1000_read_phy_reg_fake(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
+{
+
+	switch (reg_addr) {
+	case 0x00:
+		*phy_data = 0x3100;
+		break;
+	case 0x01:
+		*phy_data = 0x796d;
+		break;
+	case 0x02:
+		*phy_data = 0x001C;
+		break;
+	case 0x03:
+		*phy_data = 0xC912;
+		break;
+	case 0x04:
+		*phy_data = 0x05E1;
+		break;
+	case 0x05:
+		*phy_data = 0x01E0;
+		break;
+	case 0x06:
+		*phy_data = 0x0004;
+		break;
+	case 0x07:
+		*phy_data = 0x2001;
+		break;
+	case 0x09:
+		*phy_data = 0x0300;
+		break;
+	case 0x0A:
+		*phy_data = 0x3C00;
+		break;
+	case 0x0F:
+		*phy_data = 0x3000;
+		break;
+	case 0x11:
+		*phy_data = 0xAC00;
+		break;
+	default:
+		*phy_data = 0x0000;
+		break;
+	}
+
+	return E1000_SUCCESS;
+}
+#endif
 
 /**
  * e1000_read_phy_reg - read a phy register
@@ -2832,34 +3110,52 @@
 
 	e_dbg("e1000_read_phy_reg");
 
+#ifdef CONFIG_ARCH_GEN3
+	if(hw->phy_mode != REAL_PHY)
+		return e1000_read_phy_reg_fake(hw, reg_addr, phy_data);
+#endif
+
 	if ((hw->phy_type == e1000_phy_igp) &&
 	    (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+	    /* AVM/TKL: added mdio_addr parameter */
 		ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
-						 (u16) reg_addr);
+						 (u16) reg_addr, -1);
 		if (ret_val)
 			return ret_val;
 	}
 
+	/* AVM/TKL: added mdio_addr parameter */
 	ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
-					phy_data);
+					phy_data, -1);
 
 	return ret_val;
 }
 
+/* AVM/TKL: added mdio_addr parameter, changed error returns to goto err_out */
 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
-				 u16 *phy_data)
+				 u16 *phy_data, int32_t mdio_addr)
 {
 	u32 i;
 	u32 mdic = 0;
-	const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
+	u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
+	unsigned long flags;
+	s32 result;
 
 	e_dbg("e1000_read_phy_reg_ex");
 
+	if(mdio_addr >= 0){
+		phy_addr = mdio_addr;
+	}
+
 	if (reg_addr > MAX_PHY_REG_ADDRESS) {
 		e_dbg("PHY Address %d is out of range\n", reg_addr);
 		return -E1000_ERR_PARAM;
 	}
 
+#if defined(CONFIG_AVM_CPMAC)
+	spin_lock_irqsave(&mdio_lock, flags);
+#endif
+
 	if (hw->mac_type > e1000_82543) {
 		/* Set up Op-code, Phy Address, and register address in the MDI
 		 * Control register.  The MAC will take care of interfacing with the
@@ -2885,13 +3181,15 @@
 
 			if (mdic & INTEL_CE_GBE_MDIC_GO) {
 				e_dbg("MDI Read did not complete\n");
-				return -E1000_ERR_PHY;
+				result = -E1000_ERR_PHY;
+				goto err_out;
 			}
 
 			mdic = readl(E1000_MDIO_STS);
 			if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
 				e_dbg("MDI Read Error\n");
-				return -E1000_ERR_PHY;
+				result = -E1000_ERR_PHY;
+				goto err_out;
 			}
 			*phy_data = (u16) mdic;
 		} else {
@@ -2912,11 +3210,13 @@
 			}
 			if (!(mdic & E1000_MDIC_READY)) {
 				e_dbg("MDI Read did not complete\n");
-				return -E1000_ERR_PHY;
+				result = -E1000_ERR_PHY;
+				goto err_out;
 			}
 			if (mdic & E1000_MDIC_ERROR) {
 				e_dbg("MDI Error\n");
-				return -E1000_ERR_PHY;
+				result = -E1000_ERR_PHY;
+				goto err_out;
 			}
 			*phy_data = (u16) mdic;
 		}
@@ -2949,8 +3249,22 @@
 		 */
 		*phy_data = e1000_shift_in_mdi_bits(hw);
 	}
+	result = E1000_SUCCESS;
+
+err_out:
+#if defined(CONFIG_AVM_CPMAC)
+	spin_unlock_irqrestore(&mdio_lock, flags);
+#endif
+
+	return result;
+}
+
+#ifdef CONFIG_ARCH_GEN3
+static s32 e1000_write_phy_reg_fake(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
+{
 	return E1000_SUCCESS;
 }
+#endif
 
 /**
  * e1000_write_phy_reg - write a phy register
@@ -2967,34 +3281,52 @@
 
 	e_dbg("e1000_write_phy_reg");
 
+#ifdef CONFIG_ARCH_GEN3
+	if(hw->phy_mode != REAL_PHY)
+		return e1000_write_phy_reg_fake(hw, reg_addr, phy_data);
+#endif
+
 	if ((hw->phy_type == e1000_phy_igp) &&
-	    (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+		(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+		/* AVM/TKL: added mdio_addr parameter */
 		ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
-						 (u16) reg_addr);
+							(u16) reg_addr, -1);
 		if (ret_val)
 			return ret_val;
 	}
 
+	/* AVM/TKL: added mdio_addr parameter */
 	ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
-					 phy_data);
+					 phy_data, -1);
 
 	return ret_val;
 }
 
+/* AVM/TKL: added mdio_addr parameter, changed error returns to goto err_out */
 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
-				  u16 phy_data)
+				  u16 phy_data, int32_t mdio_addr)
 {
 	u32 i;
 	u32 mdic = 0;
-	const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
+	u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
+	s32 result;
+	unsigned long flags;
 
 	e_dbg("e1000_write_phy_reg_ex");
 
+	if(mdio_addr >= 0){
+	    phy_addr = mdio_addr;
+	}
+
 	if (reg_addr > MAX_PHY_REG_ADDRESS) {
 		e_dbg("PHY Address %d is out of range\n", reg_addr);
 		return -E1000_ERR_PARAM;
 	}
 
+#if defined(CONFIG_AVM_CPMAC)
+	spin_lock_irqsave(&mdio_lock, flags);
+#endif
+
 	if (hw->mac_type > e1000_82543) {
 		/* Set up Op-code, Phy Address, register address, and data
 		 * intended for the PHY register in the MDI Control register.
@@ -3021,7 +3353,8 @@
 			}
 			if (mdic & INTEL_CE_GBE_MDIC_GO) {
 				e_dbg("MDI Write did not complete\n");
-				return -E1000_ERR_PHY;
+				result = -E1000_ERR_PHY;
+				goto err_out;
 			}
 		} else {
 			mdic = (((u32) phy_data) |
@@ -3042,7 +3375,8 @@
 			}
 			if (!(mdic & E1000_MDIC_READY)) {
 				e_dbg("MDI Write did not complete\n");
-				return -E1000_ERR_PHY;
+				result = -E1000_ERR_PHY;
+				goto err_out;
 			}
 		}
 	} else {
@@ -3067,7 +3401,14 @@
 		e1000_shift_out_mdi_bits(hw, mdic, 32);
 	}
 
-	return E1000_SUCCESS;
+	result = E1000_SUCCESS;
+
+err_out:
+#if defined(CONFIG_AVM_CPMAC)
+	spin_unlock_irqrestore(&mdio_lock, flags);
+#endif
+
+	return result;
 }
 
 /**
@@ -3222,9 +3563,18 @@
 			match = true;
 		break;
 	case e1000_ce4100:
+#ifdef CONFIG_ARCH_GEN3
+		if ((hw->phy_id == RTL8211B_PHY_ID) ||
+		    (hw->phy_id == RTL8201N_PHY_ID) ||
+		    (hw->phy_id == RTL8201E_PHY_ID) ||
+		    (hw->phy_id == LAN8720A_PHY_ID) ||
+		    (hw->phy_id == RTL8201FR_PHY_ID) ||
+		    (hw->phy_id == M88E1118_E_PHY_ID))
+#else
 		if ((hw->phy_id == RTL8211B_PHY_ID) ||
 		    (hw->phy_id == RTL8201N_PHY_ID) ||
 		    (hw->phy_id == M88E1118_E_PHY_ID))
+#endif
 			match = true;
 		break;
 	case e1000_82541:
@@ -3470,8 +3820,18 @@
 
 	if (hw->phy_type == e1000_phy_igp)
 		return e1000_phy_igp_get_info(hw, phy_info);
+#ifdef CONFIG_ARCH_GEN3
+	else if ((hw->phy_type == e1000_phy_8211) ||
+			(hw->phy_type == e1000_phy_8201e) ||
+			(hw->phy_type == e1000_phy_lan8720a) ||
+			(hw->phy_type == e1000_phy_8201fr) ||
+			(hw->phy_type == e1000_phy_8211d) ||
+			(hw->phy_type == e1000_phy_8211e) ||
+			(hw->phy_type == e1000_phy_8201))
+#else
 	else if ((hw->phy_type == e1000_phy_8211) ||
 	         (hw->phy_type == e1000_phy_8201))
+#endif
 		return E1000_SUCCESS;
 	else
 		return e1000_phy_m88_get_info(hw, phy_info);
@@ -3920,11 +4280,15 @@
 				u16 *data)
 {
 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
-	u32 i = 0;
+	u32 i = 0, socid = 0;
 
 	e_dbg("e1000_read_eeprom");
 
-	if (hw->mac_type == e1000_ce4100) {
+#if defined(CONFIG_ARCH_GEN3)
+		intelce_get_soc_info(&socid, NULL);
+#endif
+
+	if (hw->mac_type == e1000_ce4100 || socid == CE2600_SOC_DEVICE_ID) {
 		GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
 		                      data);
 		return E1000_SUCCESS;
@@ -4088,11 +4452,15 @@
 				 u16 *data)
 {
 	struct e1000_eeprom_info *eeprom = &hw->eeprom;
-	s32 status = 0;
+	s32 status = 0, socid = 0;
 
 	e_dbg("e1000_write_eeprom");
 
-	if (hw->mac_type == e1000_ce4100) {
+#if defined(CONFIG_ARCH_GEN3)
+	intelce_get_soc_info(&socid, NULL);
+#endif
+
+	if (hw->mac_type == e1000_ce4100 || socid == CE2600_SOC_DEVICE_ID) {
 		GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
 		                       data);
 		return E1000_SUCCESS;
@@ -4733,7 +5101,7 @@
  */
 static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
 {
-	volatile u32 temp;
+	volatile u32 temp __maybe_unused;
 
 	temp = er32(CRCERRS);
 	temp = er32(SYMERRS);