--- zzzz-none-000/linux-2.6.39.4/drivers/net/e1000/e1000_hw.h	2011-08-03 19:43:28.000000000 +0000
+++ puma6-atom-6490-729/linux-2.6.39.4/drivers/net/e1000/e1000_hw.h	2021-11-10 13:38:15.000000000 +0000
@@ -25,6 +25,10 @@
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
 *******************************************************************************/
+/*******************************************************************************
+  Includes Intel Corporation's changes/modifications dated: 05/2012.
+  Changed/modified portions - Copyright(c) 2011 - 2012, Intel Corporation.
+*******************************************************************************/
 
 /* e1000_hw.h
  * Structures, enums, and macros for the MAC
@@ -35,6 +39,9 @@
 
 #include "e1000_osdep.h"
 
+#if defined(CONFIG_AVM_CPMAC)
+#include <avm/net/net.h>
+#endif
 
 /* Forward declarations of structures used by the shared code */
 struct e1000_hw;
@@ -214,6 +221,13 @@
 	e1000_phy_igp,
 	e1000_phy_8211,
 	e1000_phy_8201,
+#ifdef CONFIG_ARCH_GEN3
+	e1000_phy_8201e,
+	e1000_phy_8211d,
+	e1000_phy_8211e,
+    e1000_phy_8201fr,
+	e1000_phy_lan8720a,
+#endif
 	e1000_phy_undefined = 0xFF
 } e1000_phy_type;
 
@@ -403,6 +417,12 @@
 /* Port I/O is only supported on 82544 and newer */
 void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
 
+#if defined(CONFIG_AVM_CPMAC)
+/* MDIO functions for avmnet */
+int e1000_avmnet_mdio_read(struct avmnet_master_dev *master, uint32_t addr, uint32_t reg, uint16_t *data);
+int e1000_avmnet_mdio_write(struct avmnet_master_dev *master, uint32_t addr, uint32_t reg, uint16_t data);
+#endif
+
 #define E1000_READ_REG_IO(a, reg) \
     e1000_read_reg_io((a), E1000_##reg)
 #define E1000_WRITE_REG_IO(a, reg, val) \
@@ -813,7 +833,7 @@
 #define E1000_FLA      0x0001C	/* Flash Access - RW */
 #define E1000_MDIC     0x00020	/* MDI Control - RW */
 
-extern void __iomem *ce4100_gbe_mdio_base_virt;
+extern volatile void __iomem *ce4100_gbe_mdio_base_virt;
 #define INTEL_CE_GBE_MDIO_RCOMP_BASE    (ce4100_gbe_mdio_base_virt)
 #define E1000_MDIO_STS  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0)
 #define E1000_MDIO_CMD  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 4)
@@ -1339,7 +1359,15 @@
 	u64 icrxdmtc;
 	u64 icrxoc;
 };
-
+#ifdef CONFIG_ARCH_GEN3
+enum phy_mode {
+	REAL_PHY = 0,
+	FAKE_PHY_INTERNAL,
+	FAKE_PHY_EXTERNAL,
+	INVALID_PHY,
+};
+#define MARVAL_PHY_ADDRESS 0x4
+#endif
 /* Structure containing variables used by the shared code (e1000_hw.c) */
 struct e1000_hw {
 	u8 __iomem *hw_addr;
@@ -1366,6 +1394,9 @@
 	u32 phy_id;
 	u32 phy_revision;
 	u32 phy_addr;
+#ifdef CONFIG_ARCH_GEN3
+	enum phy_mode phy_mode;
+#endif
 	u32 original_fc;
 	u32 txcw;
 	u32 autoneg_failed;
@@ -1424,6 +1455,9 @@
 	bool leave_av_bit_off;
 	bool bad_tx_carr_stats_fd;
 	bool has_smbus;
+#ifdef CONFIG_ARCH_GEN3
+	bool cegbe_is_link_up;
+#endif
 };
 
 #define E1000_EEPROM_SWDPIN0   0x0001	/* SWDPIN 0 EEPROM Value */
@@ -2243,6 +2277,10 @@
 #define EEPROM_FLASH_VERSION          0x0032
 #define EEPROM_CHECKSUM_REG           0x003F
 
+#ifdef CONFIG_ARCH_GEN3
+#define EEPROM_CE4100_FAKE_LENGTH     0x80
+#endif
+
 #define E1000_EEPROM_CFG_DONE         0x00040000	/* MNG config cycle done */
 #define E1000_EEPROM_CFG_DONE_PORT_1  0x00080000	/* ...for second port */
 
@@ -2508,6 +2546,9 @@
 #define PHY_1000T_CTRL   0x09	/* 1000Base-T Control Reg */
 #define PHY_1000T_STATUS 0x0A	/* 1000Base-T Status Reg */
 #define PHY_EXT_STATUS   0x0F	/* Extended Status Reg */
+#ifdef CONFIG_ARCH_GEN3
+#define PHY_TEST_REG     0x19 /* Test Register */
+#endif
 
 #define MAX_PHY_REG_ADDRESS        0x1F	/* 5 bit address bus (0-0x1F) */
 #define MAX_PHY_MULTI_PAGE_REG     0xF	/* Registers equal on all pages */
@@ -2592,6 +2633,9 @@
 #define MII_CR_SPEED_SELECT_LSB 0x2000	/* bits 6,13: 10=1000, 01=100, 00=10 */
 #define MII_CR_LOOPBACK         0x4000	/* 0 = normal, 1 = loopback */
 #define MII_CR_RESET            0x8000	/* 0 = normal, 1 = PHY reset */
+#ifdef CONFIG_ARCH_GEN3
+#define RMII_MODE_SET           0x0200  /* 0 = MII Mode, 1 = RMII Mode */
+#endif
 
 /* PHY Status Register */
 #define MII_SR_EXTENDED_CAPS     0x0001	/* Extended register capabilities */
@@ -2921,9 +2965,32 @@
 #define L1LXT971A_PHY_ID   0x001378E0
 
 #define RTL8211B_PHY_ID    0x001CC910
+
+#ifdef CONFIG_ARCH_GEN3
+#define RTL8211B_PHY_REV_ID     0b0010//
+#endif
+
 #define RTL8201N_PHY_ID    0x8200
 #define RTL_PHY_CTRL_FD    0x0100 /* Full duplex.0=half; 1=full */
+
+#ifdef CONFIG_ARCH_GEN3
+#define RTL_PHY_CTRL_SPD_100    0x2000 /* Force 100Mb */
+#else
 #define RTL_PHY_CTRL_SPD_100    0x200000 /* Force 100Mb */
+#endif
+
+#ifdef CONFIG_ARCH_GEN3
+#define RTL8201E_PHY_ID     0x001CC810
+#define RTL8211D_PHY_ID     0x001CC910//It's the same as RTL8211B
+#define RTL8211D_PHY_REV_ID     0b0100
+#define RTL8211E_PHY_ID     0x001CC910//It's the same as RTL8211B
+#define RTL8211E_PHY_REV_ID     0b0101
+
+#define RTL8201FR_PHY_ID     0x001CC810
+#define RTL8201FR_PHY_REV_ID    0b0110
+
+#define LAN8720A_PHY_ID		 0x0007C0F0
+#endif
 
 /* Bits...
  * 15-5: page