--- zzzz-none-000/linux-2.6.39.4/include/linux/mmc/sdhci.h	2011-08-03 19:43:28.000000000 +0000
+++ puma6-atom-6490-729/linux-2.6.39.4/include/linux/mmc/sdhci.h	2021-11-10 13:38:17.000000000 +0000
@@ -8,6 +8,16 @@
  * the Free Software Foundation; either version 2 of the License, or (at
  * your option) any later version.
  */
+
+
+/******************************************************************
+ 
+ Includes Intel Corporation's changes/modifications dated: 12/2011, 11/2013.
+ Changed/modified portions - Copyright(c) 2011-2013, Intel Corporation. 
+
+******************************************************************/
+
+
 #ifndef __SDHCI_H
 #define __SDHCI_H
 
@@ -17,6 +27,14 @@
 #include <linux/io.h>
 #include <linux/mmc/host.h>
 
+#if defined(CONFIG_ARCH_GEN3) && defined(CONFIG_HW_MUTEXES)
+#include <linux/hw_mutex.h>
+#endif
+
+#if defined(CONFIG_ARCH_GEN3_MMC)
+#include <arch-avalanche/puma6/hw_mutex_ctrl.h>
+#endif
+
 struct sdhci_host {
 	/* Data set by hardware interface driver */
 	const char *hw_name;	/* Hardware bus name */
@@ -85,7 +103,10 @@
 #define SDHCI_QUIRK_NO_HISPD_BIT			(1<<29)
 /* Controller treats ADMA descriptors with length 0000h incorrectly */
 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC		(1<<30)
-
+#if defined(CONFIG_ARCH_GEN3)
+/* SDHCI could not suspend in CE2600 platform */	
+#define SDHCI_QUIRK_NO_SUSPEND                   (1<<31)
+#endif
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
 
@@ -110,6 +131,17 @@
 #define SDHCI_REQ_USE_DMA	(1<<2)	/* Use DMA for this req. */
 #define SDHCI_DEVICE_DEAD	(1<<3)	/* Device unresponsive */
 
+#if defined(CONFIG_ARCH_GEN3) || defined(CONFIG_ARCH_GEN3_MMC)
+#define SDHCI_SUPPORT_DDR	(1<<4)	/* Support DDR */
+#ifdef CONFIG_HW_MUTEXES
+/* Two or more processors access the controller, HW Mutex is necessary to avoid confliction*/
+#define SDHCI_SUPPORT_HW_MUTEX	(1<<5)		
+#define SDHCI_USE_AEP	    (1<<6)	/* Host Driver works in AEP mode*/
+#endif
+	void __iomem *aep_base;	/* AEP mapped address */
+	bool aep_enabled;
+#endif
+
 	unsigned int version;	/* SDHCI spec. version */
 
 	unsigned int max_clk;	/* Max possible freq (MHz) */
@@ -147,4 +179,41 @@
 
 	unsigned long private[0] ____cacheline_aligned;
 };
+
+#if (defined(CONFIG_ARCH_GEN3) || defined(CONFIG_ARCH_GEN3_MMC)) && defined(CONFIG_HW_MUTEXES)
+
+#define EMMC_HW_MUTEX_IS_LOCKED(host) (hw_mutex_is_locked(HW_MUTEX_EMMC))
+
+#ifndef CONFIG_MACH_PUMA6
+#define lock_emmc_access()
+#define unlock_emmc_access()
+#endif
+		
+
+#define LOCK_EMMC_HW_MUTEX(host) do{\
+		if(((struct sdhci_host *)host->private)->flags & SDHCI_SUPPORT_HW_MUTEX)\
+		{\
+				hw_mutex_lock(HW_MUTEX_EMMC);\
+                /* call function to lock swEmmcAccess mutex */\
+                lock_emmc_access();\
+				enable_irq(((struct sdhci_host *)host->private)->irq);\
+		}\
+	} while(0)
+
+
+#define UNLOCK_EMMC_HW_MUTEX(host) do{\
+	if(((struct sdhci_host *)host->private)->flags & SDHCI_SUPPORT_HW_MUTEX)\
+		{\
+			disable_irq(((struct sdhci_host *)host->private)->irq);\
+            /* call function to unlock swEmmcAccess mutex */\
+            unlock_emmc_access();\
+			hw_mutex_unlock(HW_MUTEX_EMMC);\
+		}\
+	} while(0)
+
+#define sdhci_host_has_HWMTX(host) ((host)->flags & SDHCI_SUPPORT_HW_MUTEX)
+
+#endif /* CONFIG_ARCH_GEN3 */
+
+
 #endif /* __SDHCI_H */