/* This file is provided under a dual BSD/GPLv2 license. When using or redistributing this file, you may do so under either license. GPL LICENSE SUMMARY Copyright(c) 2012-2014 Intel Corporation. This program is free software; you can redistribute it and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. The full GNU General Public License is included in this distribution in the file called LICENSE.GPL. Contact Information: Intel Corporation 2200 Mission College Blvd. Santa Clara, CA 97052 BSD LICENSE Copyright(c) 2012-2013 Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifdef __KERNEL__ #include #endif #ifndef PUMA6_CPPI_PRV_H #define PUMA6_CPPI_PRV_H #define PAL_CPPI4x_PRTY_LOW 0 #define PAL_CPPI4x_PRTY_HIGH 1 /********************************************************************************************************************** ####### ## ## ######## ## ## ######## ## ## ### ## ## ### ###### ######## ######## ## ## ## ## ## ## ## ## ### ### ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## #### #### ## ## #### ## ## ## ## ## ## ## ## ## ## ## ###### ## ## ###### ## ### ## ## ## ## ## ## ## ## ## #### ###### ######## ## ## ## ## ## ## ## ## ## ## ## ######### ## #### ######### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ### ## ## ## ## ## ## ## ##### ## ####### ######## ####### ######## ## ## ## ## ## ## ## ## ###### ######## ## ## **********************************************************************************************************************/ #define PAL_CPPI41_NUM_QUEUE_MGR 2 /**< Number of queue managers in CPPI system */ #define PAL_CPPI41_MAX_DESC_REGIONS 16 /**< Maximum descriptor regions per queue manager */ #define PAL_CPPI41_QUEUE_MGR_PARTITION_SR 0 #define PAL_CPPI41_QUEUE_MGR_PARTITION_DOCSIS 1 #define PAL_CPPI41_QUEUE_MGR_PARTITION_DOCSIS_DS_GROUP 0 /* +-+-+ +-+-+-+-+-+ +-+-+-+-+-+-+-+ |S|R| |Q|u|e|u|e| |M|a|n|a|g|e|r| +-+-+ +-+-+-+-+-+ +-+-+-+-+-+-+-+ */ typedef enum PAL_CPPI41_SR_QMGR_QUEUES { /* DS Resequencing Queues */ PAL_CPPI41_SR_DS_RESEQ_Q_BASE, PAL_CPPI41_SR_DS_RESEQ_Q_0 = PAL_CPPI41_SR_DS_RESEQ_Q_BASE, PAL_CPPI41_SR_DS_RESEQ_Q_1, PAL_CPPI41_SR_DS_RESEQ_Q_2, PAL_CPPI41_SR_DS_RESEQ_Q_3, PAL_CPPI41_SR_DS_RESEQ_Q_4, PAL_CPPI41_SR_DS_RESEQ_Q_5, PAL_CPPI41_SR_DS_RESEQ_Q_6, PAL_CPPI41_SR_DS_RESEQ_Q_7, PAL_CPPI41_SR_DS_RESEQ_Q_8, PAL_CPPI41_SR_DS_RESEQ_Q_9, PAL_CPPI41_SR_DS_RESEQ_Q_10, PAL_CPPI41_SR_DS_RESEQ_Q_11, PAL_CPPI41_SR_DS_RESEQ_Q_12, PAL_CPPI41_SR_DS_RESEQ_Q_13, PAL_CPPI41_SR_DS_RESEQ_Q_14, PAL_CPPI41_SR_DS_RESEQ_Q_15, PAL_CPPI41_SR_DS_RESEQ_Q_16, PAL_CPPI41_SR_DS_RESEQ_Q_17, PAL_CPPI41_SR_DS_RESEQ_Q_18, PAL_CPPI41_SR_DS_RESEQ_Q_19, PAL_CPPI41_SR_DS_RESEQ_Q_20, PAL_CPPI41_SR_DS_RESEQ_Q_21, PAL_CPPI41_SR_DS_RESEQ_Q_22, PAL_CPPI41_SR_DS_RESEQ_Q_23, PAL_CPPI41_SR_DS_RESEQ_Q_24, PAL_CPPI41_SR_DS_RESEQ_Q_25, PAL_CPPI41_SR_DS_RESEQ_Q_26, PAL_CPPI41_SR_DS_RESEQ_Q_27, PAL_CPPI41_SR_DS_RESEQ_Q_28, PAL_CPPI41_SR_DS_RESEQ_Q_29, PAL_CPPI41_SR_DS_RESEQ_Q_30, PAL_CPPI41_SR_DS_RESEQ_Q_31, PAL_CPPI41_SR_DS_RESEQ_Q_32, PAL_CPPI41_SR_DS_RESEQ_Q_33, PAL_CPPI41_SR_DS_RESEQ_Q_34, PAL_CPPI41_SR_DS_RESEQ_Q_35, PAL_CPPI41_SR_DS_RESEQ_Q_36, PAL_CPPI41_SR_DS_RESEQ_Q_37, PAL_CPPI41_SR_DS_RESEQ_Q_38, PAL_CPPI41_SR_DS_RESEQ_Q_39, PAL_CPPI41_SR_DS_RESEQ_Q_40, PAL_CPPI41_SR_DS_RESEQ_Q_41, PAL_CPPI41_SR_DS_RESEQ_Q_42, PAL_CPPI41_SR_DS_RESEQ_Q_43, PAL_CPPI41_SR_DS_RESEQ_Q_44, PAL_CPPI41_SR_DS_RESEQ_Q_45, PAL_CPPI41_SR_DS_RESEQ_Q_46, PAL_CPPI41_SR_DS_RESEQ_Q_47, PAL_CPPI41_SR_DS_RESEQ_Q_48, PAL_CPPI41_SR_DS_RESEQ_Q_49, PAL_CPPI41_SR_DS_RESEQ_Q_50, PAL_CPPI41_SR_DS_RESEQ_Q_51, PAL_CPPI41_SR_DS_RESEQ_Q_52, PAL_CPPI41_SR_DS_RESEQ_Q_53, PAL_CPPI41_SR_DS_RESEQ_Q_54, PAL_CPPI41_SR_DS_RESEQ_Q_55, PAL_CPPI41_SR_DS_RESEQ_Q_56, PAL_CPPI41_SR_DS_RESEQ_Q_57, PAL_CPPI41_SR_DS_RESEQ_Q_58, PAL_CPPI41_SR_DS_RESEQ_Q_59, PAL_CPPI41_SR_DS_RESEQ_Q_60, PAL_CPPI41_SR_DS_RESEQ_Q_61, PAL_CPPI41_SR_DS_RESEQ_Q_62, PAL_CPPI41_SR_DS_RESEQ_Q_63, PAL_CPPI41_SR_DS_RESEQ_Q_64, PAL_CPPI41_SR_DS_RESEQ_Q_65, PAL_CPPI41_SR_DS_RESEQ_Q_66, PAL_CPPI41_SR_DS_RESEQ_Q_67, PAL_CPPI41_SR_DS_RESEQ_Q_68, PAL_CPPI41_SR_DS_RESEQ_Q_69, PAL_CPPI41_SR_DS_RESEQ_Q_70, PAL_CPPI41_SR_DS_RESEQ_Q_71, PAL_CPPI41_SR_DS_RESEQ_Q_72, PAL_CPPI41_SR_DS_RESEQ_Q_73, PAL_CPPI41_SR_DS_RESEQ_Q_74, PAL_CPPI41_SR_DS_RESEQ_Q_75, PAL_CPPI41_SR_DS_RESEQ_Q_76, PAL_CPPI41_SR_DS_RESEQ_Q_77, PAL_CPPI41_SR_DS_RESEQ_Q_78, PAL_CPPI41_SR_DS_RESEQ_Q_79, PAL_CPPI41_SR_DS_RESEQ_Q_80, PAL_CPPI41_SR_DS_RESEQ_Q_81, PAL_CPPI41_SR_DS_RESEQ_Q_82, PAL_CPPI41_SR_DS_RESEQ_Q_83, PAL_CPPI41_SR_DS_RESEQ_Q_84, PAL_CPPI41_SR_DS_RESEQ_Q_85, PAL_CPPI41_SR_DS_RESEQ_Q_86, PAL_CPPI41_SR_DS_RESEQ_Q_87, PAL_CPPI41_SR_DS_RESEQ_Q_88, PAL_CPPI41_SR_DS_RESEQ_Q_89, PAL_CPPI41_SR_DS_RESEQ_Q_90, PAL_CPPI41_SR_DS_RESEQ_Q_91, PAL_CPPI41_SR_DS_RESEQ_Q_92, PAL_CPPI41_SR_DS_RESEQ_Q_93, PAL_CPPI41_SR_DS_RESEQ_Q_94, PAL_CPPI41_SR_DS_RESEQ_Q_95, PAL_CPPI41_SR_DS_RESEQ_Q_96, PAL_CPPI41_SR_DS_RESEQ_Q_97, PAL_CPPI41_SR_DS_RESEQ_Q_98, PAL_CPPI41_SR_DS_RESEQ_Q_99, PAL_CPPI41_SR_DS_RESEQ_Q_100, PAL_CPPI41_SR_DS_RESEQ_Q_101, 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PAL_CPPI41_SR_DS_RESEQ_Q_729, PAL_CPPI41_SR_DS_RESEQ_Q_730, PAL_CPPI41_SR_DS_RESEQ_Q_731, PAL_CPPI41_SR_DS_RESEQ_Q_732, PAL_CPPI41_SR_DS_RESEQ_Q_733, PAL_CPPI41_SR_DS_RESEQ_Q_734, PAL_CPPI41_SR_DS_RESEQ_Q_735, PAL_CPPI41_SR_DS_RESEQ_Q_736, PAL_CPPI41_SR_DS_RESEQ_Q_737, PAL_CPPI41_SR_DS_RESEQ_Q_738, PAL_CPPI41_SR_DS_RESEQ_Q_739, PAL_CPPI41_SR_DS_RESEQ_Q_740, PAL_CPPI41_SR_DS_RESEQ_Q_741, PAL_CPPI41_SR_DS_RESEQ_Q_742, PAL_CPPI41_SR_DS_RESEQ_Q_743, PAL_CPPI41_SR_DS_RESEQ_Q_744, PAL_CPPI41_SR_DS_RESEQ_Q_745, PAL_CPPI41_SR_DS_RESEQ_Q_746, PAL_CPPI41_SR_DS_RESEQ_Q_747, PAL_CPPI41_SR_DS_RESEQ_Q_748, PAL_CPPI41_SR_DS_RESEQ_Q_749, PAL_CPPI41_SR_DS_RESEQ_Q_750, PAL_CPPI41_SR_DS_RESEQ_Q_751, PAL_CPPI41_SR_DS_RESEQ_Q_752, PAL_CPPI41_SR_DS_RESEQ_Q_753, PAL_CPPI41_SR_DS_RESEQ_Q_754, PAL_CPPI41_SR_DS_RESEQ_Q_755, PAL_CPPI41_SR_DS_RESEQ_Q_756, PAL_CPPI41_SR_DS_RESEQ_Q_757, PAL_CPPI41_SR_DS_RESEQ_Q_758, PAL_CPPI41_SR_DS_RESEQ_Q_759, PAL_CPPI41_SR_DS_RESEQ_Q_760, PAL_CPPI41_SR_DS_RESEQ_Q_761, PAL_CPPI41_SR_DS_RESEQ_Q_762, PAL_CPPI41_SR_DS_RESEQ_Q_763, PAL_CPPI41_SR_DS_RESEQ_Q_764, PAL_CPPI41_SR_DS_RESEQ_Q_765, PAL_CPPI41_SR_DS_RESEQ_Q_766, PAL_CPPI41_SR_DS_RESEQ_Q_767, PAL_CPPI41_SR_DS_RESEQ_Q_768, PAL_CPPI41_SR_DS_RESEQ_Q_769, PAL_CPPI41_SR_DS_RESEQ_Q_770, PAL_CPPI41_SR_DS_RESEQ_Q_771, PAL_CPPI41_SR_DS_RESEQ_Q_772, PAL_CPPI41_SR_DS_RESEQ_Q_773, PAL_CPPI41_SR_DS_RESEQ_Q_774, PAL_CPPI41_SR_DS_RESEQ_Q_775, PAL_CPPI41_SR_DS_RESEQ_Q_776, PAL_CPPI41_SR_DS_RESEQ_Q_777, PAL_CPPI41_SR_DS_RESEQ_Q_778, PAL_CPPI41_SR_DS_RESEQ_Q_779, PAL_CPPI41_SR_DS_RESEQ_Q_780, PAL_CPPI41_SR_DS_RESEQ_Q_781, PAL_CPPI41_SR_DS_RESEQ_Q_782, PAL_CPPI41_SR_DS_RESEQ_Q_783, PAL_CPPI41_SR_DS_RESEQ_Q_784, PAL_CPPI41_SR_DS_RESEQ_Q_785, PAL_CPPI41_SR_DS_RESEQ_Q_786, PAL_CPPI41_SR_DS_RESEQ_Q_787, PAL_CPPI41_SR_DS_RESEQ_Q_788, PAL_CPPI41_SR_DS_RESEQ_Q_789, PAL_CPPI41_SR_DS_RESEQ_Q_790, PAL_CPPI41_SR_DS_RESEQ_Q_791, PAL_CPPI41_SR_DS_RESEQ_Q_792, PAL_CPPI41_SR_DS_RESEQ_Q_793, PAL_CPPI41_SR_DS_RESEQ_Q_794, PAL_CPPI41_SR_DS_RESEQ_Q_795, PAL_CPPI41_SR_DS_RESEQ_Q_796, PAL_CPPI41_SR_DS_RESEQ_Q_797, PAL_CPPI41_SR_DS_RESEQ_Q_798, PAL_CPPI41_SR_DS_RESEQ_Q_799, PAL_CPPI41_SR_DS_RESEQ_Q_800, PAL_CPPI41_SR_DS_RESEQ_Q_801, PAL_CPPI41_SR_DS_RESEQ_Q_802, PAL_CPPI41_SR_DS_RESEQ_Q_803, PAL_CPPI41_SR_DS_RESEQ_Q_804, PAL_CPPI41_SR_DS_RESEQ_Q_805, PAL_CPPI41_SR_DS_RESEQ_Q_806, PAL_CPPI41_SR_DS_RESEQ_Q_807, PAL_CPPI41_SR_DS_RESEQ_Q_808, PAL_CPPI41_SR_DS_RESEQ_Q_809, PAL_CPPI41_SR_DS_RESEQ_Q_810, PAL_CPPI41_SR_DS_RESEQ_Q_811, PAL_CPPI41_SR_DS_RESEQ_Q_812, PAL_CPPI41_SR_DS_RESEQ_Q_813, PAL_CPPI41_SR_DS_RESEQ_Q_814, PAL_CPPI41_SR_DS_RESEQ_Q_815, PAL_CPPI41_SR_DS_RESEQ_Q_816, PAL_CPPI41_SR_DS_RESEQ_Q_817, PAL_CPPI41_SR_DS_RESEQ_Q_818, PAL_CPPI41_SR_DS_RESEQ_Q_819, PAL_CPPI41_SR_DS_RESEQ_Q_820, PAL_CPPI41_SR_DS_RESEQ_Q_821, PAL_CPPI41_SR_DS_RESEQ_Q_822, PAL_CPPI41_SR_DS_RESEQ_Q_823, PAL_CPPI41_SR_DS_RESEQ_Q_824, PAL_CPPI41_SR_DS_RESEQ_Q_825, PAL_CPPI41_SR_DS_RESEQ_Q_826, PAL_CPPI41_SR_DS_RESEQ_Q_827, PAL_CPPI41_SR_DS_RESEQ_Q_828, PAL_CPPI41_SR_DS_RESEQ_Q_829, PAL_CPPI41_SR_DS_RESEQ_Q_830, PAL_CPPI41_SR_DS_RESEQ_Q_831, PAL_CPPI41_SR_DS_RESEQ_Q_832, PAL_CPPI41_SR_DS_RESEQ_Q_833, PAL_CPPI41_SR_DS_RESEQ_Q_834, PAL_CPPI41_SR_DS_RESEQ_Q_835, PAL_CPPI41_SR_DS_RESEQ_Q_836, PAL_CPPI41_SR_DS_RESEQ_Q_837, PAL_CPPI41_SR_DS_RESEQ_Q_838, PAL_CPPI41_SR_DS_RESEQ_Q_839, PAL_CPPI41_SR_DS_RESEQ_Q_840, PAL_CPPI41_SR_DS_RESEQ_Q_841, PAL_CPPI41_SR_DS_RESEQ_Q_842, PAL_CPPI41_SR_DS_RESEQ_Q_843, PAL_CPPI41_SR_DS_RESEQ_Q_844, PAL_CPPI41_SR_DS_RESEQ_Q_845, PAL_CPPI41_SR_DS_RESEQ_Q_846, PAL_CPPI41_SR_DS_RESEQ_Q_847, PAL_CPPI41_SR_DS_RESEQ_Q_848, PAL_CPPI41_SR_DS_RESEQ_Q_849, PAL_CPPI41_SR_DS_RESEQ_Q_850, PAL_CPPI41_SR_DS_RESEQ_Q_851, PAL_CPPI41_SR_DS_RESEQ_Q_852, PAL_CPPI41_SR_DS_RESEQ_Q_853, PAL_CPPI41_SR_DS_RESEQ_Q_854, PAL_CPPI41_SR_DS_RESEQ_Q_855, PAL_CPPI41_SR_DS_RESEQ_Q_856, PAL_CPPI41_SR_DS_RESEQ_Q_857, PAL_CPPI41_SR_DS_RESEQ_Q_858, PAL_CPPI41_SR_DS_RESEQ_Q_859, PAL_CPPI41_SR_DS_RESEQ_Q_860, PAL_CPPI41_SR_DS_RESEQ_Q_861, PAL_CPPI41_SR_DS_RESEQ_Q_862, PAL_CPPI41_SR_DS_RESEQ_Q_863, PAL_CPPI41_SR_DS_RESEQ_Q_864, PAL_CPPI41_SR_DS_RESEQ_Q_865, PAL_CPPI41_SR_DS_RESEQ_Q_866, PAL_CPPI41_SR_DS_RESEQ_Q_867, PAL_CPPI41_SR_DS_RESEQ_Q_868, PAL_CPPI41_SR_DS_RESEQ_Q_869, PAL_CPPI41_SR_DS_RESEQ_Q_870, PAL_CPPI41_SR_DS_RESEQ_Q_871, PAL_CPPI41_SR_DS_RESEQ_Q_872, PAL_CPPI41_SR_DS_RESEQ_Q_873, PAL_CPPI41_SR_DS_RESEQ_Q_874, PAL_CPPI41_SR_DS_RESEQ_Q_875, PAL_CPPI41_SR_DS_RESEQ_Q_876, PAL_CPPI41_SR_DS_RESEQ_Q_877, PAL_CPPI41_SR_DS_RESEQ_Q_878, PAL_CPPI41_SR_DS_RESEQ_Q_879, PAL_CPPI41_SR_DS_RESEQ_Q_880, PAL_CPPI41_SR_DS_RESEQ_Q_881, PAL_CPPI41_SR_DS_RESEQ_Q_882, PAL_CPPI41_SR_DS_RESEQ_Q_883, PAL_CPPI41_SR_DS_RESEQ_Q_884, PAL_CPPI41_SR_DS_RESEQ_Q_885, PAL_CPPI41_SR_DS_RESEQ_Q_886, PAL_CPPI41_SR_DS_RESEQ_Q_887, PAL_CPPI41_SR_DS_RESEQ_Q_888, PAL_CPPI41_SR_DS_RESEQ_Q_889, PAL_CPPI41_SR_DS_RESEQ_Q_890, PAL_CPPI41_SR_DS_RESEQ_Q_891, PAL_CPPI41_SR_DS_RESEQ_Q_892, PAL_CPPI41_SR_DS_RESEQ_Q_893, PAL_CPPI41_SR_DS_RESEQ_Q_894, PAL_CPPI41_SR_DS_RESEQ_Q_895, PAL_CPPI41_SR_DS_RESEQ_Q_896, PAL_CPPI41_SR_DS_RESEQ_Q_897, PAL_CPPI41_SR_DS_RESEQ_Q_898, PAL_CPPI41_SR_DS_RESEQ_Q_899, PAL_CPPI41_SR_DS_RESEQ_Q_900, PAL_CPPI41_SR_DS_RESEQ_Q_901, PAL_CPPI41_SR_DS_RESEQ_Q_902, PAL_CPPI41_SR_DS_RESEQ_Q_903, PAL_CPPI41_SR_DS_RESEQ_Q_904, PAL_CPPI41_SR_DS_RESEQ_Q_905, PAL_CPPI41_SR_DS_RESEQ_Q_906, PAL_CPPI41_SR_DS_RESEQ_Q_907, PAL_CPPI41_SR_DS_RESEQ_Q_908, PAL_CPPI41_SR_DS_RESEQ_Q_909, PAL_CPPI41_SR_DS_RESEQ_Q_910, PAL_CPPI41_SR_DS_RESEQ_Q_911, PAL_CPPI41_SR_DS_RESEQ_Q_912, PAL_CPPI41_SR_DS_RESEQ_Q_913, PAL_CPPI41_SR_DS_RESEQ_Q_914, PAL_CPPI41_SR_DS_RESEQ_Q_915, PAL_CPPI41_SR_DS_RESEQ_Q_916, PAL_CPPI41_SR_DS_RESEQ_Q_917, PAL_CPPI41_SR_DS_RESEQ_Q_918, PAL_CPPI41_SR_DS_RESEQ_Q_919, PAL_CPPI41_SR_DS_RESEQ_Q_920, PAL_CPPI41_SR_DS_RESEQ_Q_921, PAL_CPPI41_SR_DS_RESEQ_Q_922, PAL_CPPI41_SR_DS_RESEQ_Q_923, PAL_CPPI41_SR_DS_RESEQ_Q_924, PAL_CPPI41_SR_DS_RESEQ_Q_925, PAL_CPPI41_SR_DS_RESEQ_Q_926, PAL_CPPI41_SR_DS_RESEQ_Q_927, PAL_CPPI41_SR_DS_RESEQ_Q_928, PAL_CPPI41_SR_DS_RESEQ_Q_929, PAL_CPPI41_SR_DS_RESEQ_Q_930, PAL_CPPI41_SR_DS_RESEQ_Q_931, PAL_CPPI41_SR_DS_RESEQ_Q_932, PAL_CPPI41_SR_DS_RESEQ_Q_933, PAL_CPPI41_SR_DS_RESEQ_Q_934, PAL_CPPI41_SR_DS_RESEQ_Q_935, PAL_CPPI41_SR_DS_RESEQ_Q_936, PAL_CPPI41_SR_DS_RESEQ_Q_937, PAL_CPPI41_SR_DS_RESEQ_Q_938, PAL_CPPI41_SR_DS_RESEQ_Q_939, PAL_CPPI41_SR_DS_RESEQ_Q_940, PAL_CPPI41_SR_DS_RESEQ_Q_941, PAL_CPPI41_SR_DS_RESEQ_Q_942, PAL_CPPI41_SR_DS_RESEQ_Q_943, PAL_CPPI41_SR_DS_RESEQ_Q_944, PAL_CPPI41_SR_DS_RESEQ_Q_945, PAL_CPPI41_SR_DS_RESEQ_Q_946, PAL_CPPI41_SR_DS_RESEQ_Q_947, PAL_CPPI41_SR_DS_RESEQ_Q_948, PAL_CPPI41_SR_DS_RESEQ_Q_949, PAL_CPPI41_SR_DS_RESEQ_Q_950, PAL_CPPI41_SR_DS_RESEQ_Q_951, PAL_CPPI41_SR_DS_RESEQ_Q_952, PAL_CPPI41_SR_DS_RESEQ_Q_953, PAL_CPPI41_SR_DS_RESEQ_Q_954, PAL_CPPI41_SR_DS_RESEQ_Q_955, PAL_CPPI41_SR_DS_RESEQ_Q_956, PAL_CPPI41_SR_DS_RESEQ_Q_957, PAL_CPPI41_SR_DS_RESEQ_Q_958, PAL_CPPI41_SR_DS_RESEQ_Q_959, PAL_CPPI41_SR_DS_RESEQ_Q_960, PAL_CPPI41_SR_DS_RESEQ_Q_961, PAL_CPPI41_SR_DS_RESEQ_Q_962, PAL_CPPI41_SR_DS_RESEQ_Q_963, PAL_CPPI41_SR_DS_RESEQ_Q_964, PAL_CPPI41_SR_DS_RESEQ_Q_965, PAL_CPPI41_SR_DS_RESEQ_Q_966, PAL_CPPI41_SR_DS_RESEQ_Q_967, PAL_CPPI41_SR_DS_RESEQ_Q_968, PAL_CPPI41_SR_DS_RESEQ_Q_969, PAL_CPPI41_SR_DS_RESEQ_Q_970, PAL_CPPI41_SR_DS_RESEQ_Q_971, PAL_CPPI41_SR_DS_RESEQ_Q_972, PAL_CPPI41_SR_DS_RESEQ_Q_973, PAL_CPPI41_SR_DS_RESEQ_Q_974, PAL_CPPI41_SR_DS_RESEQ_Q_975, PAL_CPPI41_SR_DS_RESEQ_Q_976, PAL_CPPI41_SR_DS_RESEQ_Q_977, PAL_CPPI41_SR_DS_RESEQ_Q_978, PAL_CPPI41_SR_DS_RESEQ_Q_979, PAL_CPPI41_SR_DS_RESEQ_Q_980, PAL_CPPI41_SR_DS_RESEQ_Q_981, PAL_CPPI41_SR_DS_RESEQ_Q_982, PAL_CPPI41_SR_DS_RESEQ_Q_983, PAL_CPPI41_SR_DS_RESEQ_Q_984, PAL_CPPI41_SR_DS_RESEQ_Q_985, PAL_CPPI41_SR_DS_RESEQ_Q_986, PAL_CPPI41_SR_DS_RESEQ_Q_987, PAL_CPPI41_SR_DS_RESEQ_Q_988, PAL_CPPI41_SR_DS_RESEQ_Q_989, PAL_CPPI41_SR_DS_RESEQ_Q_990, PAL_CPPI41_SR_DS_RESEQ_Q_991, PAL_CPPI41_SR_DS_RESEQ_Q_992, PAL_CPPI41_SR_DS_RESEQ_Q_993, PAL_CPPI41_SR_DS_RESEQ_Q_994, PAL_CPPI41_SR_DS_RESEQ_Q_995, PAL_CPPI41_SR_DS_RESEQ_Q_996, PAL_CPPI41_SR_DS_RESEQ_Q_997, PAL_CPPI41_SR_DS_RESEQ_Q_998, PAL_CPPI41_SR_DS_RESEQ_Q_999, PAL_CPPI41_SR_DS_RESEQ_Q_1000, PAL_CPPI41_SR_DS_RESEQ_Q_1001, PAL_CPPI41_SR_DS_RESEQ_Q_1002, PAL_CPPI41_SR_DS_RESEQ_Q_1003, PAL_CPPI41_SR_DS_RESEQ_Q_1004, PAL_CPPI41_SR_DS_RESEQ_Q_1005, PAL_CPPI41_SR_DS_RESEQ_Q_1006, PAL_CPPI41_SR_DS_RESEQ_Q_1007, PAL_CPPI41_SR_DS_RESEQ_Q_1008, PAL_CPPI41_SR_DS_RESEQ_Q_1009, PAL_CPPI41_SR_DS_RESEQ_Q_1010, PAL_CPPI41_SR_DS_RESEQ_Q_1011, PAL_CPPI41_SR_DS_RESEQ_Q_1012, PAL_CPPI41_SR_DS_RESEQ_Q_1013, PAL_CPPI41_SR_DS_RESEQ_Q_1014, PAL_CPPI41_SR_DS_RESEQ_Q_1015, PAL_CPPI41_SR_DS_RESEQ_Q_1016, PAL_CPPI41_SR_DS_RESEQ_Q_1017, PAL_CPPI41_SR_DS_RESEQ_Q_1018, PAL_CPPI41_SR_DS_RESEQ_Q_1019, PAL_CPPI41_SR_DS_RESEQ_Q_1020, PAL_CPPI41_SR_DS_RESEQ_Q_1021, PAL_CPPI41_SR_DS_RESEQ_Q_1022, PAL_CPPI41_SR_DS_RESEQ_Q_1023, PAL_CPPI41_SR_DS_RESEQ_Q_1024, PAL_CPPI41_SR_DS_RESEQ_Q_1025, PAL_CPPI41_SR_DS_RESEQ_Q_1026, PAL_CPPI41_SR_DS_RESEQ_Q_1027, PAL_CPPI41_SR_DS_RESEQ_Q_1028, PAL_CPPI41_SR_DS_RESEQ_Q_1029, PAL_CPPI41_SR_DS_RESEQ_Q_1030, PAL_CPPI41_SR_DS_RESEQ_Q_1031, PAL_CPPI41_SR_DS_RESEQ_Q_1032, PAL_CPPI41_SR_DS_RESEQ_Q_1033, PAL_CPPI41_SR_DS_RESEQ_Q_1034, PAL_CPPI41_SR_DS_RESEQ_Q_1035, PAL_CPPI41_SR_DS_RESEQ_Q_1036, PAL_CPPI41_SR_DS_RESEQ_Q_1037, PAL_CPPI41_SR_DS_RESEQ_Q_1038, PAL_CPPI41_SR_DS_RESEQ_Q_1039, PAL_CPPI41_SR_DS_RESEQ_Q_1040, PAL_CPPI41_SR_DS_RESEQ_Q_1041, PAL_CPPI41_SR_DS_RESEQ_Q_1042, PAL_CPPI41_SR_DS_RESEQ_Q_1043, PAL_CPPI41_SR_DS_RESEQ_Q_1044, PAL_CPPI41_SR_DS_RESEQ_Q_1045, PAL_CPPI41_SR_DS_RESEQ_Q_1046, PAL_CPPI41_SR_DS_RESEQ_Q_1047, PAL_CPPI41_SR_DS_RESEQ_Q_1048, PAL_CPPI41_SR_DS_RESEQ_Q_1049, PAL_CPPI41_SR_DS_RESEQ_Q_1050, PAL_CPPI41_SR_DS_RESEQ_Q_1051, PAL_CPPI41_SR_DS_RESEQ_Q_1052, PAL_CPPI41_SR_DS_RESEQ_Q_1053, PAL_CPPI41_SR_DS_RESEQ_Q_1054, PAL_CPPI41_SR_DS_RESEQ_Q_1055, PAL_CPPI41_SR_DS_RESEQ_Q_1056, PAL_CPPI41_SR_DS_RESEQ_Q_1057, PAL_CPPI41_SR_DS_RESEQ_Q_1058, PAL_CPPI41_SR_DS_RESEQ_Q_1059, PAL_CPPI41_SR_DS_RESEQ_Q_1060, PAL_CPPI41_SR_DS_RESEQ_Q_1061, PAL_CPPI41_SR_DS_RESEQ_Q_1062, PAL_CPPI41_SR_DS_RESEQ_Q_1063, PAL_CPPI41_SR_DS_RESEQ_Q_1064, PAL_CPPI41_SR_DS_RESEQ_Q_1065, PAL_CPPI41_SR_DS_RESEQ_Q_1066, PAL_CPPI41_SR_DS_RESEQ_Q_1067, PAL_CPPI41_SR_DS_RESEQ_Q_1068, PAL_CPPI41_SR_DS_RESEQ_Q_1069, PAL_CPPI41_SR_DS_RESEQ_Q_1070, PAL_CPPI41_SR_DS_RESEQ_Q_1071, PAL_CPPI41_SR_DS_RESEQ_Q_1072, PAL_CPPI41_SR_DS_RESEQ_Q_1073, PAL_CPPI41_SR_DS_RESEQ_Q_1074, PAL_CPPI41_SR_DS_RESEQ_Q_1075, PAL_CPPI41_SR_DS_RESEQ_Q_1076, PAL_CPPI41_SR_DS_RESEQ_Q_1077, PAL_CPPI41_SR_DS_RESEQ_Q_1078, PAL_CPPI41_SR_DS_RESEQ_Q_1079, PAL_CPPI41_SR_DS_RESEQ_Q_1080, PAL_CPPI41_SR_DS_RESEQ_Q_1081, PAL_CPPI41_SR_DS_RESEQ_Q_1082, PAL_CPPI41_SR_DS_RESEQ_Q_1083, PAL_CPPI41_SR_DS_RESEQ_Q_1084, PAL_CPPI41_SR_DS_RESEQ_Q_1085, PAL_CPPI41_SR_DS_RESEQ_Q_1086, PAL_CPPI41_SR_DS_RESEQ_Q_1087, PAL_CPPI41_SR_DS_RESEQ_Q_1088, PAL_CPPI41_SR_DS_RESEQ_Q_1089, PAL_CPPI41_SR_DS_RESEQ_Q_1090, PAL_CPPI41_SR_DS_RESEQ_Q_1091, PAL_CPPI41_SR_DS_RESEQ_Q_1092, PAL_CPPI41_SR_DS_RESEQ_Q_1093, PAL_CPPI41_SR_DS_RESEQ_Q_1094, PAL_CPPI41_SR_DS_RESEQ_Q_1095, PAL_CPPI41_SR_DS_RESEQ_Q_1096, PAL_CPPI41_SR_DS_RESEQ_Q_1097, PAL_CPPI41_SR_DS_RESEQ_Q_1098, PAL_CPPI41_SR_DS_RESEQ_Q_1099, PAL_CPPI41_SR_DS_RESEQ_Q_1100, PAL_CPPI41_SR_DS_RESEQ_Q_1101, PAL_CPPI41_SR_DS_RESEQ_Q_1102, PAL_CPPI41_SR_DS_RESEQ_Q_1103, PAL_CPPI41_SR_DS_RESEQ_Q_1104, PAL_CPPI41_SR_DS_RESEQ_Q_1105, PAL_CPPI41_SR_DS_RESEQ_Q_1106, PAL_CPPI41_SR_DS_RESEQ_Q_1107, PAL_CPPI41_SR_DS_RESEQ_Q_1108, PAL_CPPI41_SR_DS_RESEQ_Q_1109, PAL_CPPI41_SR_DS_RESEQ_Q_1110, PAL_CPPI41_SR_DS_RESEQ_Q_1111, PAL_CPPI41_SR_DS_RESEQ_Q_1112, PAL_CPPI41_SR_DS_RESEQ_Q_1113, PAL_CPPI41_SR_DS_RESEQ_Q_1114, PAL_CPPI41_SR_DS_RESEQ_Q_1115, PAL_CPPI41_SR_DS_RESEQ_Q_1116, PAL_CPPI41_SR_DS_RESEQ_Q_1117, PAL_CPPI41_SR_DS_RESEQ_Q_1118, PAL_CPPI41_SR_DS_RESEQ_Q_1119, PAL_CPPI41_SR_DS_RESEQ_Q_1120, PAL_CPPI41_SR_DS_RESEQ_Q_1121, PAL_CPPI41_SR_DS_RESEQ_Q_1122, PAL_CPPI41_SR_DS_RESEQ_Q_1123, PAL_CPPI41_SR_DS_RESEQ_Q_1124, PAL_CPPI41_SR_DS_RESEQ_Q_1125, PAL_CPPI41_SR_DS_RESEQ_Q_1126, PAL_CPPI41_SR_DS_RESEQ_Q_1127, PAL_CPPI41_SR_DS_RESEQ_Q_1128, PAL_CPPI41_SR_DS_RESEQ_Q_1129, PAL_CPPI41_SR_DS_RESEQ_Q_1130, PAL_CPPI41_SR_DS_RESEQ_Q_1131, PAL_CPPI41_SR_DS_RESEQ_Q_1132, PAL_CPPI41_SR_DS_RESEQ_Q_1133, PAL_CPPI41_SR_DS_RESEQ_Q_1134, PAL_CPPI41_SR_DS_RESEQ_Q_1135, PAL_CPPI41_SR_DS_RESEQ_Q_1136, PAL_CPPI41_SR_DS_RESEQ_Q_1137, PAL_CPPI41_SR_DS_RESEQ_Q_1138, PAL_CPPI41_SR_DS_RESEQ_Q_1139, PAL_CPPI41_SR_DS_RESEQ_Q_1140, PAL_CPPI41_SR_DS_RESEQ_Q_1141, PAL_CPPI41_SR_DS_RESEQ_Q_1142, PAL_CPPI41_SR_DS_RESEQ_Q_1143, PAL_CPPI41_SR_DS_RESEQ_Q_1144, PAL_CPPI41_SR_DS_RESEQ_Q_1145, PAL_CPPI41_SR_DS_RESEQ_Q_1146, PAL_CPPI41_SR_DS_RESEQ_Q_1147, PAL_CPPI41_SR_DS_RESEQ_Q_1148, PAL_CPPI41_SR_DS_RESEQ_Q_1149, PAL_CPPI41_SR_DS_RESEQ_Q_1150, PAL_CPPI41_SR_DS_RESEQ_Q_1151, PAL_CPPI41_SR_DS_RESEQ_Q_LAST = PAL_CPPI41_SR_DS_RESEQ_Q_1151, /* QoS PDSP QoS Queues */ PAL_CPPI41_SR_QPDSP_QOS_Q_BASE, PAL_CPPI41_SR_DOCSIS_TX_QPDSP_QOS_Q_BASE = PAL_CPPI41_SR_QPDSP_QOS_Q_BASE, PAL_CPPI41_SR_CLUSTER0_DOCSIS_TX_BE0_HIGH_QPDSP_QOS_Q_NUM = PAL_CPPI41_SR_DOCSIS_TX_QPDSP_QOS_Q_BASE, /* PAL_CPPI41_SR_Q_1152 */ PAL_CPPI41_SR_CLUSTER0_DOCSIS_TX_BE0_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1153 */ PAL_CPPI41_SR_CLUSTER1_DOCSIS_TX_BE1_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1154 */ PAL_CPPI41_SR_CLUSTER1_DOCSIS_TX_BE1_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1155 */ PAL_CPPI41_SR_CLUSTER2_DOCSIS_TX_BE2_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1156 */ PAL_CPPI41_SR_CLUSTER2_DOCSIS_TX_BE2_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1157 */ PAL_CPPI41_SR_CLUSTER3_DOCSIS_TX_BE3_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1158 */ PAL_CPPI41_SR_CLUSTER3_DOCSIS_TX_BE3_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1159 */ PAL_CPPI41_SR_CLUSTER4_DOCSIS_TX_BE4_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1160 */ PAL_CPPI41_SR_CLUSTER4_DOCSIS_TX_BE4_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1161 */ PAL_CPPI41_SR_CLUSTER5_DOCSIS_TX_BE5_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1162 */ PAL_CPPI41_SR_CLUSTER5_DOCSIS_TX_BE5_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1163 */ PAL_CPPI41_SR_CLUSTER6_DOCSIS_TX_BE6_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1164 */ PAL_CPPI41_SR_CLUSTER6_DOCSIS_TX_BE6_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1165 */ PAL_CPPI41_SR_CLUSTER7_DOCSIS_TX_BE7_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1166 */ PAL_CPPI41_SR_CLUSTER7_DOCSIS_TX_BE7_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1167 */ PAL_CPPI41_SR_CLUSTER8_DOCSIS_TX_BE8_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1168 */ PAL_CPPI41_SR_CLUSTER8_DOCSIS_TX_BE8_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1169 */ PAL_CPPI41_SR_CLUSTER9_DOCSIS_TX_BE9_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1170 */ PAL_CPPI41_SR_CLUSTER9_DOCSIS_TX_BE9_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1171 */ PAL_CPPI41_SR_CLUSTER10_DOCSIS_TX_BE10_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1172 */ PAL_CPPI41_SR_CLUSTER10_DOCSIS_TX_BE10_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1173 */ PAL_CPPI41_SR_CLUSTER11_DOCSIS_TX_BE11_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1174 */ PAL_CPPI41_SR_CLUSTER11_DOCSIS_TX_BE11_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1175 */ PAL_CPPI41_SR_CLUSTER12_DOCSIS_TX_BE12_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1176 */ PAL_CPPI41_SR_CLUSTER12_DOCSIS_TX_BE12_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1177 */ PAL_CPPI41_SR_CLUSTER13_DOCSIS_TX_BE13_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1178 */ PAL_CPPI41_SR_CLUSTER13_DOCSIS_TX_BE13_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1179 */ PAL_CPPI41_SR_CLUSTER14_DOCSIS_TX_BE14_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1180 */ PAL_CPPI41_SR_CLUSTER14_DOCSIS_TX_BE14_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1181 */ PAL_CPPI41_SR_CLUSTER15_DOCSIS_TX_BE15_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1182 */ PAL_CPPI41_SR_CLUSTER15_DOCSIS_TX_BE15_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1183 */ PAL_CPPI41_SR_DOCSIS_TX_QPDSP_QOS_Q_LAST = PAL_CPPI41_SR_CLUSTER15_DOCSIS_TX_BE15_LOW_QPDSP_QOS_Q_NUM, PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_BASE, PAL_CPPI41_SR_CLUSTER16_L2SW_DATA0_HIGH_QPDSP_QOS_Q_NUM = PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_BASE, /* PAL_CPPI41_SR_Q_1184 */ PAL_CPPI41_SR_CLUSTER16_L2SW_DATA0_MED_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1185 */ PAL_CPPI41_SR_CLUSTER16_L2SW_DATA0_MED_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1186 */ PAL_CPPI41_SR_CLUSTER16_L2SW_DATA0_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1187 */ PAL_CPPI41_SR_CLUSTER17_L2SW_MGMT0_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1188 */ PAL_CPPI41_SR_CLUSTER17_L2SW_MGMT0_MED_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1189 */ PAL_CPPI41_SR_CLUSTER17_L2SW_MGMT0_MED_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1190 */ PAL_CPPI41_SR_CLUSTER17_L2SW_MGMT0_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1191 */ PAL_CPPI41_SR_CLUSTER18_L2SW_MOCA0_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1192 */ PAL_CPPI41_SR_CLUSTER18_L2SW_MOCA0_MED_HIGH_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1193 */ PAL_CPPI41_SR_CLUSTER18_L2SW_MOCA0_MED_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1194 */ PAL_CPPI41_SR_CLUSTER18_L2SW_MOCA0_LOW_QPDSP_QOS_Q_NUM, /* PAL_CPPI41_SR_Q_1195 */ PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_LAST = PAL_CPPI41_SR_CLUSTER18_L2SW_MOCA0_LOW_QPDSP_QOS_Q_NUM, PAL_CPPI41_SR_QPDSP_QOS_Q_44, /* PAL_CPPI41_SR_Q_1196 */ PAL_CPPI41_SR_QPDSP_QOS_Q_45, /* PAL_CPPI41_SR_Q_1197 */ PAL_CPPI41_SR_QPDSP_QOS_Q_46, /* PAL_CPPI41_SR_Q_1198 */ PAL_CPPI41_SR_QPDSP_QOS_Q_47, /* PAL_CPPI41_SR_Q_1199 */ PAL_CPPI41_SR_QPDSP_QOS_Q_48, /* PAL_CPPI41_SR_Q_1200 */ PAL_CPPI41_SR_QPDSP_QOS_Q_49, /* PAL_CPPI41_SR_Q_1201 */ PAL_CPPI41_SR_QPDSP_QOS_Q_50, /* PAL_CPPI41_SR_Q_1202 */ PAL_CPPI41_SR_QPDSP_QOS_Q_51, /* PAL_CPPI41_SR_Q_1203 */ PAL_CPPI41_SR_QPDSP_QOS_Q_52, /* PAL_CPPI41_SR_Q_1204 */ PAL_CPPI41_SR_QPDSP_QOS_Q_53, /* PAL_CPPI41_SR_Q_1205 */ PAL_CPPI41_SR_QPDSP_QOS_Q_54, /* PAL_CPPI41_SR_Q_1206 */ PAL_CPPI41_SR_QPDSP_QOS_Q_55, /* PAL_CPPI41_SR_Q_1207 */ PAL_CPPI41_SR_QPDSP_QOS_Q_56, /* PAL_CPPI41_SR_Q_1208 */ PAL_CPPI41_SR_QPDSP_QOS_Q_57, /* PAL_CPPI41_SR_Q_1209 */ PAL_CPPI41_SR_QPDSP_QOS_Q_58, /* PAL_CPPI41_SR_Q_1200 */ PAL_CPPI41_SR_QPDSP_QOS_Q_59, /* PAL_CPPI41_SR_Q_1211 */ PAL_CPPI41_SR_QPDSP_QOS_Q_60, /* PAL_CPPI41_SR_Q_1212 */ PAL_CPPI41_SR_QPDSP_QOS_Q_61, /* PAL_CPPI41_SR_Q_1213 */ PAL_CPPI41_SR_QPDSP_QOS_Q_62, /* PAL_CPPI41_SR_Q_1214 */ PAL_CPPI41_SR_QPDSP_QOS_Q_63, /* PAL_CPPI41_SR_Q_1215 */ PAL_CPPI41_SR_QPDSP_QOS_Q_LAST = PAL_CPPI41_SR_QPDSP_QOS_Q_63, PAL_CPPI41_SR_PP_SYNCH_Q_BASE, PAL_CPPI41_SR_PP_SYNCH_Q_0 = PAL_CPPI41_SR_PP_SYNCH_Q_BASE, /* PAL_CPPI41_SR_Q_1216 */ PAL_CPPI41_SR_PP_SYNCH_Q_1, /* PAL_CPPI41_SR_Q_1217 */ PAL_CPPI41_SR_PP_SYNCH_Q_2, /* PAL_CPPI41_SR_Q_1218 */ PAL_CPPI41_SR_PP_SYNCH_Q_3, /* PAL_CPPI41_SR_Q_1219 */ PAL_CPPI41_SR_PP_SYNCH_Q_4, /* PAL_CPPI41_SR_Q_1220 */ PAL_CPPI41_SR_PP_SYNCH_Q_5, /* PAL_CPPI41_SR_Q_1221 */ PAL_CPPI41_SR_PP_SYNCH_Q_6, /* PAL_CPPI41_SR_Q_1222 */ PAL_CPPI41_SR_PP_SYNCH_Q_7, /* PAL_CPPI41_SR_Q_1223 */ PAL_CPPI41_SR_PP_SYNCH_Q_8, /* PAL_CPPI41_SR_Q_1224 */ PAL_CPPI41_SR_PP_SYNCH_Q_9, /* PAL_CPPI41_SR_Q_1225 */ PAL_CPPI41_SR_PP_SYNCH_Q_10, /* PAL_CPPI41_SR_Q_1226 */ PAL_CPPI41_SR_PP_SYNCH_Q_11, /* PAL_CPPI41_SR_Q_1227 */ PAL_CPPI41_SR_PP_SYNCH_Q_12, /* PAL_CPPI41_SR_Q_1228 */ PAL_CPPI41_SR_PP_SYNCH_Q_13, /* PAL_CPPI41_SR_Q_1229 */ PAL_CPPI41_SR_PP_SYNCH_Q_14, /* PAL_CPPI41_SR_Q_1230 */ PAL_CPPI41_SR_PP_SYNCH_Q_15, /* PAL_CPPI41_SR_Q_1231 */ PAL_CPPI41_SR_PP_SYNCH_Q_16, /* PAL_CPPI41_SR_Q_1232 */ PAL_CPPI41_SR_PP_SYNCH_Q_17, /* PAL_CPPI41_SR_Q_1233 */ PAL_CPPI41_SR_PP_SYNCH_Q_18, /* PAL_CPPI41_SR_Q_1234 */ PAL_CPPI41_SR_PP_SYNCH_Q_19, /* PAL_CPPI41_SR_Q_1235 */ PAL_CPPI41_SR_PP_SYNCH_Q_20, /* PAL_CPPI41_SR_Q_1236 */ PAL_CPPI41_SR_PP_SYNCH_Q_21, /* PAL_CPPI41_SR_Q_1237 */ PAL_CPPI41_SR_PP_SYNCH_Q_22, /* PAL_CPPI41_SR_Q_1238 */ PAL_CPPI41_SR_PP_SYNCH_Q_23, /* PAL_CPPI41_SR_Q_1239 */ PAL_CPPI41_SR_PP_SYNCH_Q_24, /* PAL_CPPI41_SR_Q_1240 */ PAL_CPPI41_SR_PP_SYNCH_Q_25, /* PAL_CPPI41_SR_Q_1241 */ PAL_CPPI41_SR_PP_SYNCH_Q_26, /* PAL_CPPI41_SR_Q_1242 */ PAL_CPPI41_SR_PP_SYNCH_Q_27, /* PAL_CPPI41_SR_Q_1243 */ PAL_CPPI41_SR_PP_SYNCH_Q_28, /* PAL_CPPI41_SR_Q_1244 */ PAL_CPPI41_SR_PP_SYNCH_Q_29, /* PAL_CPPI41_SR_Q_1245 */ PAL_CPPI41_SR_PP_SYNCH_Q_30, /* PAL_CPPI41_SR_Q_1246 */ PAL_CPPI41_SR_PP_SYNCH_Q_31, /* PAL_CPPI41_SR_Q_1247 */ PAL_CPPI41_SR_PP_SYNCH_Q_32, /* PAL_CPPI41_SR_Q_1248 */ PAL_CPPI41_SR_PP_SYNCH_Q_33, /* PAL_CPPI41_SR_Q_1249 */ PAL_CPPI41_SR_PP_SYNCH_Q_34, /* PAL_CPPI41_SR_Q_1250 */ PAL_CPPI41_SR_PP_SYNCH_Q_35, /* PAL_CPPI41_SR_Q_1251 */ PAL_CPPI41_SR_PP_SYNCH_Q_36, /* PAL_CPPI41_SR_Q_1252 */ PAL_CPPI41_SR_PP_SYNCH_Q_37, /* PAL_CPPI41_SR_Q_1253 */ PAL_CPPI41_SR_PP_SYNCH_Q_38, /* PAL_CPPI41_SR_Q_1254 */ PAL_CPPI41_SR_PP_SYNCH_Q_39, /* PAL_CPPI41_SR_Q_1255 */ PAL_CPPI41_SR_PP_SYNCH_Q_40, /* PAL_CPPI41_SR_Q_1256 */ PAL_CPPI41_SR_PP_SYNCH_Q_41, /* PAL_CPPI41_SR_Q_1257 */ PAL_CPPI41_SR_PP_SYNCH_Q_42, /* PAL_CPPI41_SR_Q_1258 */ PAL_CPPI41_SR_PP_SYNCH_Q_43, /* PAL_CPPI41_SR_Q_1259 */ PAL_CPPI41_SR_PP_SYNCH_Q_44, /* PAL_CPPI41_SR_Q_1260 */ PAL_CPPI41_SR_PP_SYNCH_Q_45, /* PAL_CPPI41_SR_Q_1261 */ PAL_CPPI41_SR_PP_SYNCH_Q_46, /* PAL_CPPI41_SR_Q_1262 */ PAL_CPPI41_SR_PP_SYNCH_Q_47, /* PAL_CPPI41_SR_Q_1263 */ PAL_CPPI41_SR_PP_SYNCH_Q_48, /* PAL_CPPI41_SR_Q_1264 */ PAL_CPPI41_SR_PP_SYNCH_Q_49, /* PAL_CPPI41_SR_Q_1265 */ PAL_CPPI41_SR_PP_SYNCH_Q_50, /* PAL_CPPI41_SR_Q_1266 */ PAL_CPPI41_SR_PP_SYNCH_Q_51, /* PAL_CPPI41_SR_Q_1267 */ PAL_CPPI41_SR_PP_SYNCH_Q_52, /* PAL_CPPI41_SR_Q_1268 */ PAL_CPPI41_SR_PP_SYNCH_Q_53, /* PAL_CPPI41_SR_Q_1269 */ PAL_CPPI41_SR_PP_SYNCH_Q_54, /* PAL_CPPI41_SR_Q_1270 */ PAL_CPPI41_SR_PP_SYNCH_Q_55, /* PAL_CPPI41_SR_Q_1271 */ PAL_CPPI41_SR_PP_SYNCH_Q_56, /* PAL_CPPI41_SR_Q_1272 */ PAL_CPPI41_SR_PP_SYNCH_Q_57, /* PAL_CPPI41_SR_Q_1273 */ PAL_CPPI41_SR_PP_SYNCH_Q_58, /* PAL_CPPI41_SR_Q_1274 */ PAL_CPPI41_SR_PP_SYNCH_Q_59, /* PAL_CPPI41_SR_Q_1275 */ PAL_CPPI41_SR_PP_SYNCH_Q_60, /* PAL_CPPI41_SR_Q_1276 */ PAL_CPPI41_SR_PP_SYNCH_Q_61, /* PAL_CPPI41_SR_Q_1277 */ PAL_CPPI41_SR_PP_SYNCH_Q_62, /* PAL_CPPI41_SR_Q_1278 */ PAL_CPPI41_SR_PP_SYNCH_Q_63, /* PAL_CPPI41_SR_Q_1279 */ PAL_CPPI41_SR_PP_SYNCH_Q_LAST = PAL_CPPI41_SR_PP_SYNCH_Q_63, /* Multicast Cache Queues */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_BASE, PAL_CPPI41_SR_MULTICAST_CACHE_Q_0 = PAL_CPPI41_SR_MULTICAST_CACHE_Q_BASE, /* PAL_CPPI41_SR_Q_1280 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_1, /* PAL_CPPI41_SR_Q_1281 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_2, /* PAL_CPPI41_SR_Q_1282 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_3, /* PAL_CPPI41_SR_Q_1283 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_4, /* PAL_CPPI41_SR_Q_1284 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_5, /* PAL_CPPI41_SR_Q_1285 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_6, /* PAL_CPPI41_SR_Q_1286 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_7, /* PAL_CPPI41_SR_Q_1287 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_8, /* PAL_CPPI41_SR_Q_1288 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_9, /* PAL_CPPI41_SR_Q_1289 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_10, /* PAL_CPPI41_SR_Q_1290 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_11, /* PAL_CPPI41_SR_Q_1291 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_12, /* PAL_CPPI41_SR_Q_1292 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_13, /* PAL_CPPI41_SR_Q_1293 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_14, /* PAL_CPPI41_SR_Q_1294 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_15, /* PAL_CPPI41_SR_Q_1295 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_16, /* PAL_CPPI41_SR_Q_1296 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_17, /* PAL_CPPI41_SR_Q_1297 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_18, /* PAL_CPPI41_SR_Q_1298 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_19, /* PAL_CPPI41_SR_Q_1299 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_20, /* PAL_CPPI41_SR_Q_1300 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_21, /* PAL_CPPI41_SR_Q_1301 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_22, /* PAL_CPPI41_SR_Q_1302 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_23, /* PAL_CPPI41_SR_Q_1303 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_24, /* PAL_CPPI41_SR_Q_1304 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_25, /* PAL_CPPI41_SR_Q_1305 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_26, /* PAL_CPPI41_SR_Q_1306 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_27, /* PAL_CPPI41_SR_Q_1307 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_28, /* PAL_CPPI41_SR_Q_1308 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_29, /* PAL_CPPI41_SR_Q_1309 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_30, /* PAL_CPPI41_SR_Q_1310 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_31, /* PAL_CPPI41_SR_Q_1311 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_32, /* PAL_CPPI41_SR_Q_1312 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_33, /* PAL_CPPI41_SR_Q_1313 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_34, /* PAL_CPPI41_SR_Q_1314 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_35, /* PAL_CPPI41_SR_Q_1315 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_36, /* PAL_CPPI41_SR_Q_1316 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_37, /* PAL_CPPI41_SR_Q_1317 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_38, /* PAL_CPPI41_SR_Q_1318 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_39, /* PAL_CPPI41_SR_Q_1319 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_40, /* PAL_CPPI41_SR_Q_1320 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_41, /* PAL_CPPI41_SR_Q_1321 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_42, /* PAL_CPPI41_SR_Q_1322 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_43, /* PAL_CPPI41_SR_Q_1323 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_44, /* PAL_CPPI41_SR_Q_1324 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_45, /* PAL_CPPI41_SR_Q_1325 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_46, /* PAL_CPPI41_SR_Q_1326 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_47, /* PAL_CPPI41_SR_Q_1327 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_48, /* PAL_CPPI41_SR_Q_1328 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_49, /* PAL_CPPI41_SR_Q_1329 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_50, /* PAL_CPPI41_SR_Q_1330 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_51, /* PAL_CPPI41_SR_Q_1331 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_52, /* PAL_CPPI41_SR_Q_1332 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_53, /* PAL_CPPI41_SR_Q_1333 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_54, /* PAL_CPPI41_SR_Q_1334 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_55, /* PAL_CPPI41_SR_Q_1335 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_56, /* PAL_CPPI41_SR_Q_1336 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_57, /* PAL_CPPI41_SR_Q_1337 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_58, /* PAL_CPPI41_SR_Q_1338 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_59, /* PAL_CPPI41_SR_Q_1339 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_60, /* PAL_CPPI41_SR_Q_1340 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_61, /* PAL_CPPI41_SR_Q_1341 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_62, /* PAL_CPPI41_SR_Q_1342 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_63, /* PAL_CPPI41_SR_Q_1343 */ PAL_CPPI41_SR_MULTICAST_CACHE_Q_LAST = PAL_CPPI41_SR_MULTICAST_CACHE_Q_63, /* Queues 1344-1375 are unassigned */ PAL_CPPI41_SR_Q_1344, /* PAL_CPPI41_SR_Q_1344 */ PAL_CPPI41_SR_Q_1345, /* PAL_CPPI41_SR_Q_1345 */ PAL_CPPI41_SR_Q_1346, /* PAL_CPPI41_SR_Q_1346 */ PAL_CPPI41_SR_Q_1347, /* PAL_CPPI41_SR_Q_1347 */ PAL_CPPI41_SR_Q_1348, /* PAL_CPPI41_SR_Q_1348 */ PAL_CPPI41_SR_Q_1349, /* PAL_CPPI41_SR_Q_1349 */ PAL_CPPI41_SR_Q_1350, /* PAL_CPPI41_SR_Q_1350 */ PAL_CPPI41_SR_Q_1351, /* PAL_CPPI41_SR_Q_1351 */ PAL_CPPI41_SR_Q_1352, /* PAL_CPPI41_SR_Q_1352 */ PAL_CPPI41_SR_Q_1353, /* PAL_CPPI41_SR_Q_1353 */ PAL_CPPI41_SR_Q_1354, /* PAL_CPPI41_SR_Q_1354 */ PAL_CPPI41_SR_Q_1355, /* PAL_CPPI41_SR_Q_1355 */ PAL_CPPI41_SR_Q_1356, /* PAL_CPPI41_SR_Q_1356 */ PAL_CPPI41_SR_Q_1357, /* PAL_CPPI41_SR_Q_1357 */ PAL_CPPI41_SR_Q_1358, /* PAL_CPPI41_SR_Q_1358 */ PAL_CPPI41_SR_Q_1359, /* PAL_CPPI41_SR_Q_1359 */ PAL_CPPI41_SR_Q_1360, /* PAL_CPPI41_SR_Q_1360 */ PAL_CPPI41_SR_Q_1361, /* PAL_CPPI41_SR_Q_1361 */ PAL_CPPI41_SR_Q_1362, /* PAL_CPPI41_SR_Q_1362 */ PAL_CPPI41_SR_Q_1363, /* PAL_CPPI41_SR_Q_1363 */ PAL_CPPI41_SR_Q_1364, /* PAL_CPPI41_SR_Q_1364 */ PAL_CPPI41_SR_Q_1365, /* PAL_CPPI41_SR_Q_1365 */ PAL_CPPI41_SR_Q_1366, /* PAL_CPPI41_SR_Q_1366 */ PAL_CPPI41_SR_Q_1367, /* PAL_CPPI41_SR_Q_1367 */ PAL_CPPI41_SR_Q_1368, /* PAL_CPPI41_SR_Q_1368 */ PAL_CPPI41_SR_Q_1369, /* PAL_CPPI41_SR_Q_1369 */ PAL_CPPI41_SR_Q_1370, /* PAL_CPPI41_SR_Q_1370 */ PAL_CPPI41_SR_Q_1371, /* PAL_CPPI41_SR_Q_1371 */ PAL_CPPI41_SR_Q_1372, /* PAL_CPPI41_SR_Q_1372 */ PAL_CPPI41_SR_Q_1373, /* PAL_CPPI41_SR_Q_1373 */ PAL_CPPI41_SR_Q_1374, /* PAL_CPPI41_SR_Q_1374 */ PAL_CPPI41_SR_Q_1375, /* PAL_CPPI41_SR_Q_1375 */ /* Proxy PDSP Input Queues */ PAL_CPPI41_SR_PrxPDSP_Q_BASE, PAL_CPPI41_SR_L2SW_DATA0_PrxPDSP_Q_NUM = PAL_CPPI41_SR_PrxPDSP_Q_BASE, /* PAL_CPPI41_SR_Q_1376 */ PAL_CPPI41_SR_L2SW_MGMT0_PrxPDSP_Q_NUM, /* PAL_CPPI41_SR_Q_1377 */ PAL_CPPI41_SR_PrxPDSP_Q_2, /* PAL_CPPI41_SR_Q_1378 */ PAL_CPPI41_SR_PrxPDSP_Q_3, /* PAL_CPPI41_SR_Q_1379 */ PAL_CPPI41_SR_PrxPDSP_Q_4, /* PAL_CPPI41_SR_Q_1380 */ PAL_CPPI41_SR_PrxPDSP_Q_5, /* PAL_CPPI41_SR_Q_1381 */ PAL_CPPI41_SR_PrxPDSP_Q_6, /* PAL_CPPI41_SR_Q_1382 */ PAL_CPPI41_SR_PrxPDSP_Q_7, /* PAL_CPPI41_SR_Q_1383 */ PAL_CPPI41_SR_PrxPDSP_Q_8, /* PAL_CPPI41_SR_Q_1384 */ PAL_CPPI41_SR_PrxPDSP_Q_9, /* PAL_CPPI41_SR_Q_1385 */ PAL_CPPI41_SR_PrxPDSP_Q_10, /* PAL_CPPI41_SR_Q_1386 */ PAL_CPPI41_SR_PrxPDSP_Q_11, /* PAL_CPPI41_SR_Q_1387 */ PAL_CPPI41_SR_PrxPDSP_Q_12, /* PAL_CPPI41_SR_Q_1388 */ PAL_CPPI41_SR_PrxPDSP_Q_13, /* PAL_CPPI41_SR_Q_1389 */ PAL_CPPI41_SR_PrxPDSP_Q_14, /* PAL_CPPI41_SR_Q_1390 */ PAL_CPPI41_SR_PrxPDSP_Q_15, /* PAL_CPPI41_SR_Q_1391 */ PAL_CPPI41_SR_PrxPDSP_Q_16, /* PAL_CPPI41_SR_Q_1392 */ PAL_CPPI41_SR_PrxPDSP_Q_17, /* PAL_CPPI41_SR_Q_1393 */ PAL_CPPI41_SR_PrxPDSP_Q_18, /* PAL_CPPI41_SR_Q_1394 */ PAL_CPPI41_SR_PrxPDSP_Q_19, /* PAL_CPPI41_SR_Q_1395 */ PAL_CPPI41_SR_PrxPDSP_Q_20, /* PAL_CPPI41_SR_Q_1396 */ PAL_CPPI41_SR_PrxPDSP_Q_21, /* PAL_CPPI41_SR_Q_1397 */ PAL_CPPI41_SR_PrxPDSP_Q_22, /* PAL_CPPI41_SR_Q_1398 */ PAL_CPPI41_SR_PrxPDSP_Q_23, /* PAL_CPPI41_SR_Q_1399 */ PAL_CPPI41_SR_PrxPDSP_Q_24, /* PAL_CPPI41_SR_Q_1400 */ PAL_CPPI41_SR_PrxPDSP_Q_25, /* PAL_CPPI41_SR_Q_1401 */ PAL_CPPI41_SR_PrxPDSP_Q_26, /* PAL_CPPI41_SR_Q_1402 */ PAL_CPPI41_SR_PrxPDSP_Q_27, /* PAL_CPPI41_SR_Q_1403 */ PAL_CPPI41_SR_PrxPDSP_Q_28, /* PAL_CPPI41_SR_Q_1404 */ PAL_CPPI41_SR_PrxPDSP_Q_29, /* PAL_CPPI41_SR_Q_1405 */ PAL_CPPI41_SR_PrxPDSP_Q_30, /* PAL_CPPI41_SR_Q_1406 */ PAL_CPPI41_SR_PrxPDSP_Q_31, /* PAL_CPPI41_SR_Q_1407 */ PAL_CPPI41_SR_PrxPDSP_Q_LAST = PAL_CPPI41_SR_PrxPDSP_Q_31, /* Cache Offloader PDSP Input Queues */ PAL_CPPI41_SR_CoePDSP_Q_BASE, PAL_CPPI41_SR_CoePDSP_Q_0 = PAL_CPPI41_SR_CoePDSP_Q_BASE, /* PAL_CPPI41_SR_Q_1408 */ PAL_CPPI41_SR_CoePDSP_Q_1, /* PAL_CPPI41_SR_Q_1409 */ PAL_CPPI41_SR_CoePDSP_Q_2, /* PAL_CPPI41_SR_Q_1410 */ PAL_CPPI41_SR_CoePDSP_Q_3, /* PAL_CPPI41_SR_Q_1411 */ PAL_CPPI41_SR_CoePDSP_Q_4, /* PAL_CPPI41_SR_Q_1412 */ PAL_CPPI41_SR_CoePDSP_Q_5, /* PAL_CPPI41_SR_Q_1413 */ PAL_CPPI41_SR_CoePDSP_Q_6, /* PAL_CPPI41_SR_Q_1414 */ PAL_CPPI41_SR_CoePDSP_Q_7, /* PAL_CPPI41_SR_Q_1415 */ PAL_CPPI41_SR_CoePDSP_Q_8, /* PAL_CPPI41_SR_Q_1416 */ PAL_CPPI41_SR_CoePDSP_Q_9, /* PAL_CPPI41_SR_Q_1417 */ PAL_CPPI41_SR_CoePDSP_Q_10, /* PAL_CPPI41_SR_Q_1418 */ PAL_CPPI41_SR_CoePDSP_Q_11, /* PAL_CPPI41_SR_Q_1419 */ PAL_CPPI41_SR_CoePDSP_Q_12, /* PAL_CPPI41_SR_Q_1420 */ PAL_CPPI41_SR_CoePDSP_Q_13, /* PAL_CPPI41_SR_Q_1421 */ PAL_CPPI41_SR_CoePDSP_Q_14, /* PAL_CPPI41_SR_Q_1422 */ PAL_CPPI41_SR_CoePDSP_Q_15, /* PAL_CPPI41_SR_Q_1423 */ PAL_CPPI41_SR_CoePDSP_Q_LAST = PAL_CPPI41_SR_CoePDSP_Q_15, PAL_CPPI41_SR_COE_FORWARDING_APPLICATION_Q_NUM, /* PAL_CPPI41_SR_Q_1424 */ /* Queues 1425 - 1438 are unassigned */ PAL_CPPI41_SR_Q_1425, PAL_CPPI41_SR_Q_1426, PAL_CPPI41_SR_Q_1427, PAL_CPPI41_SR_Q_1428, PAL_CPPI41_SR_Q_1429, PAL_CPPI41_SR_Q_1430, PAL_CPPI41_SR_Q_1431, PAL_CPPI41_SR_Q_1432, PAL_CPPI41_SR_Q_1433, PAL_CPPI41_SR_Q_1434, PAL_CPPI41_SR_Q_1435, PAL_CPPI41_SR_Q_1436, PAL_CPPI41_SR_Q_1437, PAL_CPPI41_SR_Q_1438, PAL_CPPI41_SR_VOICE_DSP_C55_INPUT_Q_NUM, /* Classifier1 PDSP Input Queues */ PAL_CPPI41_SR_C1PDSP_Q_BASE, PAL_CPPI41_SR_C1PDSP_Q_0 = PAL_CPPI41_SR_C1PDSP_Q_BASE, /* PAL_CPPI41_SR_Q_1440 */ PAL_CPPI41_SR_C1PDSP_Q_1, /* PAL_CPPI41_SR_Q_1441 */ PAL_CPPI41_SR_C1PDSP_Q_2, /* PAL_CPPI41_SR_Q_1442 */ PAL_CPPI41_SR_C1PDSP_Q_3, /* PAL_CPPI41_SR_Q_1443 */ PAL_CPPI41_SR_C1PDSP_Q_4, /* PAL_CPPI41_SR_Q_1444 */ PAL_CPPI41_SR_C1PDSP_Q_5, /* PAL_CPPI41_SR_Q_1445 */ PAL_CPPI41_SR_C1PDSP_Q_6, /* PAL_CPPI41_SR_Q_1446 */ PAL_CPPI41_SR_C1PDSP_Q_7, /* PAL_CPPI41_SR_Q_1447 */ PAL_CPPI41_SR_C1PDSP_Q_LAST = PAL_CPPI41_SR_C1PDSP_Q_7, /* Classifier2 PDSP Input Queues */ PAL_CPPI41_SR_C2PDSP_Q_BASE, PAL_CPPI41_SR_C2PDSP_Q_0 = PAL_CPPI41_SR_C2PDSP_Q_BASE, /* PAL_CPPI41_SR_Q_1448 */ PAL_CPPI41_SR_C2PDSP_Q_1, /* PAL_CPPI41_SR_Q_1449 */ PAL_CPPI41_SR_C2PDSP_Q_2, /* PAL_CPPI41_SR_Q_1450 */ PAL_CPPI41_SR_C2PDSP_Q_3, /* PAL_CPPI41_SR_Q_1451 */ PAL_CPPI41_SR_C2PDSP_Q_4, /* PAL_CPPI41_SR_Q_1452 */ PAL_CPPI41_SR_C2PDSP_Q_5, /* PAL_CPPI41_SR_Q_1453 */ PAL_CPPI41_SR_C2PDSP_Q_6, /* PAL_CPPI41_SR_Q_1454 */ PAL_CPPI41_SR_C2PDSP_Q_7, /* PAL_CPPI41_SR_Q_1455 */ PAL_CPPI41_SR_C2PDSP_Q_LAST = PAL_CPPI41_SR_C2PDSP_Q_7, /* Modifier PDSP Input Queues */ PAL_CPPI41_SR_MPDSP_Q_BASE, PAL_CPPI41_SR_MPDSP_Q_0 = PAL_CPPI41_SR_MPDSP_Q_BASE, /* PAL_CPPI41_SR_Q_1456 */ PAL_CPPI41_SR_MPDSP_Q_1, /* PAL_CPPI41_SR_Q_1457 */ PAL_CPPI41_SR_MPDSP_Q_2, /* PAL_CPPI41_SR_Q_1458 */ PAL_CPPI41_SR_MPDSP_Q_3, /* PAL_CPPI41_SR_Q_1459 */ PAL_CPPI41_SR_MPDSP_Q_4, /* PAL_CPPI41_SR_Q_1460 */ PAL_CPPI41_SR_MPDSP_Q_5, /* PAL_CPPI41_SR_Q_1461 */ PAL_CPPI41_SR_MPDSP_Q_6, /* PAL_CPPI41_SR_Q_1462 */ PAL_CPPI41_SR_MPDSP_Q_7, /* PAL_CPPI41_SR_Q_1463 */ PAL_CPPI41_SR_MPDSP_Q_LAST = PAL_CPPI41_SR_MPDSP_Q_7, /* Host to QoS PDSP Input Queues */ PAL_CPPI41_SR_HOST_TO_QPDSP_Q_BASE, PAL_CPPI41_SR_HOST_TO_QPDSP_Q_0 = PAL_CPPI41_SR_HOST_TO_QPDSP_Q_BASE, /* PAL_CPPI41_SR_Q_1464 */ PAL_CPPI41_SR_HOST_TO_QPDSP_LOW_EMB_TYPE_Q_NUM, /* PAL_CPPI41_SR_Q_1465 */ PAL_CPPI41_SR_HOST_TO_QPDSP_Q_2, /* PAL_CPPI41_SR_Q_1466 */ PAL_CPPI41_SR_HOST_TO_QPDSP_HIGH_EMB_TYPE_Q_NUM, /* PAL_CPPI41_SR_Q_1467 */ PAL_CPPI41_SR_HOST_TO_QPDSP_Q_4, /* PAL_CPPI41_SR_Q_1468 */ PAL_CPPI41_SR_HOST_TO_QPDSP_Q_5, /* PAL_CPPI41_SR_Q_1469 */ PAL_CPPI41_SR_HOST_TO_QPDSP_Q_6, /* PAL_CPPI41_SR_Q_1470 */ PAL_CPPI41_SR_HOST_TO_QPDSP_Q_7, /* PAL_CPPI41_SR_Q_1471 */ PAL_CPPI41_SR_HOST_TO_QPDSP_Q_LAST = PAL_CPPI41_SR_HOST_TO_QPDSP_Q_7, /* Prefetcher PDSP Input Queues */ PAL_CPPI41_SR_PPDSP_Q_BASE, PAL_CPPI41_SR_PPDSP_LOW_Q_NUM = PAL_CPPI41_SR_PPDSP_Q_BASE, /* PAL_CPPI41_SR_Q_1472 */ PAL_CPPI41_SR_PPDSP_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1473 */ PAL_CPPI41_SR_PPDSP_Q_2, /* PAL_CPPI41_SR_Q_1474 */ PAL_CPPI41_SR_PPDSP_Q_3, /* PAL_CPPI41_SR_Q_1475 */ PAL_CPPI41_SR_PPDSP_Q_4, /* PAL_CPPI41_SR_Q_1476 */ PAL_CPPI41_SR_PPDSP_Q_5, /* PAL_CPPI41_SR_Q_1477 */ PAL_CPPI41_SR_PPDSP_Q_6, /* PAL_CPPI41_SR_Q_1478 */ PAL_CPPI41_SR_PPDSP_Q_7, /* PAL_CPPI41_SR_Q_1479 */ PAL_CPPI41_SR_PPDSP_Q_LAST = PAL_CPPI41_SR_PPDSP_Q_7, /* Us Prefetcher PDSP Input Queues */ PAL_CPPI41_SR_UsPrefPDSP_Q_BASE, PAL_CPPI41_SR_UsPrefPDSP_Q_0 = PAL_CPPI41_SR_UsPrefPDSP_Q_BASE, /* PAL_CPPI41_SR_Q_1480 */ PAL_CPPI41_SR_UsPrefPDSP_Q_1, /* PAL_CPPI41_SR_Q_1481 */ PAL_CPPI41_SR_UsPrefPDSP_Q_2, /* PAL_CPPI41_SR_Q_1482 */ PAL_CPPI41_SR_UsPrefPDSP_Q_3, /* PAL_CPPI41_SR_Q_1483 */ PAL_CPPI41_SR_UsPrefPDSP_Q_4, /* PAL_CPPI41_SR_Q_1484 */ PAL_CPPI41_SR_UsPrefPDSP_Q_5, /* PAL_CPPI41_SR_Q_1485 */ PAL_CPPI41_SR_UsPrefPDSP_Q_6, /* PAL_CPPI41_SR_Q_1486 */ PAL_CPPI41_SR_UsPrefPDSP_Q_7, /* PAL_CPPI41_SR_Q_1487 */ PAL_CPPI41_SR_UsPrefPDSP_Q_8, /* PAL_CPPI41_SR_Q_1488 */ PAL_CPPI41_SR_UsPrefPDSP_Q_9, /* PAL_CPPI41_SR_Q_1489 */ PAL_CPPI41_SR_UsPrefPDSP_Q_10, /* PAL_CPPI41_SR_Q_1490 */ PAL_CPPI41_SR_UsPrefPDSP_Q_11, /* PAL_CPPI41_SR_Q_1491 */ PAL_CPPI41_SR_UsPrefPDSP_Q_12, /* PAL_CPPI41_SR_Q_1492 */ PAL_CPPI41_SR_UsPrefPDSP_Q_13, /* PAL_CPPI41_SR_Q_1493 */ PAL_CPPI41_SR_UsPrefPDSP_Q_14, /* PAL_CPPI41_SR_Q_1494 */ PAL_CPPI41_SR_UsPrefPDSP_Q_15, /* PAL_CPPI41_SR_Q_1495 */ PAL_CPPI41_SR_UsPrefPDSP_Q_16, /* PAL_CPPI41_SR_Q_1496 */ PAL_CPPI41_SR_UsPrefPDSP_Q_17, /* PAL_CPPI41_SR_Q_1497 */ PAL_CPPI41_SR_UsPrefPDSP_Q_LAST = PAL_CPPI41_SR_UsPrefPDSP_Q_17, /* Host TX Complete Queues */ PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_BASE, PAL_CPPI41_SR_HOST_TX_COMPLETE_LOW_Q_NUM = PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_BASE, /* PAL_CPPI41_SR_Q_1498 */ PAL_CPPI41_SR_HOST_TX_COMPLETE_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1499 */ PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_2, /* PAL_CPPI41_SR_Q_1500 */ PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_3, /* PAL_CPPI41_SR_Q_1501 */ PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_4, /* PAL_CPPI41_SR_Q_1502 */ PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_5, /* PAL_CPPI41_SR_Q_1503 */ PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_6, /* PAL_CPPI41_SR_Q_1504 */ PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_7, /* PAL_CPPI41_SR_Q_1505 */ PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_LAST = PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_7, /* Host RX Queues */ PAL_CPPI41_SR_HOST_RX_Q_BASE, PAL_CPPI41_SR_CNI_LOW_HOST_RX_Q_NUM = PAL_CPPI41_SR_HOST_RX_Q_BASE, /* PAL_CPPI41_SR_Q_1506 */ PAL_CPPI41_SR_CNI_HIGH_HOST_RX_Q_NUM, /* PAL_CPPI41_SR_Q_1507 */ PAL_CPPI41_SR_DOCSIS_MGMT_HOST_RX_Q_NUM, /* PAL_CPPI41_SR_Q_1508 */ PAL_CPPI41_SR_VOICE_DSP_C55_HOST_RX_Q_NUM, /* PAL_CPPI41_SR_Q_1509 */ PAL_CPPI41_SR_MPEG_HOST_RX_Q_NUM, /* PAL_CPPI41_SR_Q_1510 */ PAL_CPPI41_SR_L2SW_HOST_RX_Q_BASE, PAL_CPPI41_SR_L2SW_DATA0_HOST_RX_Q_NUM = PAL_CPPI41_SR_L2SW_HOST_RX_Q_BASE, /* PAL_CPPI41_SR_Q_1511 */ PAL_CPPI41_SR_L2SW_MGMT0_HOST_RX_Q_NUM, /* PAL_CPPI41_SR_Q_1512 */ PAL_CPPI41_SR_L2SW_HOST_RX_Q_LAST = PAL_CPPI41_SR_L2SW_MGMT0_HOST_RX_Q_NUM, PAL_CPPI41_SR_HOST_RX_Q_7, /* PAL_CPPI41_SR_Q_1513 */ PAL_CPPI41_SR_HOST_RX_Q_8, /* PAL_CPPI41_SR_Q_1514 */ PAL_CPPI41_SR_HOST_RX_Q_9, /* PAL_CPPI41_SR_Q_1515 */ PAL_CPPI41_SR_HOST_RX_Q_10, /* PAL_CPPI41_SR_Q_1516 */ PAL_CPPI41_SR_HOST_RX_Q_11, /* PAL_CPPI41_SR_Q_1517 */ PAL_CPPI41_SR_HOST_RX_Q_12, /* PAL_CPPI41_SR_Q_1518 */ PAL_CPPI41_SR_HOST_RX_Q_13, /* PAL_CPPI41_SR_Q_1519 */ PAL_CPPI41_SR_HOST_RX_Q_14, /* PAL_CPPI41_SR_Q_1520 */ PAL_CPPI41_SR_HOST_RX_Q_15, /* PAL_CPPI41_SR_Q_1521 */ PAL_CPPI41_SR_HOST_RX_Q_LAST = PAL_CPPI41_SR_HOST_RX_Q_15, /* PP to Host Events Queues */ PAL_CPPI41_SR_Q_1522, /* PAL_CPPI41_SR_Q_1522 */ PAL_CPPI41_SR_Q_1523, /* PAL_CPPI41_SR_Q_1523 */ PAL_CPPI41_SR_Q_1524, /* PAL_CPPI41_SR_Q_1524 */ PAL_CPPI41_SR_Q_1525, /* PAL_CPPI41_SR_Q_1525 */ /* PP Free Descriptors Queues */ PAL_CPPI41_SR_FD_PP_Q_BASE, PAL_CPPI41_SR_PPDSP_PREFETCH_DESC_FD_Q_NUM = PAL_CPPI41_SR_FD_PP_Q_BASE, /* PAL_CPPI41_SR_Q_1526 */ PAL_CPPI41_SR_Q_1527, /* PAL_CPPI41_SR_Q_1527 */ PAL_CPPI41_SR_Q_1528, /* PAL_CPPI41_SR_Q_1528 */ PAL_CPPI41_SR_Q_1529, /* PAL_CPPI41_SR_Q_1529 */ PAL_CPPI41_SR_FD_PP_Q_LAST = PAL_CPPI41_SR_Q_1529, /* Host Type Free Descriptors Queues */ PAL_CPPI41_SR_FD_HOST_Q_BASE, PAL_CPPI41_SR_CNI_INFRA_LOW_FD_HOST_Q_NUM = PAL_CPPI41_SR_FD_HOST_Q_BASE, /* PAL_CPPI41_SR_Q_1530 */ PAL_CPPI41_SR_CNI_INFRA_HIGH_FD_HOST_Q_NUM, /* PAL_CPPI41_SR_Q_1531 */ PAL_CPPI41_SR_DOCSIS_MGMT_RX_FD_HOST_Q_NUM, /* PAL_CPPI41_SR_Q_1532 */ PAL_CPPI41_SR_DOCSIS_MGMT_TX_FD_HOST_Q_NUM, /* PAL_CPPI41_SR_Q_1533 */ PAL_CPPI41_SR_HOST_TO_PP_LOW_FD_HOST_Q_NUM, /* PAL_CPPI41_SR_Q_1534 */ PAL_CPPI41_SR_HOST_TO_PP_HIGH_FD_HOST_Q_NUM, /* PAL_CPPI41_SR_Q_1535 */ PAL_CPPI41_SR_L2SW_INFRA_FD_HOST_Q_NUM, /* PAL_CPPI41_SR_Q_1536 */ PAL_CPPI41_SR_RECYCLE_FD_HOST_Q_NUM, /* PAL_CPPI41_SR_Q_1537 */ PAL_CPPI41_SR_COE_MONOLITHIC_FD_Q_NUM, /* PAL_CPPI41_SR_Q_1538 */ PAL_CPPI41_SR_COE_FORWARDING_FD_HOST_Q_NUM, /* PAL_CPPI41_SR_Q_1539 */ PAL_CPPI41_SR_COE_STREAMING_FD_HOST_Q_NUM, /* PAL_CPPI41_SR_Q_1540 */ PAL_CPPI41_SR_Q_1541, PAL_CPPI41_SR_Q_1542, PAL_CPPI41_SR_Q_1543, PAL_CPPI41_SR_Q_1544, PAL_CPPI41_SR_Q_1545, PAL_CPPI41_SR_Q_1546, PAL_CPPI41_SR_Q_1547, PAL_CPPI41_SR_Q_1548, PAL_CPPI41_SR_Q_1549, PAL_CPPI41_SR_Q_1550, PAL_CPPI41_SR_Q_1551, PAL_CPPI41_SR_Q_1552, PAL_CPPI41_SR_Q_1553, PAL_CPPI41_SR_FD_HOST_Q_LAST = PAL_CPPI41_SR_Q_1553, /* Embedded Type Free Descriptors Queues */ PAL_CPPI41_SR_FD_EMB_Q_BASE, PAL_CPPI41_SR_DOCSIS_RX_CoP_LOW_FD_EMB_Q_NUM = PAL_CPPI41_SR_FD_EMB_Q_BASE, /* PAL_CPPI41_SR_Q_1554 */ PAL_CPPI41_SR_DOCSIS_RX_CoP_HIGH_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1555 */ PAL_CPPI41_SR_DOCSIS_RX_VOICE_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1556 */ PAL_CPPI41_SR_HOST_TO_PP_INFRA_LOW_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1557 */ PAL_CPPI41_SR_HOST_TO_PP_INFRA_HIGH_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1558 */ PAL_CPPI41_SR_MPEG_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1559 */ PAL_CPPI41_SR_MPEG_ENCAP_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1560 */ PAL_CPPI41_SR_VOICE_DSP_C55_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1561 */ PAL_CPPI41_SR_VOICE_INFRA_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1562 */ PAL_CPPI41_SR_PROXY_PDSP_LOW_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1563 */ PAL_CPPI41_SR_PROXY_PDSP_HIGH_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1564 */ PAL_CPPI41_SR_Q_1565, /* PAL_CPPI41_SR_Q_1565 */ PAL_CPPI41_SR_Q_1566, /* PAL_CPPI41_SR_Q_1566 */ PAL_CPPI41_SR_DMA_FD_TEARDOWN_Q_NUM, /* PAL_CPPI41_SR_Q_1567 */ PAL_CPPI41_SR_USPREF_PDSP_MGMT_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1568 */ PAL_CPPI41_SR_USPREF_PDSP_VOICE_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1569 */ PAL_CPPI41_SR_USPREF_PDSP_BE_FD_EMB_Q_NUM, /* PAL_CPPI41_SR_Q_1570 */ PAL_CPPI41_SR_Q_1571, PAL_CPPI41_SR_Q_1572, PAL_CPPI41_SR_Q_1573, PAL_CPPI41_SR_Q_1574, PAL_CPPI41_SR_Q_1575, PAL_CPPI41_SR_Q_1576, PAL_CPPI41_SR_Q_1577, PAL_CPPI41_SR_FD_EMB_Q_LAST = PAL_CPPI41_SR_Q_1577, PAL_CPPI41_SR_DOCSIS_TX_MONOLITHIC_Q_NUM, /* PAL_CPPI41_SR_Q_1578 */ /* DOCSIS TX PreProcessing Queues */ PAL_CPPI41_SR_DOCSIS_TX_Q_BASE, PAL_CPPI41_SR_DOCSIS_TX_MGMT_Q_NUM = PAL_CPPI41_SR_DOCSIS_TX_Q_BASE, /* PAL_CPPI41_SR_Q_1579 */ PAL_CPPI41_SR_DOCSIS_TX_VOICE_Q_NUM, /* PAL_CPPI41_SR_Q_1580 */ PAL_CPPI41_SR_DOCSIS_TX_BE0_Q_NUM, // 1581 PAL_CPPI41_SR_DOCSIS_TX_BE1_Q_NUM, // 1582 PAL_CPPI41_SR_DOCSIS_TX_BE2_Q_NUM, // 1583 PAL_CPPI41_SR_DOCSIS_TX_BE3_Q_NUM, // 1584 PAL_CPPI41_SR_DOCSIS_TX_BE4_Q_NUM, // 1585 PAL_CPPI41_SR_DOCSIS_TX_BE5_Q_NUM, // 1586 PAL_CPPI41_SR_DOCSIS_TX_BE6_Q_NUM, // 1587 PAL_CPPI41_SR_DOCSIS_TX_BE7_Q_NUM, // 1588 PAL_CPPI41_SR_DOCSIS_TX_BE8_Q_NUM, // 1589 PAL_CPPI41_SR_DOCSIS_TX_BE9_Q_NUM, // 1590 PAL_CPPI41_SR_DOCSIS_TX_BE10_Q_NUM, // 1591 PAL_CPPI41_SR_DOCSIS_TX_BE11_Q_NUM, // 1592 PAL_CPPI41_SR_DOCSIS_TX_BE12_Q_NUM, // 1593 PAL_CPPI41_SR_DOCSIS_TX_BE13_Q_NUM, // 1594 PAL_CPPI41_SR_DOCSIS_TX_BE14_Q_NUM, // 1595 PAL_CPPI41_SR_DOCSIS_TX_BE15_Q_NUM, // 1596 PAL_CPPI41_SR_DOCSIS_TX_Q_LAST = PAL_CPPI41_SR_DOCSIS_TX_BE15_Q_NUM, PAL_CPPI41_SR_Q_1597, PAL_CPPI41_SR_Q_1598, PAL_CPPI41_SR_Q_1599, PAL_CPPI41_SR_Q_1600, PAL_CPPI41_SR_Q_1601, PAL_CPPI41_SR_Q_1602, PAL_CPPI41_SR_DOCSIS_TX_CoP_Q_NUM, PAL_CPPI41_SR_MPEG_OUT_PROGRAM0_Q_NUM, /* PAL_CPPI41_SR_Q_1604 */ PAL_CPPI41_SR_MPEG_OUT_PROGRAM1_Q_NUM, /* PAL_CPPI41_SR_Q_1605 */ /* DMA2 Infrastructure Input Queues */ PAL_CPPI41_SR_DMA2_INFRA_INPUT_Q_BASE, PAL_CPPI41_SR_DMA2_CNI_INFRA_LOW_INPUT_HIGH_Q_NUM = PAL_CPPI41_SR_DMA2_INFRA_INPUT_Q_BASE, /* PAL_CPPI41_SR_Q_1606 */ PAL_CPPI41_SR_DMA2_CNI_INFRA_LOW_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1607 */ PAL_CPPI41_SR_DMA2_CNI_INFRA_HIGH_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1608 */ PAL_CPPI41_SR_DMA2_CNI_INFRA_HIGH_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1609 */ PAL_CPPI41_SR_DMA2_L2SW_DATA0_INFRA_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1610 */ PAL_CPPI41_SR_DMA2_L2SW_DATA0_INFRA_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1611 */ PAL_CPPI41_SR_DMA2_L2SW_MGMT0_INFRA_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1612 */ PAL_CPPI41_SR_DMA2_L2SW_MGMT0_INFRA_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1613 */ PAL_CPPI41_SR_DMA2_C55_INFRA_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1614 */ PAL_CPPI41_SR_DMA2_C55_INFRA_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1615 */ PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA5_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1616 */ PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA5_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1617 */ PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA6_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1618 */ PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA6_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1619 */ PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA7_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1620 */ PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA7_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1621 */ PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA8_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1622 */ PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA8_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1623 */ PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA9_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1624 */ PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA9_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1625 */ PAL_CPPI41_SR_DMA2_INFRA_INPUT_Q_LAST = PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA9_INPUT_LOW_Q_NUM, /* DMA3 Infrastructure Input Queues */ PAL_CPPI41_SR_DMA3_INFRA_INPUT_Q_BASE, PAL_CPPI41_SR_DMA3_HOST_TO_PP_LOW_INFRA_INPUT_HIGH_Q_NUM = PAL_CPPI41_SR_DMA3_INFRA_INPUT_Q_BASE, /* PAL_CPPI41_SR_Q_1626 */ PAL_CPPI41_SR_DMA3_HOST_TO_PP_LOW_INFRA_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1627 */ PAL_CPPI41_SR_DMA3_HOST_TO_PP_HIGH_INFRA_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1628 */ PAL_CPPI41_SR_DMA3_HOST_TO_PP_HIGH_INFRA_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1629 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA2_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1630 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA2_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1631 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA3_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1632 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA3_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1633 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA4_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1634 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA4_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1635 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA5_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1636 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA5_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1637 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA6_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1638 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA6_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1639 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA7_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1640 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA7_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1641 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA8_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1642 */ PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA8_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1643 */ PAL_CPPI41_SR_DMA3_RECYCLE_INFRA_INPUT_HIGH_Q_NUM, /* PAL_CPPI41_SR_Q_1644 */ PAL_CPPI41_SR_DMA3_RECYCLE_INFRA_INPUT_LOW_Q_NUM, /* PAL_CPPI41_SR_Q_1645 */ PAL_CPPI41_SR_DMA3_INFRA_INPUT_Q_LAST = PAL_CPPI41_SR_DMA3_RECYCLE_INFRA_INPUT_LOW_Q_NUM, PAL_CPPI41_SR_QMGR_TOTAL_Q_COUNT /* 1646 */ }PAL_CPPI41_SR_QMGR_QUEUES_e; #define PAL_CPPI41_SR_QMGR_QUEUES_STR(v) \ char * v[ PAL_CPPI41_SR_QMGR_TOTAL_Q_COUNT ] = \ {\ /* DS Resequencing Queues */\ "PAL_CPPI41_SR_DS_RESEQ_Q_0",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1",\ "PAL_CPPI41_SR_DS_RESEQ_Q_2",\ "PAL_CPPI41_SR_DS_RESEQ_Q_3",\ "PAL_CPPI41_SR_DS_RESEQ_Q_4",\ "PAL_CPPI41_SR_DS_RESEQ_Q_5",\ "PAL_CPPI41_SR_DS_RESEQ_Q_6",\ "PAL_CPPI41_SR_DS_RESEQ_Q_7",\ "PAL_CPPI41_SR_DS_RESEQ_Q_8",\ "PAL_CPPI41_SR_DS_RESEQ_Q_9",\ "PAL_CPPI41_SR_DS_RESEQ_Q_10",\ "PAL_CPPI41_SR_DS_RESEQ_Q_11",\ "PAL_CPPI41_SR_DS_RESEQ_Q_12",\ "PAL_CPPI41_SR_DS_RESEQ_Q_13",\ "PAL_CPPI41_SR_DS_RESEQ_Q_14",\ "PAL_CPPI41_SR_DS_RESEQ_Q_15",\ "PAL_CPPI41_SR_DS_RESEQ_Q_16",\ "PAL_CPPI41_SR_DS_RESEQ_Q_17",\ "PAL_CPPI41_SR_DS_RESEQ_Q_18",\ "PAL_CPPI41_SR_DS_RESEQ_Q_19",\ "PAL_CPPI41_SR_DS_RESEQ_Q_20",\ "PAL_CPPI41_SR_DS_RESEQ_Q_21",\ "PAL_CPPI41_SR_DS_RESEQ_Q_22",\ "PAL_CPPI41_SR_DS_RESEQ_Q_23",\ "PAL_CPPI41_SR_DS_RESEQ_Q_24",\ "PAL_CPPI41_SR_DS_RESEQ_Q_25",\ "PAL_CPPI41_SR_DS_RESEQ_Q_26",\ "PAL_CPPI41_SR_DS_RESEQ_Q_27",\ "PAL_CPPI41_SR_DS_RESEQ_Q_28",\ "PAL_CPPI41_SR_DS_RESEQ_Q_29",\ "PAL_CPPI41_SR_DS_RESEQ_Q_30",\ "PAL_CPPI41_SR_DS_RESEQ_Q_31",\ "PAL_CPPI41_SR_DS_RESEQ_Q_32",\ "PAL_CPPI41_SR_DS_RESEQ_Q_33",\ "PAL_CPPI41_SR_DS_RESEQ_Q_34",\ "PAL_CPPI41_SR_DS_RESEQ_Q_35",\ "PAL_CPPI41_SR_DS_RESEQ_Q_36",\ "PAL_CPPI41_SR_DS_RESEQ_Q_37",\ "PAL_CPPI41_SR_DS_RESEQ_Q_38",\ "PAL_CPPI41_SR_DS_RESEQ_Q_39",\ "PAL_CPPI41_SR_DS_RESEQ_Q_40",\ "PAL_CPPI41_SR_DS_RESEQ_Q_41",\ "PAL_CPPI41_SR_DS_RESEQ_Q_42",\ "PAL_CPPI41_SR_DS_RESEQ_Q_43",\ "PAL_CPPI41_SR_DS_RESEQ_Q_44",\ "PAL_CPPI41_SR_DS_RESEQ_Q_45",\ "PAL_CPPI41_SR_DS_RESEQ_Q_46",\ "PAL_CPPI41_SR_DS_RESEQ_Q_47",\ "PAL_CPPI41_SR_DS_RESEQ_Q_48",\ "PAL_CPPI41_SR_DS_RESEQ_Q_49",\ "PAL_CPPI41_SR_DS_RESEQ_Q_50",\ "PAL_CPPI41_SR_DS_RESEQ_Q_51",\ "PAL_CPPI41_SR_DS_RESEQ_Q_52",\ "PAL_CPPI41_SR_DS_RESEQ_Q_53",\ "PAL_CPPI41_SR_DS_RESEQ_Q_54",\ "PAL_CPPI41_SR_DS_RESEQ_Q_55",\ "PAL_CPPI41_SR_DS_RESEQ_Q_56",\ "PAL_CPPI41_SR_DS_RESEQ_Q_57",\ "PAL_CPPI41_SR_DS_RESEQ_Q_58",\ "PAL_CPPI41_SR_DS_RESEQ_Q_59",\ "PAL_CPPI41_SR_DS_RESEQ_Q_60",\ "PAL_CPPI41_SR_DS_RESEQ_Q_61",\ "PAL_CPPI41_SR_DS_RESEQ_Q_62",\ "PAL_CPPI41_SR_DS_RESEQ_Q_63",\ "PAL_CPPI41_SR_DS_RESEQ_Q_64",\ "PAL_CPPI41_SR_DS_RESEQ_Q_65",\ "PAL_CPPI41_SR_DS_RESEQ_Q_66",\ "PAL_CPPI41_SR_DS_RESEQ_Q_67",\ "PAL_CPPI41_SR_DS_RESEQ_Q_68",\ "PAL_CPPI41_SR_DS_RESEQ_Q_69",\ "PAL_CPPI41_SR_DS_RESEQ_Q_70",\ "PAL_CPPI41_SR_DS_RESEQ_Q_71",\ "PAL_CPPI41_SR_DS_RESEQ_Q_72",\ "PAL_CPPI41_SR_DS_RESEQ_Q_73",\ "PAL_CPPI41_SR_DS_RESEQ_Q_74",\ "PAL_CPPI41_SR_DS_RESEQ_Q_75",\ "PAL_CPPI41_SR_DS_RESEQ_Q_76",\ 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"PAL_CPPI41_SR_DS_RESEQ_Q_1124",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1125",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1126",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1127",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1128",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1129",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1130",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1131",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1132",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1133",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1134",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1135",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1136",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1137",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1138",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1139",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1140",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1141",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1142",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1143",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1144",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1145",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1146",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1147",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1148",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1149",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1150",\ "PAL_CPPI41_SR_DS_RESEQ_Q_1151",\ \ \ /* QoS PDSP QoS Queues */\ "PAL_CPPI41_SR_CLUSTER0_DOCSIS_TX_BE0_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1152 */\ "PAL_CPPI41_SR_CLUSTER0_DOCSIS_TX_BE0_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1153 */\ "PAL_CPPI41_SR_CLUSTER1_DOCSIS_TX_BE1_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1154 */\ "PAL_CPPI41_SR_CLUSTER1_DOCSIS_TX_BE1_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1155 */\ "PAL_CPPI41_SR_CLUSTER2_DOCSIS_TX_BE2_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1156 */\ "PAL_CPPI41_SR_CLUSTER2_DOCSIS_TX_BE2_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1157 */\ "PAL_CPPI41_SR_CLUSTER3_DOCSIS_TX_BE3_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1158 */\ "PAL_CPPI41_SR_CLUSTER3_DOCSIS_TX_BE3_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1159 */\ "PAL_CPPI41_SR_CLUSTER4_DOCSIS_TX_BE4_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1160 */\ "PAL_CPPI41_SR_CLUSTER4_DOCSIS_TX_BE4_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1161 */\ "PAL_CPPI41_SR_CLUSTER5_DOCSIS_TX_BE5_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1162 */\ "PAL_CPPI41_SR_CLUSTER5_DOCSIS_TX_BE5_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1163 */\ "PAL_CPPI41_SR_CLUSTER6_DOCSIS_TX_BE6_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1164 */\ "PAL_CPPI41_SR_CLUSTER6_DOCSIS_TX_BE6_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1165 */\ "PAL_CPPI41_SR_CLUSTER7_DOCSIS_TX_BE7_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1166 */\ "PAL_CPPI41_SR_CLUSTER7_DOCSIS_TX_BE7_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1167 */\ "PAL_CPPI41_SR_CLUSTER8_DOCSIS_TX_BE8_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1168 */\ "PAL_CPPI41_SR_CLUSTER8_DOCSIS_TX_BE8_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1169 */\ "PAL_CPPI41_SR_CLUSTER9_DOCSIS_TX_BE9_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1170 */\ "PAL_CPPI41_SR_CLUSTER9_DOCSIS_TX_BE9_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1171 */\ "PAL_CPPI41_SR_CLUSTER10_DOCSIS_TX_BE10_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1172 */\ "PAL_CPPI41_SR_CLUSTER10_DOCSIS_TX_BE10_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1173 */\ "PAL_CPPI41_SR_CLUSTER11_DOCSIS_TX_BE11_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1174 */\ "PAL_CPPI41_SR_CLUSTER11_DOCSIS_TX_BE11_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1175 */\ "PAL_CPPI41_SR_CLUSTER12_DOCSIS_TX_BE12_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1176 */\ "PAL_CPPI41_SR_CLUSTER12_DOCSIS_TX_BE12_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1177 */\ "PAL_CPPI41_SR_CLUSTER13_DOCSIS_TX_BE13_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1178 */\ "PAL_CPPI41_SR_CLUSTER13_DOCSIS_TX_BE13_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1179 */\ "PAL_CPPI41_SR_CLUSTER14_DOCSIS_TX_BE14_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1180 */\ "PAL_CPPI41_SR_CLUSTER14_DOCSIS_TX_BE14_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1181 */\ "PAL_CPPI41_SR_CLUSTER15_DOCSIS_TX_BE15_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1182 */\ "PAL_CPPI41_SR_CLUSTER15_DOCSIS_TX_BE15_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1183 */\ "PAL_CPPI41_SR_CLUSTER16_L2SW_DATA0_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1184 */\ "PAL_CPPI41_SR_CLUSTER16_L2SW_DATA0_MED_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1185 */\ "PAL_CPPI41_SR_CLUSTER16_L2SW_DATA0_MED_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1186 */\ "PAL_CPPI41_SR_CLUSTER16_L2SW_DATA0_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1187 */\ "PAL_CPPI41_SR_CLUSTER17_L2SW_MGMT0_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1188 */\ "PAL_CPPI41_SR_CLUSTER17_L2SW_MGMT0_MED_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1189 */\ "PAL_CPPI41_SR_CLUSTER17_L2SW_MGMT0_MED_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1190 */\ "PAL_CPPI41_SR_CLUSTER17_L2SW_MGMT0_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1191 */\ "PAL_CPPI41_SR_CLUSTER18_L2SW_MOCA0_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1192 */\ "PAL_CPPI41_SR_CLUSTER18_L2SW_MOCA0_MED_HIGH_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1193 */\ "PAL_CPPI41_SR_CLUSTER18_L2SW_MOCA0_MED_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1194 */\ "PAL_CPPI41_SR_CLUSTER18_L2SW_MOCA0_LOW_QPDSP_QOS_Q_NUM", /* PAL_CPPI41_SR_Q_1195 */\ \ "PAL_CPPI41_SR_QPDSP_QOS_Q_44", /* PAL_CPPI41_SR_Q_1196 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_45", /* PAL_CPPI41_SR_Q_1197 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_46", /* PAL_CPPI41_SR_Q_1198 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_47", /* PAL_CPPI41_SR_Q_1199 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_48", /* PAL_CPPI41_SR_Q_1200 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_49", /* PAL_CPPI41_SR_Q_1201 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_50", /* PAL_CPPI41_SR_Q_1202 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_51", /* PAL_CPPI41_SR_Q_1203 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_52", /* PAL_CPPI41_SR_Q_1204 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_53", /* PAL_CPPI41_SR_Q_1205 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_54", /* PAL_CPPI41_SR_Q_1206 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_55", /* PAL_CPPI41_SR_Q_1207 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_56", /* PAL_CPPI41_SR_Q_1208 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_57", /* PAL_CPPI41_SR_Q_1209 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_58", /* PAL_CPPI41_SR_Q_1210 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_59", /* PAL_CPPI41_SR_Q_1211 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_60", /* PAL_CPPI41_SR_Q_1212 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_61", /* PAL_CPPI41_SR_Q_1213 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_62", /* PAL_CPPI41_SR_Q_1214 */\ "PAL_CPPI41_SR_QPDSP_QOS_Q_63", /* PAL_CPPI41_SR_Q_1215 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_0", /* PAL_CPPI41_SR_Q_1216 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_1", /* PAL_CPPI41_SR_Q_1217 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_2", /* PAL_CPPI41_SR_Q_1218 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_3", /* PAL_CPPI41_SR_Q_1219 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_4", /* PAL_CPPI41_SR_Q_1220 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_5", /* PAL_CPPI41_SR_Q_1221 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_6", /* PAL_CPPI41_SR_Q_1222 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_7", /* PAL_CPPI41_SR_Q_1223 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_8", /* PAL_CPPI41_SR_Q_1224 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_9", /* PAL_CPPI41_SR_Q_1225 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_10", /* PAL_CPPI41_SR_Q_1226 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_11", /* PAL_CPPI41_SR_Q_1227 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_12", /* PAL_CPPI41_SR_Q_1228 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_13", /* PAL_CPPI41_SR_Q_1229 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_14", /* PAL_CPPI41_SR_Q_1230 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_15", /* PAL_CPPI41_SR_Q_1231 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_16", /* PAL_CPPI41_SR_Q_1232 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_17", /* PAL_CPPI41_SR_Q_1233 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_18", /* PAL_CPPI41_SR_Q_1234 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_19", /* PAL_CPPI41_SR_Q_1235 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_20", /* PAL_CPPI41_SR_Q_1236 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_21", /* PAL_CPPI41_SR_Q_1237 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_22", /* PAL_CPPI41_SR_Q_1238 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_23", /* PAL_CPPI41_SR_Q_1239 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_24", /* PAL_CPPI41_SR_Q_1240 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_25", /* PAL_CPPI41_SR_Q_1241 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_26", /* PAL_CPPI41_SR_Q_1242 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_27", /* PAL_CPPI41_SR_Q_1243 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_28", /* PAL_CPPI41_SR_Q_1244 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_29", /* PAL_CPPI41_SR_Q_1245 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_30", /* PAL_CPPI41_SR_Q_1246 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_31", /* PAL_CPPI41_SR_Q_1247 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_32", /* PAL_CPPI41_SR_Q_1248 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_33", /* PAL_CPPI41_SR_Q_1249 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_34", /* PAL_CPPI41_SR_Q_1250 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_35", /* PAL_CPPI41_SR_Q_1251 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_36", /* PAL_CPPI41_SR_Q_1252 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_37", /* PAL_CPPI41_SR_Q_1253 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_38", /* PAL_CPPI41_SR_Q_1254 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_39", /* PAL_CPPI41_SR_Q_1255 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_40", /* PAL_CPPI41_SR_Q_1256 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_41", /* PAL_CPPI41_SR_Q_1257 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_42", /* PAL_CPPI41_SR_Q_1258 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_43", /* PAL_CPPI41_SR_Q_1259 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_44", /* PAL_CPPI41_SR_Q_1260 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_45", /* PAL_CPPI41_SR_Q_1261 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_46", /* PAL_CPPI41_SR_Q_1262 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_47", /* PAL_CPPI41_SR_Q_1263 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_48", /* PAL_CPPI41_SR_Q_1264 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_49", /* PAL_CPPI41_SR_Q_1265 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_50", /* PAL_CPPI41_SR_Q_1266 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_51", /* PAL_CPPI41_SR_Q_1267 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_52", /* PAL_CPPI41_SR_Q_1268 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_53", /* PAL_CPPI41_SR_Q_1269 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_54", /* PAL_CPPI41_SR_Q_1270 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_55", /* PAL_CPPI41_SR_Q_1271 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_56", /* PAL_CPPI41_SR_Q_1272 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_57", /* PAL_CPPI41_SR_Q_1273 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_58", /* PAL_CPPI41_SR_Q_1274 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_59", /* PAL_CPPI41_SR_Q_1275 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_60", /* PAL_CPPI41_SR_Q_1276 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_61", /* PAL_CPPI41_SR_Q_1277 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_62", /* PAL_CPPI41_SR_Q_1278 */\ "PAL_CPPI41_SR_PP_SYNCH_Q_63", /* PAL_CPPI41_SR_Q_1279 */\ \ /* Multicast Cache Queues */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_0", /* PAL_CPPI41_SR_Q_1280 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_1", /* PAL_CPPI41_SR_Q_1281 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_2", /* PAL_CPPI41_SR_Q_1282 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_3", /* PAL_CPPI41_SR_Q_1283 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_4", /* PAL_CPPI41_SR_Q_1284 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_5", /* PAL_CPPI41_SR_Q_1285 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_6", /* PAL_CPPI41_SR_Q_1286 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_7", /* PAL_CPPI41_SR_Q_1287 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_8", /* PAL_CPPI41_SR_Q_1288 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_9", /* PAL_CPPI41_SR_Q_1289 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_10", /* PAL_CPPI41_SR_Q_1290 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_11", /* PAL_CPPI41_SR_Q_1291 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_12", /* PAL_CPPI41_SR_Q_1292 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_13", /* PAL_CPPI41_SR_Q_1293 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_14", /* PAL_CPPI41_SR_Q_1294 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_15", /* PAL_CPPI41_SR_Q_1295 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_16", /* PAL_CPPI41_SR_Q_1296 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_17", /* PAL_CPPI41_SR_Q_1297 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_18", /* PAL_CPPI41_SR_Q_1298 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_19", /* PAL_CPPI41_SR_Q_1299 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_20", /* PAL_CPPI41_SR_Q_1300 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_21", /* PAL_CPPI41_SR_Q_1301 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_22", /* PAL_CPPI41_SR_Q_1302 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_23", /* PAL_CPPI41_SR_Q_1303 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_24", /* PAL_CPPI41_SR_Q_1304 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_25", /* PAL_CPPI41_SR_Q_1305 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_26", /* PAL_CPPI41_SR_Q_1306 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_27", /* PAL_CPPI41_SR_Q_1307 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_28", /* PAL_CPPI41_SR_Q_1308 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_29", /* PAL_CPPI41_SR_Q_1309 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_30", /* PAL_CPPI41_SR_Q_1310 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_31", /* PAL_CPPI41_SR_Q_1311 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_32", /* PAL_CPPI41_SR_Q_1312 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_33", /* PAL_CPPI41_SR_Q_1313 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_34", /* PAL_CPPI41_SR_Q_1314 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_35", /* PAL_CPPI41_SR_Q_1315 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_36", /* PAL_CPPI41_SR_Q_1316 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_37", /* PAL_CPPI41_SR_Q_1317 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_38", /* PAL_CPPI41_SR_Q_1318 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_39", /* PAL_CPPI41_SR_Q_1319 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_40", /* PAL_CPPI41_SR_Q_1320 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_41", /* PAL_CPPI41_SR_Q_1321 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_42", /* PAL_CPPI41_SR_Q_1322 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_43", /* PAL_CPPI41_SR_Q_1323 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_44", /* PAL_CPPI41_SR_Q_1324 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_45", /* PAL_CPPI41_SR_Q_1325 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_46", /* PAL_CPPI41_SR_Q_1326 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_47", /* PAL_CPPI41_SR_Q_1327 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_48", /* PAL_CPPI41_SR_Q_1328 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_49", /* PAL_CPPI41_SR_Q_1329 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_50", /* PAL_CPPI41_SR_Q_1330 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_51", /* PAL_CPPI41_SR_Q_1331 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_52", /* PAL_CPPI41_SR_Q_1332 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_53", /* PAL_CPPI41_SR_Q_1333 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_54", /* PAL_CPPI41_SR_Q_1334 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_55", /* PAL_CPPI41_SR_Q_1335 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_56", /* PAL_CPPI41_SR_Q_1336 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_57", /* PAL_CPPI41_SR_Q_1337 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_58", /* PAL_CPPI41_SR_Q_1338 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_59", /* PAL_CPPI41_SR_Q_1339 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_60", /* PAL_CPPI41_SR_Q_1340 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_61", /* PAL_CPPI41_SR_Q_1341 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_62", /* PAL_CPPI41_SR_Q_1342 */\ "PAL_CPPI41_SR_MULTICAST_CACHE_Q_63", /* PAL_CPPI41_SR_Q_1343 */\ \ /* Unused Queues */\ "PAL_CPPI41_SR_Q_1344", /* PAL_CPPI41_SR_Q_1344 */\ "PAL_CPPI41_SR_Q_1345", /* PAL_CPPI41_SR_Q_1345 */\ "PAL_CPPI41_SR_Q_1346", /* PAL_CPPI41_SR_Q_1346 */\ "PAL_CPPI41_SR_Q_1347", /* PAL_CPPI41_SR_Q_1347 */\ "PAL_CPPI41_SR_Q_1348", /* PAL_CPPI41_SR_Q_1348 */\ "PAL_CPPI41_SR_Q_1349", /* PAL_CPPI41_SR_Q_1349 */\ "PAL_CPPI41_SR_Q_1350", /* PAL_CPPI41_SR_Q_1350 */\ "PAL_CPPI41_SR_Q_1351", /* PAL_CPPI41_SR_Q_1351 */\ "PAL_CPPI41_SR_Q_1352", /* PAL_CPPI41_SR_Q_1352 */\ "PAL_CPPI41_SR_Q_1353", /* PAL_CPPI41_SR_Q_1353 */\ "PAL_CPPI41_SR_Q_1354", /* PAL_CPPI41_SR_Q_1354 */\ "PAL_CPPI41_SR_Q_1355", /* PAL_CPPI41_SR_Q_1355 */\ "PAL_CPPI41_SR_Q_1356", /* PAL_CPPI41_SR_Q_1356 */\ "PAL_CPPI41_SR_Q_1357", /* PAL_CPPI41_SR_Q_1357 */\ "PAL_CPPI41_SR_Q_1358", /* PAL_CPPI41_SR_Q_1358 */\ "PAL_CPPI41_SR_Q_1359", /* PAL_CPPI41_SR_Q_1359 */\ "PAL_CPPI41_SR_Q_1360", /* PAL_CPPI41_SR_Q_1360 */\ "PAL_CPPI41_SR_Q_1361", /* PAL_CPPI41_SR_Q_1361 */\ "PAL_CPPI41_SR_Q_1362", /* PAL_CPPI41_SR_Q_1362 */\ "PAL_CPPI41_SR_Q_1363", /* PAL_CPPI41_SR_Q_1363 */\ "PAL_CPPI41_SR_Q_1364", /* PAL_CPPI41_SR_Q_1364 */\ "PAL_CPPI41_SR_Q_1365", /* PAL_CPPI41_SR_Q_1365 */\ "PAL_CPPI41_SR_Q_1366", /* PAL_CPPI41_SR_Q_1366 */\ "PAL_CPPI41_SR_Q_1367", /* PAL_CPPI41_SR_Q_1367 */\ "PAL_CPPI41_SR_Q_1368", /* PAL_CPPI41_SR_Q_1368 */\ "PAL_CPPI41_SR_Q_1369", /* PAL_CPPI41_SR_Q_1369 */\ "PAL_CPPI41_SR_Q_1370", /* PAL_CPPI41_SR_Q_1370 */\ "PAL_CPPI41_SR_Q_1371", /* PAL_CPPI41_SR_Q_1371 */\ "PAL_CPPI41_SR_Q_1372", /* PAL_CPPI41_SR_Q_1372 */\ "PAL_CPPI41_SR_Q_1373", /* PAL_CPPI41_SR_Q_1373 */\ "PAL_CPPI41_SR_Q_1374", /* PAL_CPPI41_SR_Q_1374 */\ "PAL_CPPI41_SR_Q_1375", /* PAL_CPPI41_SR_Q_1375 */\ \ /* Proxy PDSP Input Queues */\ "PAL_CPPI41_SR_L2SW_DATA0_PrxPDSP_Q_NUM", /* PAL_CPPI41_SR_Q_1376 */\ "PAL_CPPI41_SR_L2SW_MGMT0_PrxPDSP_Q_NUM", /* PAL_CPPI41_SR_Q_1377 */\ "PAL_CPPI41_SR_PrxPDSP_Q_2", /* PAL_CPPI41_SR_Q_1378 */\ "PAL_CPPI41_SR_PrxPDSP_Q_3", /* PAL_CPPI41_SR_Q_1379 */\ "PAL_CPPI41_SR_PrxPDSP_Q_4", /* PAL_CPPI41_SR_Q_1380 */\ "PAL_CPPI41_SR_PrxPDSP_Q_5", /* PAL_CPPI41_SR_Q_1381 */\ "PAL_CPPI41_SR_PrxPDSP_Q_6", /* PAL_CPPI41_SR_Q_1382 */\ "PAL_CPPI41_SR_PrxPDSP_Q_7", /* PAL_CPPI41_SR_Q_1383 */\ "PAL_CPPI41_SR_PrxPDSP_Q_8", /* PAL_CPPI41_SR_Q_1384 */\ "PAL_CPPI41_SR_PrxPDSP_Q_9", /* PAL_CPPI41_SR_Q_1385 */\ "PAL_CPPI41_SR_PrxPDSP_Q_10", /* PAL_CPPI41_SR_Q_1386 */\ "PAL_CPPI41_SR_PrxPDSP_Q_11", /* PAL_CPPI41_SR_Q_1387 */\ "PAL_CPPI41_SR_PrxPDSP_Q_12", /* PAL_CPPI41_SR_Q_1388 */\ "PAL_CPPI41_SR_PrxPDSP_Q_13", /* PAL_CPPI41_SR_Q_1389 */\ "PAL_CPPI41_SR_PrxPDSP_Q_14", /* PAL_CPPI41_SR_Q_1390 */\ "PAL_CPPI41_SR_PrxPDSP_Q_15", /* PAL_CPPI41_SR_Q_1391 */\ "PAL_CPPI41_SR_PrxPDSP_Q_16", /* PAL_CPPI41_SR_Q_1392 */\ "PAL_CPPI41_SR_PrxPDSP_Q_17", /* PAL_CPPI41_SR_Q_1393 */\ "PAL_CPPI41_SR_PrxPDSP_Q_18", /* PAL_CPPI41_SR_Q_1394 */\ "PAL_CPPI41_SR_PrxPDSP_Q_19", /* PAL_CPPI41_SR_Q_1395 */\ "PAL_CPPI41_SR_PrxPDSP_Q_20", /* PAL_CPPI41_SR_Q_1396 */\ "PAL_CPPI41_SR_PrxPDSP_Q_21", /* PAL_CPPI41_SR_Q_1397 */\ "PAL_CPPI41_SR_PrxPDSP_Q_22", /* PAL_CPPI41_SR_Q_1398 */\ "PAL_CPPI41_SR_PrxPDSP_Q_23", /* PAL_CPPI41_SR_Q_1399 */\ "PAL_CPPI41_SR_PrxPDSP_Q_24", /* PAL_CPPI41_SR_Q_1400 */\ "PAL_CPPI41_SR_PrxPDSP_Q_25", /* PAL_CPPI41_SR_Q_1401 */\ "PAL_CPPI41_SR_PrxPDSP_Q_26", /* PAL_CPPI41_SR_Q_1402 */\ "PAL_CPPI41_SR_PrxPDSP_Q_27", /* PAL_CPPI41_SR_Q_1403 */\ "PAL_CPPI41_SR_PrxPDSP_Q_28", /* PAL_CPPI41_SR_Q_1404 */\ "PAL_CPPI41_SR_PrxPDSP_Q_29", /* PAL_CPPI41_SR_Q_1405 */\ "PAL_CPPI41_SR_PrxPDSP_Q_30", /* PAL_CPPI41_SR_Q_1406 */\ "PAL_CPPI41_SR_PrxPDSP_Q_31", /* PAL_CPPI41_SR_Q_1407 */\ \ /* Cache Offloader PDSP Input Queues */\ "PAL_CPPI41_SR_CoePDSP_Q_0", /* PAL_CPPI41_SR_Q_1408 */\ "PAL_CPPI41_SR_CoePDSP_Q_1", /* PAL_CPPI41_SR_Q_1409 */\ "PAL_CPPI41_SR_CoePDSP_Q_2", /* PAL_CPPI41_SR_Q_1410 */\ "PAL_CPPI41_SR_CoePDSP_Q_3", /* PAL_CPPI41_SR_Q_1411 */\ "PAL_CPPI41_SR_CoePDSP_Q_4", /* PAL_CPPI41_SR_Q_1412 */\ "PAL_CPPI41_SR_CoePDSP_Q_5", /* PAL_CPPI41_SR_Q_1413 */\ "PAL_CPPI41_SR_CoePDSP_Q_6", /* PAL_CPPI41_SR_Q_1414 */\ "PAL_CPPI41_SR_CoePDSP_Q_7", /* PAL_CPPI41_SR_Q_1415 */\ "PAL_CPPI41_SR_CoePDSP_Q_8", /* PAL_CPPI41_SR_Q_1416 */\ "PAL_CPPI41_SR_CoePDSP_Q_9", /* PAL_CPPI41_SR_Q_1417 */\ "PAL_CPPI41_SR_CoePDSP_Q_10", /* PAL_CPPI41_SR_Q_1418 */\ "PAL_CPPI41_SR_CoePDSP_Q_11", /* PAL_CPPI41_SR_Q_1419 */\ "PAL_CPPI41_SR_CoePDSP_Q_12", /* PAL_CPPI41_SR_Q_1420 */\ "PAL_CPPI41_SR_CoePDSP_Q_13", /* PAL_CPPI41_SR_Q_1421 */\ "PAL_CPPI41_SR_CoePDSP_Q_14", /* PAL_CPPI41_SR_Q_1422 */\ "PAL_CPPI41_SR_CoePDSP_Q_15", /* PAL_CPPI41_SR_Q_1423 */\ \ /* Queues 1425 - 1439 are unassigned */\ "PAL_CPPI41_SR_COE_FORWARDING_APPLICATION_Q_NUM",/* PAL_CPPI41_SR_Q_1425 */\ "PAL_CPPI41_SR_Q_1425",\ "PAL_CPPI41_SR_Q_1426",\ "PAL_CPPI41_SR_Q_1427",\ "PAL_CPPI41_SR_Q_1428",\ "PAL_CPPI41_SR_Q_1429",\ "PAL_CPPI41_SR_Q_1430",\ "PAL_CPPI41_SR_Q_1431",\ "PAL_CPPI41_SR_Q_1432",\ "PAL_CPPI41_SR_Q_1433",\ "PAL_CPPI41_SR_Q_1434",\ "PAL_CPPI41_SR_Q_1435",\ "PAL_CPPI41_SR_Q_1436",\ "PAL_CPPI41_SR_Q_1437",\ "PAL_CPPI41_SR_Q_1438",\ "PAL_CPPI41_SR_VOICE_DSP_C55_INPUT_Q_NUM",\ \ /* Classifier1 PDSP Input Queues */\ "PAL_CPPI41_SR_C1PDSP_Q_0", /* PAL_CPPI41_SR_Q_1440 */\ "PAL_CPPI41_SR_C1PDSP_Q_1", /* PAL_CPPI41_SR_Q_1441 */\ "PAL_CPPI41_SR_C1PDSP_Q_2", /* PAL_CPPI41_SR_Q_1442 */\ "PAL_CPPI41_SR_C1PDSP_Q_3", /* PAL_CPPI41_SR_Q_1443 */\ "PAL_CPPI41_SR_C1PDSP_Q_4", /* PAL_CPPI41_SR_Q_1444 */\ "PAL_CPPI41_SR_C1PDSP_Q_5", /* PAL_CPPI41_SR_Q_1445 */\ "PAL_CPPI41_SR_C1PDSP_Q_6", /* PAL_CPPI41_SR_Q_1446 */\ "PAL_CPPI41_SR_C1PDSP_Q_7", /* PAL_CPPI41_SR_Q_1447 */\ \ /* Classifier2 PDSP Input Queues */\ "PAL_CPPI41_SR_C2PDSP_Q_0", /* PAL_CPPI41_SR_Q_1448 */\ "PAL_CPPI41_SR_C2PDSP_Q_1", /* PAL_CPPI41_SR_Q_1449 */\ "PAL_CPPI41_SR_C2PDSP_Q_2", /* PAL_CPPI41_SR_Q_1450 */\ "PAL_CPPI41_SR_C2PDSP_Q_3", /* PAL_CPPI41_SR_Q_1451 */\ "PAL_CPPI41_SR_C2PDSP_Q_4", /* PAL_CPPI41_SR_Q_1452 */\ "PAL_CPPI41_SR_C2PDSP_Q_5", /* PAL_CPPI41_SR_Q_1453 */\ "PAL_CPPI41_SR_C2PDSP_Q_6", /* PAL_CPPI41_SR_Q_1454 */\ "PAL_CPPI41_SR_C2PDSP_Q_7", /* PAL_CPPI41_SR_Q_1455 */\ \ /* Modifier PDSP Input Queues */\ "PAL_CPPI41_SR_MPDSP_Q_0", /* PAL_CPPI41_SR_Q_1456 */\ "PAL_CPPI41_SR_MPDSP_Q_1", /* PAL_CPPI41_SR_Q_1457 */\ "PAL_CPPI41_SR_MPDSP_Q_2", /* PAL_CPPI41_SR_Q_1458 */\ "PAL_CPPI41_SR_MPDSP_Q_3", /* PAL_CPPI41_SR_Q_1459 */\ "PAL_CPPI41_SR_MPDSP_Q_4", /* PAL_CPPI41_SR_Q_1460 */\ "PAL_CPPI41_SR_MPDSP_Q_5", /* PAL_CPPI41_SR_Q_1461 */\ "PAL_CPPI41_SR_MPDSP_Q_6", /* PAL_CPPI41_SR_Q_1462 */\ "PAL_CPPI41_SR_MPDSP_Q_7", /* PAL_CPPI41_SR_Q_1463 */\ \ /* Host to QoS PDSP Input Queues */\ "PAL_CPPI41_SR_HOST_TO_QPDSP_Q_0", /* PAL_CPPI41_SR_Q_1464 */\ "PAL_CPPI41_SR_HOST_TO_QPDSP_LOW_EMB_TYPE_Q_NUM", /* PAL_CPPI41_SR_Q_1465 */\ "PAL_CPPI41_SR_HOST_TO_QPDSP_Q_2", /* PAL_CPPI41_SR_Q_1466 */\ "PAL_CPPI41_SR_HOST_TO_QPDSP_HIGH_EMB_TYPE_Q_NUM", /* PAL_CPPI41_SR_Q_1467 */\ "PAL_CPPI41_SR_HOST_TO_QPDSP_Q_4", /* PAL_CPPI41_SR_Q_1468 */\ "PAL_CPPI41_SR_HOST_TO_QPDSP_Q_5", /* PAL_CPPI41_SR_Q_1469 */\ "PAL_CPPI41_SR_HOST_TO_QPDSP_Q_6", /* PAL_CPPI41_SR_Q_1470 */\ "PAL_CPPI41_SR_HOST_TO_QPDSP_Q_7", /* PAL_CPPI41_SR_Q_1471 */\ \ /* Prefetcher PDSP Input Queues */\ "PAL_CPPI41_SR_PPDSP_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1472 */\ "PAL_CPPI41_SR_PPDSP_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1473 */\ "PAL_CPPI41_SR_PPDSP_Q_2", /* PAL_CPPI41_SR_Q_1474 */\ "PAL_CPPI41_SR_PPDSP_Q_3", /* PAL_CPPI41_SR_Q_1475 */\ "PAL_CPPI41_SR_PPDSP_Q_4", /* PAL_CPPI41_SR_Q_1476 */\ "PAL_CPPI41_SR_PPDSP_Q_5", /* PAL_CPPI41_SR_Q_1477 */\ "PAL_CPPI41_SR_PPDSP_Q_6", /* PAL_CPPI41_SR_Q_1478 */\ "PAL_CPPI41_SR_PPDSP_Q_7", /* PAL_CPPI41_SR_Q_1479 */\ \ /* Us Prefetcher PDSP Input Queues */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_0", /* PAL_CPPI41_SR_Q_1480 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_1", /* PAL_CPPI41_SR_Q_1481 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_2", /* PAL_CPPI41_SR_Q_1482 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_3", /* PAL_CPPI41_SR_Q_1483 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_4", /* PAL_CPPI41_SR_Q_1484 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_5", /* PAL_CPPI41_SR_Q_1485 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_6", /* PAL_CPPI41_SR_Q_1486 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_7", /* PAL_CPPI41_SR_Q_1487 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_8", /* PAL_CPPI41_SR_Q_1488 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_9", /* PAL_CPPI41_SR_Q_1489 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_10", /* PAL_CPPI41_SR_Q_1490 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_11", /* PAL_CPPI41_SR_Q_1491 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_12", /* PAL_CPPI41_SR_Q_1492 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_13", /* PAL_CPPI41_SR_Q_1493 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_14", /* PAL_CPPI41_SR_Q_1494 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_15", /* PAL_CPPI41_SR_Q_1495 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_16", /* PAL_CPPI41_SR_Q_1496 */\ "PAL_CPPI41_SR_UsPrefPDSP_Q_17", /* PAL_CPPI41_SR_Q_1497 */\ \ /* Host TX Complete Queues */\ "PAL_CPPI41_SR_HOST_TX_COMPLETE_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1498 */\ "PAL_CPPI41_SR_HOST_TX_COMPLETE_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1499 */\ "PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_2", /* PAL_CPPI41_SR_Q_1500 */\ "PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_3", /* PAL_CPPI41_SR_Q_1501 */\ "PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_4", /* PAL_CPPI41_SR_Q_1502 */\ "PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_5", /* PAL_CPPI41_SR_Q_1503 */\ "PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_6", /* PAL_CPPI41_SR_Q_1504 */\ "PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_7", /* PAL_CPPI41_SR_Q_1505 */\ \ /* Host RX Queues */\ "PAL_CPPI41_SR_CNI_LOW_HOST_RX_Q_NUM", /* PAL_CPPI41_SR_Q_1506 */\ "PAL_CPPI41_SR_CNI_HIGH_HOST_RX_Q_NUM", /* PAL_CPPI41_SR_Q_1507 */\ "PAL_CPPI41_SR_DOCSIS_MGMT_HOST_RX_Q_NUM", /* PAL_CPPI41_SR_Q_1508 */\ "PAL_CPPI41_SR_VOICE_DSP_C55_HOST_RX_Q_NUM", /* PAL_CPPI41_SR_Q_1509 */\ "PAL_CPPI41_SR_MPEG_HOST_RX_Q_NUM", /* PAL_CPPI41_SR_Q_1510 */\ "PAL_CPPI41_SR_L2SW_DATA0_HOST_RX_Q_NUM", /* PAL_CPPI41_SR_Q_1511 */\ "PAL_CPPI41_SR_L2SW_MGMT0_HOST_RX_Q_NUM", /* PAL_CPPI41_SR_Q_1512 */\ "PAL_CPPI41_SR_HOST_RX_Q_7", /* PAL_CPPI41_SR_Q_1513 */\ "PAL_CPPI41_SR_HOST_RX_Q_8", /* PAL_CPPI41_SR_Q_1514 */\ "PAL_CPPI41_SR_HOST_RX_Q_9", /* PAL_CPPI41_SR_Q_1515 */\ "PAL_CPPI41_SR_HOST_RX_Q_10", /* PAL_CPPI41_SR_Q_1516 */\ "PAL_CPPI41_SR_HOST_RX_Q_11", /* PAL_CPPI41_SR_Q_1517 */\ "PAL_CPPI41_SR_HOST_RX_Q_12", /* PAL_CPPI41_SR_Q_1518 */\ "PAL_CPPI41_SR_HOST_RX_Q_13", /* PAL_CPPI41_SR_Q_1519 */\ "PAL_CPPI41_SR_HOST_RX_Q_14", /* PAL_CPPI41_SR_Q_1520 */\ "PAL_CPPI41_SR_HOST_RX_Q_15", /* PAL_CPPI41_SR_Q_1521 */\ \ /* PP to Host Events Queues */\ "PAL_CPPI41_SR_Q_1522", /* PAL_CPPI41_SR_Q_1522 */\ "PAL_CPPI41_SR_Q_1523", /* PAL_CPPI41_SR_Q_1523 */\ "PAL_CPPI41_SR_Q_1524", /* PAL_CPPI41_SR_Q_1524 */\ "PAL_CPPI41_SR_Q_1525", /* PAL_CPPI41_SR_Q_1525 */\ \ /* PP Free Descriptors Queues */\ "PAL_CPPI41_SR_PPDSP_PREFETCH_DESC_FD_Q_NUM", /* PAL_CPPI41_SR_Q_1526 */\ "PAL_CPPI41_SR_Q_1527", /* PAL_CPPI41_SR_Q_1527 */\ "PAL_CPPI41_SR_Q_1528", /* PAL_CPPI41_SR_Q_1528 */\ "PAL_CPPI41_SR_Q_1529", /* PAL_CPPI41_SR_Q_1529 */\ \ /* Host Type Free Descriptors Queues */\ "PAL_CPPI41_SR_CNI_INFRA_LOW_FD_HOST_Q_NUM", /* PAL_CPPI41_SR_Q_1530 */\ "PAL_CPPI41_SR_CNI_INFRA_HIGH_FD_HOST_Q_NUM", /* PAL_CPPI41_SR_Q_1531 */\ "PAL_CPPI41_SR_DOCSIS_MGMT_RX_FD_HOST_Q_NUM", /* PAL_CPPI41_SR_Q_1532 */\ "PAL_CPPI41_SR_DOCSIS_MGMT_TX_FD_HOST_Q_NUM", /* PAL_CPPI41_SR_Q_1533 */\ "PAL_CPPI41_SR_HOST_TO_PP_LOW_FD_HOST_Q_NUM", /* PAL_CPPI41_SR_Q_1534 */\ "PAL_CPPI41_SR_HOST_TO_PP_HIGH_FD_HOST_Q_NUM", /* PAL_CPPI41_SR_Q_1535 */\ "PAL_CPPI41_SR_L2SW_INFRA_FD_HOST_Q_NUM", /* PAL_CPPI41_SR_Q_1536 */\ "PAL_CPPI41_SR_RECYCLE_FD_HOST_Q_NUM", /* PAL_CPPI41_SR_Q_1537 */\ "PAL_CPPI41_SR_COE_MONOLITHIC_FD_Q_NUM", /* PAL_CPPI41_SR_Q_1538 */\ "PAL_CPPI41_SR_COE_FORWARDING_FD_HOST_Q_NUM", /* PAL_CPPI41_SR_Q_1539 */\ "PAL_CPPI41_SR_COE_STREAMING_FD_HOST_Q_NUM", /* PAL_CPPI41_SR_Q_1540 */\ "PAL_CPPI41_SR_Q_1541",\ "PAL_CPPI41_SR_Q_1542",\ "PAL_CPPI41_SR_Q_1543",\ "PAL_CPPI41_SR_Q_1544",\ "PAL_CPPI41_SR_Q_1545",\ "PAL_CPPI41_SR_Q_1546",\ "PAL_CPPI41_SR_Q_1547",\ "PAL_CPPI41_SR_Q_1548",\ "PAL_CPPI41_SR_Q_1549",\ "PAL_CPPI41_SR_Q_1550",\ "PAL_CPPI41_SR_Q_1551",\ "PAL_CPPI41_SR_Q_1552",\ "PAL_CPPI41_SR_Q_1553",\ \ /* Embedded Type Free Descriptors Queues */\ "PAL_CPPI41_SR_DOCSIS_RX_CoP_LOW_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1554 */\ "PAL_CPPI41_SR_DOCSIS_RX_CoP_HIGH_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1555 */\ "PAL_CPPI41_SR_DOCSIS_RX_VOICE_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1556 */\ "PAL_CPPI41_SR_HOST_TO_PP_INFRA_LOW_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1557 */\ "PAL_CPPI41_SR_HOST_TO_PP_INFRA_HIGH_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1558 */\ "PAL_CPPI41_SR_MPEG_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1559 */\ "PAL_CPPI41_SR_MPEG_ENCAP_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1560 */\ "PAL_CPPI41_SR_VOICE_DSP_C55_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1561 */\ "PAL_CPPI41_SR_Q_1562",\ "PAL_CPPI41_SR_PROXY_PDSP_LOW_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1563 */\ "PAL_CPPI41_SR_PROXY_PDSP_MED_LOW_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1564 */\ "PAL_CPPI41_SR_PROXY_PDSP_MED_HIGH_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1565 */\ "PAL_CPPI41_SR_PROXY_PDSP_HIGH_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1566 */\ "PAL_CPPI41_SR_DMA_FD_TEARDOWN_Q_NUM", /* PAL_CPPI41_SR_Q_1567 */\ "PAL_CPPI41_SR_USPREF_PDSP_MGMT_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1568 */\ "PAL_CPPI41_SR_USPREF_PDSP_VOICE_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1569 */\ "PAL_CPPI41_SR_USPREF_PDSP_BE_FD_EMB_Q_NUM", /* PAL_CPPI41_SR_Q_1570 */\ "PAL_CPPI41_SR_Q_1571",\ "PAL_CPPI41_SR_Q_1572",\ "PAL_CPPI41_SR_Q_1573",\ "PAL_CPPI41_SR_Q_1574",\ "PAL_CPPI41_SR_Q_1575",\ "PAL_CPPI41_SR_Q_1576",\ "PAL_CPPI41_SR_Q_1577",\ \ "PAL_CPPI41_SR_DOCSIS_TX_MONOLITHIC_Q_NUM", /* PAL_CPPI41_SR_Q_1578 */\ \ /* DOCSIS TX PreProcessing Queues */\ "PAL_CPPI41_SR_DOCSIS_TX_MGMT_Q_NUM", /* PAL_CPPI41_SR_Q_1579 */\ "PAL_CPPI41_SR_DOCSIS_TX_VOICE_Q_NUM", /* PAL_CPPI41_SR_Q_1580 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE0_Q_NUM", /* PAL_CPPI41_SR_Q_1581 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE1_Q_NUM", /* PAL_CPPI41_SR_Q_1582 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE2_Q_NUM", /* PAL_CPPI41_SR_Q_1583 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE3_Q_NUM", /* PAL_CPPI41_SR_Q_1584 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE4_Q_NUM", /* PAL_CPPI41_SR_Q_1585 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE5_Q_NUM", /* PAL_CPPI41_SR_Q_1586 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE6_Q_NUM", /* PAL_CPPI41_SR_Q_1587 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE7_Q_NUM", /* PAL_CPPI41_SR_Q_1588 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE8_Q_NUM", /* PAL_CPPI41_SR_Q_1589 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE9_Q_NUM", /* PAL_CPPI41_SR_Q_1590 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE10_Q_NUM", /* PAL_CPPI41_SR_Q_1591 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE11_Q_NUM", /* PAL_CPPI41_SR_Q_1592 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE12_Q_NUM", /* PAL_CPPI41_SR_Q_1593 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE13_Q_NUM", /* PAL_CPPI41_SR_Q_1594 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE14_Q_NUM", /* PAL_CPPI41_SR_Q_1595 */\ "PAL_CPPI41_SR_DOCSIS_TX_BE15_Q_NUM", /* PAL_CPPI41_SR_Q_1596 */\ \ "PAL_CPPI41_SR_Q_1597",\ "PAL_CPPI41_SR_Q_1598",\ "PAL_CPPI41_SR_Q_1599",\ "PAL_CPPI41_SR_Q_1600",\ "PAL_CPPI41_SR_Q_1601",\ "PAL_CPPI41_SR_Q_1602",\ "PAL_CPPI41_SR_DOCSIS_TX_CoP_Q_NUM",\ "PAL_CPPI41_SR_MPEG_OUT_PROGRAM0_Q_NUM", /* PAL_CPPI41_SR_Q_1604 */\ "PAL_CPPI41_SR_MPEG_OUT_PROGRAM1_Q_NUM", /* PAL_CPPI41_SR_Q_1605 */\ \ /* DMA2 Infrastructure Input Queues */\ "PAL_CPPI41_SR_DMA2_CNI_INFRA_LOW_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1606 */\ "PAL_CPPI41_SR_DMA2_CNI_INFRA_LOW_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1607 */\ "PAL_CPPI41_SR_DMA2_CNI_INFRA_HIGH_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1608 */\ "PAL_CPPI41_SR_DMA2_CNI_INFRA_HIGH_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1609 */\ "PAL_CPPI41_SR_DMA2_L2SW_DATA0_INFRA_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1610 */\ "PAL_CPPI41_SR_DMA2_L2SW_DATA0_INFRA_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1611 */\ "PAL_CPPI41_SR_DMA2_L2SW_MGMT0_INFRA_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1612 */\ "PAL_CPPI41_SR_DMA2_L2SW_MGMT0_INFRA_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1613 */\ "PAL_CPPI41_SR_DMA2_C55_INFRA_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1614 */\ "PAL_CPPI41_SR_DMA2_C55_INFRA_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1615 */\ "PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA5_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1616 */\ "PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA5_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1617 */\ "PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA6_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1618 */\ "PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA6_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1619 */\ "PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA7_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1620 */\ "PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA7_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1621 */\ "PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA8_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1622 */\ "PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA8_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1623 */\ "PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA9_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1624 */\ "PAL_CPPI41_SR_DMA2_UNASSIGNED_INFRA9_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1625 */\ \ /* DMA3 Infrastructure Input Queues */\ "PAL_CPPI41_SR_DMA3_HOST_TO_PP_LOW_INFRA_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1626 */\ "PAL_CPPI41_SR_DMA3_HOST_TO_PP_LOW_INFRA_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1627 */\ "PAL_CPPI41_SR_DMA3_HOST_TO_PP_HIGH_INFRA_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1628 */\ "PAL_CPPI41_SR_DMA3_HOST_TO_PP_HIGH_INFRA_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1629 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA2_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1630 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA2_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1631 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA3_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1632 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA3_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1633 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA4_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1634 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA4_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1635 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA5_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1636 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA5_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1637 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA6_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1638 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA6_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1639 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA7_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1640 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA7_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1641 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA8_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1642 */\ "PAL_CPPI41_SR_DMA3_UNASSIGNED_INFRA8_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1643 */\ "PAL_CPPI41_SR_DMA3_RECYCLE_INFRA_INPUT_HIGH_Q_NUM", /* PAL_CPPI41_SR_Q_1644 */\ "PAL_CPPI41_SR_DMA3_RECYCLE_INFRA_INPUT_LOW_Q_NUM", /* PAL_CPPI41_SR_Q_1645 */\ \ } /* +-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+ |Q|u|e|u|e| |D|e|f|i|n|i|t|i|o|n|s| +-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+ */ /* Host to PP */ #define PAL_CPPI41_SR_HOST_TO_PP_Q_COUNT 2 #define PAL_CPPI41_SR_HOST_TO_PP_FD_HOST_Q_NUM(pri) (PAL_CPPI41_SR_HOST_TO_PP_LOW_FD_HOST_Q_NUM + (pri)) #define PAL_CPPI41_SR_HOST_TO_PP_LOW_FD_HOST_DESC_COUNT 512 #define PAL_CPPI41_SR_HOST_TO_PP_HIGH_FD_HOST_DESC_COUNT 64 #define PAL_CPPI41_SR_HOST_TO_PP_FD_HOST_DESC_COUNT (PAL_CPPI41_SR_HOST_TO_PP_LOW_FD_HOST_DESC_COUNT + \ PAL_CPPI41_SR_HOST_TO_PP_HIGH_FD_HOST_DESC_COUNT) #define PAL_CPPI41_SR_HOST_TO_PP_FD_HOST_DESC_SIZE 64 #define PAL_CPPI41_SR_HOST_TO_PP_INFRA_INPUT_Q_NUM(pri) (PAL_CPPI41_SR_DMA3_HOST_TO_PP_LOW_INFRA_INPUT_LOW_Q_NUM + (2*(pri))) #define PAL_CPPI41_SR_HOST_TO_PP_INFRA_FD_EMB_Q_NUM(pri) (PAL_CPPI41_SR_HOST_TO_PP_INFRA_LOW_FD_EMB_Q_NUM + (pri)) #define PAL_CPPI41_SR_HOST_TO_PP_INFRA_LOW_FD_EMB_DESC_COUNT 512 #define PAL_CPPI41_SR_HOST_TO_PP_INFRA_HIGH_FD_EMB_DESC_COUNT 64 #define PAL_CPPI41_SR_HOST_TO_QPDSP_EMB_TYPE_Q_NUM(pri) (PAL_CPPI41_SR_HOST_TO_QPDSP_LOW_EMB_TYPE_Q_NUM + (2*(pri))) /* CNI */ #define PAL_CPPI41_SR_CNI_INFRA_INPUT_Q_NUM(pri) (PAL_CPPI41_SR_DMA2_CNI_INFRA_LOW_INPUT_LOW_Q_NUM + (2*(pri))) #define PAL_CPPI41_SR_CNI_INFRA_FD_HOST_Q_NUM(pri) (PAL_CPPI41_SR_CNI_INFRA_LOW_FD_HOST_Q_NUM + (pri)) #define PAL_CPPI41_SR_CNI_INFRA_LOW_FD_HOST_DESC_COUNT 128 #define PAL_CPPI41_SR_CNI_INFRA_HIGH_FD_HOST_DESC_COUNT 64 #define PAL_CPPI41_SR_CNI_INFRA_FD_HOST_DESC_COUNT (PAL_CPPI41_SR_CNI_INFRA_HIGH_FD_HOST_DESC_COUNT + \ PAL_CPPI41_SR_CNI_INFRA_LOW_FD_HOST_DESC_COUNT ) #define PAL_CPPI41_SR_CNI_INFRA_FD_HOST_DESC_SIZE 64 #define PAL_CPPI41_SR_CNI_INFRA_FD_HOST_BUFFER_SIZE 1600 #define PAL_CPPI41_SR_CNI_HOST_RX_Q_NUM(pri) (PAL_CPPI41_SR_CNI_LOW_HOST_RX_Q_NUM + (pri)) #define PAL_CPPI41_SR_CNI_HOST_RX_Q_COUNT (PAL_CPPI41_SR_CNI_HIGH_HOST_RX_Q_NUM - PAL_CPPI41_SR_CNI_LOW_HOST_RX_Q_NUM + 1) /* DOCSIS RX */ #define PAL_CPPI41_SR_DOCSIS_RX_CoP_HIGH_FD_EMB_DESC_COUNT 256 #define PAL_CPPI41_SR_DOCSIS_RX_CoP_LOW_FD_EMB_DESC_COUNT (8*1024) /* DOCSIS TX */ #define PAL_CPPI41_SR_DOCSIS_TX_HIGH_QPDSP_QOS_Q_NUM(clst) (PAL_CPPI41_SR_CLUSTER0_DOCSIS_TX_BE0_HIGH_QPDSP_QOS_Q_NUM + (2*(clst))) #define PAL_CPPI41_SR_DOCSIS_TX_LOW_QPDSP_QOS_Q_NUM(clst) (PAL_CPPI41_SR_CLUSTER0_DOCSIS_TX_BE0_LOW_QPDSP_QOS_Q_NUM + (2*(clst))) #define PAL_CPPI41_SR_DOCSIS_TX_DATA_Q_COUNT 17 #define PAL_CPPI41_SR_DOCSIS_TX_DATA_Q_NUM(pri) (PAL_CPPI41_SR_DOCSIS_TX_VOICE_Q_NUM + (pri)) #define PAL_CPPI41_SR_DOCSIS_TX_DATA_Q_OFFSET(pri) (PAL_CPPI41_SR_DOCSIS_TX_DATA_Q_NUM(pri) - PAL_CPPI41_SR_PrxPDSP_Q_BASE) #define PAL_CPPI41_SR_DOCSIS_TX_MONOLITHIC_DESC_COUNT 32 #define PAL_CPPI41_SR_DOCSIS_TX_MONOLITHIC_DESC_SIZE 128 /* L2Switch */ #define PAL_CPPI41_SR_L2SW_INFRA_INPUT_LOW_Q_NUM(devInstance) (PAL_CPPI41_SR_DMA2_L2SW_DATA0_INFRA_INPUT_LOW_Q_NUM + ((devInstance) * 2)) #define PAL_CPPI41_SR_L2SW_INFRA_FD_HOST_DESC_COUNT 512 #define PAL_CPPI41_SR_L2SW_INFRA_FD_HOST_DESC_SIZE 64 #define PAL_CPPI41_SR_L2SW_INFRA_FD_HOST_BUFFER_SIZE 1600 #define PAL_CPPI41_SR_L2SW_HOST_RX_Q_NUM(devInstance) (PAL_CPPI41_SR_L2SW_HOST_RX_Q_BASE + (devInstance)) #define PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_PRIORITIES_COUNT 4 #define PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_PRIORITY_HIGH 0 #define PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_PRIORITY_MEDHIGH 1 #define PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_PRIORITY_MEDLOW 2 #define PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_PRIORITY_LOW 3 #define PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_NUM(devInstance, pri) (PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_BASE + (PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_PRIORITIES_COUNT*(devInstance)) + (pri)) #define PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_OFFSET(devInstance, pri) (PAL_CPPI41_SR_L2SW_QPDSP_QOS_Q_NUM((devInstance), (pri)) - PAL_CPPI41_SR_QPDSP_QOS_Q_BASE) #define PAL_CPPI41_SR_L2SW_PrxPDSP_Q_NUM(devInstance) (PAL_CPPI41_SR_L2SW_DATA0_PrxPDSP_Q_NUM + (devInstance)) #define PAL_CPPI41_SR_L2SW_PrxPDSP_Q_OFFSET(devInstance) (PAL_CPPI41_SR_L2SW_PrxPDSP_Q_NUM(devInstance) - PAL_CPPI41_SR_PrxPDSP_Q_BASE) /* Packet Processor */ #define PAL_CPPI41_SR_PPDSP_PREFETCH_DESC_FD_DESC_COUNT 64 #define PAL_CPPI41_SR_PPDSP_PREFETCH_DESC_FD_DESC_SIZE 128 /* DOCSIS Management RX */ #define PAL_CPPI41_SR_DOCSIS_MGMT_RX_FD_HOST_DESC_COUNT 64 #define PAL_CPPI41_SR_DOCSIS_MGMT_RX_FD_HOST_DESC_SIZE 64 #define PAL_CPPI41_SR_DOCSIS_MGMT_RX_FD_HOST_BUFF_SIZE 2048 /* DOCSIS Management TX */ #define PAL_CPPI41_SR_DOCSIS_MGMT_TX_FD_HOST_DESC_COUNT 64 #define PAL_CPPI41_SR_DOCSIS_MGMT_TX_FD_HOST_DESC_SIZE 64 #define PAL_CPPI41_SR_DOCSIS_MGMT_TX_FD_HOST_BUFF_SIZE 2048 /* Host TX Complete */ #define PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_NUM(pri) (PAL_CPPI41_SR_HOST_TX_COMPLETE_Q_BASE + (pri)) /* Recycle */ #define PAL_CPPI41_RECYCLE_INFRA_INPUT_LOW_Q_NUM PAL_CPPI41_SR_DMA3_RECYCLE_INFRA_INPUT_LOW_Q_NUM // For backward compatible /* Proxy PDSP */ #define PAL_CPPI41_SR_PROXY_PDSP_LOW_FD_EMB_DESC_COUNT 960 #define PAL_CPPI41_SR_PROXY_PDSP_HIGH_FD_EMB_DESC_COUNT 64 #define PAL_CPPI41_SR_PROXY_PDSP_FD_EMB_DESC_SIZE 64 /* COE */ #define PAL_CPPI41_SR_COE_MONOLITHIC_FD_DESC_COUNT 32 #define PAL_CPPI41_SR_COE_MONOLITHIC_FD_DESC_SIZE 256 #define PAL_CPPI41_SR_COE_FORWARDING_FD_HOST_DESC_COUNT 16 #define PAL_CPPI41_SR_COE_FORWARDING_FD_HOST_DESC_SIZE 64 #define PAL_CPPI41_SR_COE_STREAMING_FD_HOST_DESC_COUNT 64 #define PAL_CPPI41_SR_COE_STREAMING_FD_HOST_DESC_SIZE 32 /* +-+-+-+-+-+-+ +-+-+-+-+-+ +-+-+-+-+-+-+-+ |D|O|C|S|I|S| |Q|u|e|u|e| |M|a|n|a|g|e|r| +-+-+-+-+-+-+ +-+-+-+-+-+ +-+-+-+-+-+-+-+ */ typedef enum PAL_CPPI41_DOCSIS_US_QMGR_QUEUES { PAL_CPPI41_DOCSIS_INTERNAL_Q_BASE, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE0_Q_HIGH = PAL_CPPI41_DOCSIS_INTERNAL_Q_BASE, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE0_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE1_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE1_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE2_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE2_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE3_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE3_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE4_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE4_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE5_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE5_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE6_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE6_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE7_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE7_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE8_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE8_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE9_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE9_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE10_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE10_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE11_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE11_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE12_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE12_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE13_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE13_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE14_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE14_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE15_Q_HIGH, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE15_Q_LOW, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS31_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS30_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS29_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS28_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS27_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS26_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS25_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS24_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS23_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS22_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS21_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS20_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS19_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS18_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS17_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS16_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS15_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS14_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS13_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS12_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS11_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS10_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS9_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS8_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS7_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS6_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS5_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS4_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS3_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS2_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS1_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS0_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_MGMT_Q, PAL_CPPI41_DOCSIS_US_RX_CO_PROC_HIGH_Q, PAL_CPPI41_DOCSIS_US_TX_MAC_Q0, PAL_CPPI41_DOCSIS_US_TX_MAC_Q1, PAL_CPPI41_DOCSIS_US_TX_MAC_Q2, PAL_CPPI41_DOCSIS_US_TX_MAC_Q3, PAL_CPPI41_DOCSIS_US_TX_MAC_Q4, PAL_CPPI41_DOCSIS_US_TX_MAC_Q5, PAL_CPPI41_DOCSIS_US_TX_MAC_Q6, PAL_CPPI41_DOCSIS_US_TX_MAC_Q7, PAL_CPPI41_DOCSIS_US_FD_EMB_Q, PAL_CPPI41_DOCSIS_US_FD_MONO_Q, PAL_CPPI41_DOCSIS_US_Q_76, PAL_CPPI41_DOCSIS_US_Q_77, PAL_CPPI41_DOCSIS_US_Q_78, PAL_CPPI41_DOCSIS_US_Q_79, PAL_CPPI41_DOCSIS_US_QMGR_TOTAL_Q_COUNT }PAL_CPPI41_DOCSIS_US_QMGR_QUEUES_e; #define PAL_CPPI41_DOCSIS_US_QMGR_QUEUES_STR(v) \ static char * v[ PAL_CPPI41_DOCSIS_US_QMGR_TOTAL_Q_COUNT ] = \ {\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE0_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE0_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE1_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE1_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE2_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE2_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE3_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE3_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE4_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE4_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE5_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE5_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE6_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE6_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE7_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE7_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE8_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE8_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE9_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE9_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE10_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE10_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE11_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE11_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE12_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE12_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE13_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE13_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE14_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE14_Q_LOW",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE15_Q_HIGH",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_BE15_Q_LOW",\ \ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS31_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS30_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS29_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS28_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS27_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS26_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS25_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS24_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS23_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS22_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS21_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS20_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS19_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS18_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS17_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS16_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS15_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS14_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS13_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS12_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS11_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS10_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS9_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS8_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS7_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS6_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS5_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS4_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS3_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS2_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS1_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_UGS0_Q",\ \ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_MGMT_Q",\ "PAL_CPPI41_DOCSIS_US_RX_CO_PROC_HIGH_Q",\ \ "PAL_CPPI41_DOCSIS_US_TX_MAC_Q0",\ "PAL_CPPI41_DOCSIS_US_TX_MAC_Q1",\ "PAL_CPPI41_DOCSIS_US_TX_MAC_Q2",\ "PAL_CPPI41_DOCSIS_US_TX_MAC_Q3",\ "PAL_CPPI41_DOCSIS_US_TX_MAC_Q4",\ "PAL_CPPI41_DOCSIS_US_TX_MAC_Q5",\ "PAL_CPPI41_DOCSIS_US_TX_MAC_Q6",\ "PAL_CPPI41_DOCSIS_US_TX_MAC_Q7",\ \ "PAL_CPPI41_DOCSIS_US_FD_EMB_Q",\ "PAL_CPPI41_DOCSIS_US_FD_MONO_Q",\ "PAL_CPPI41_DOCSIS_US_Q_76",\ "PAL_CPPI41_DOCSIS_US_Q_77",\ "PAL_CPPI41_DOCSIS_US_Q_78",\ "PAL_CPPI41_DOCSIS_US_Q_79"\ } #define PAL_CPPI41_DOCSIS_US_FD_EMB_DESC_SIZE 32 #define PAL_CPPI41_DOCSIS_US_FD_EMB_DESC_COUNT (256 + 16) // num of buffers + 2 per service flow( for fragmentation ) typedef enum PAL_CPPI41_DOCSIS_DS_QMGR_QUEUES { PAL_CPPI41_DOCSIS_DS_Q_0, PAL_CPPI41_DOCSIS_DS_Q_1, PAL_CPPI41_DOCSIS_DS_Q_2, PAL_CPPI41_DOCSIS_DS_Q_3, PAL_CPPI41_DOCSIS_DS_Q_4, PAL_CPPI41_DOCSIS_DS_Q_5, PAL_CPPI41_DOCSIS_DS_Q_6, PAL_CPPI41_DOCSIS_DS_Q_7, PAL_CPPI41_DOCSIS_DS_Q_8, PAL_CPPI41_DOCSIS_DS_Q_9, PAL_CPPI41_DOCSIS_DS_Q_10, PAL_CPPI41_DOCSIS_DS_Q_11, PAL_CPPI41_DOCSIS_DS_Q_12, PAL_CPPI41_DOCSIS_DS_Q_13, PAL_CPPI41_DOCSIS_DS_Q_14, PAL_CPPI41_DOCSIS_DS_Q_15, PAL_CPPI41_DOCSIS_DS_CoP_Q, /* PAL_CPPI41_DOCSIS_DS_Q_16, */ PAL_CPPI41_DOCSIS_DS_Q_17, PAL_CPPI41_DOCSIS_DS_Q_18, PAL_CPPI41_DOCSIS_DS_Q_19, PAL_CPPI41_DOCSIS_DS_Q_20, PAL_CPPI41_DOCSIS_DS_Q_21, PAL_CPPI41_DOCSIS_DS_Q_22, PAL_CPPI41_DOCSIS_DS_Q_23, PAL_CPPI41_DOCSIS_DS_Q_24, PAL_CPPI41_DOCSIS_DS_Q_25, PAL_CPPI41_DOCSIS_DS_Q_26, PAL_CPPI41_DOCSIS_DS_Q_27, PAL_CPPI41_DOCSIS_DS_Q_28, PAL_CPPI41_DOCSIS_DS_Q_29, PAL_CPPI41_DOCSIS_DS_Q_30, PAL_CPPI41_DOCSIS_DS_Q_31, PAL_CPPI41_DOCSIS_DS_Q_32, PAL_CPPI41_DOCSIS_DS_Q_33, PAL_CPPI41_DOCSIS_DS_Q_34, PAL_CPPI41_DOCSIS_DS_Q_35, PAL_CPPI41_DOCSIS_DS_Q_36, PAL_CPPI41_DOCSIS_DS_Q_37, PAL_CPPI41_DOCSIS_DS_Q_38, PAL_CPPI41_DOCSIS_DS_Q_39, PAL_CPPI41_DOCSIS_DS_Q_40, PAL_CPPI41_DOCSIS_DS_Q_41, PAL_CPPI41_DOCSIS_DS_Q_42, PAL_CPPI41_DOCSIS_DS_Q_43, PAL_CPPI41_DOCSIS_DS_Q_44, PAL_CPPI41_DOCSIS_DS_Q_45, PAL_CPPI41_DOCSIS_DS_Q_46, PAL_CPPI41_DOCSIS_DS_Q_47, PAL_CPPI41_DOCSIS_DS_Q_48, PAL_CPPI41_DOCSIS_DS_Q_49, PAL_CPPI41_DOCSIS_DS_Q_50, PAL_CPPI41_DOCSIS_DS_Q_51, PAL_CPPI41_DOCSIS_DS_Q_52, PAL_CPPI41_DOCSIS_DS_Q_53, PAL_CPPI41_DOCSIS_DS_Q_54, PAL_CPPI41_DOCSIS_DS_Q_55, PAL_CPPI41_DOCSIS_DS_Q_56, PAL_CPPI41_DOCSIS_DS_Q_57, PAL_CPPI41_DOCSIS_DS_FD_EMB_Q, /* PAL_CPPI41_DOCSIS_DS_Q_58, */ PAL_CPPI41_DOCSIS_DS_Q_59, PAL_CPPI41_DOCSIS_DS_Q_60, PAL_CPPI41_DOCSIS_DS_Q_61, PAL_CPPI41_DOCSIS_DS_Q_62, PAL_CPPI41_DOCSIS_DS_Q_63, PAL_CPPI41_DOCSIS_DS_QMGR_TOTAL_Q_COUNT }PAL_CPPI41_DOCSIS_DS_QMGR_QUEUES_e; #define PAL_CPPI41_DOCSIS_DS_QMGR_QUEUES_STR(v) \ static char * v[ PAL_CPPI41_DOCSIS_DS_QMGR_TOTAL_Q_COUNT ] = \ {\ "PAL_CPPI41_DOCSIS_DS_Q_0",\ "PAL_CPPI41_DOCSIS_DS_Q_1",\ "PAL_CPPI41_DOCSIS_DS_Q_2",\ "PAL_CPPI41_DOCSIS_DS_Q_3",\ "PAL_CPPI41_DOCSIS_DS_Q_4",\ "PAL_CPPI41_DOCSIS_DS_Q_5",\ "PAL_CPPI41_DOCSIS_DS_Q_6",\ "PAL_CPPI41_DOCSIS_DS_Q_7",\ "PAL_CPPI41_DOCSIS_DS_Q_8",\ "PAL_CPPI41_DOCSIS_DS_Q_9",\ "PAL_CPPI41_DOCSIS_DS_Q_10",\ "PAL_CPPI41_DOCSIS_DS_Q_11",\ "PAL_CPPI41_DOCSIS_DS_Q_12",\ "PAL_CPPI41_DOCSIS_DS_Q_13",\ "PAL_CPPI41_DOCSIS_DS_Q_14",\ "PAL_CPPI41_DOCSIS_DS_Q_15",\ \ "PAL_CPPI41_DOCSIS_DS_CoP_Q", /* PAL_CPPI41_DOCSIS_DS_Q_16, */\ \ "PAL_CPPI41_DOCSIS_DS_Q_17",\ "PAL_CPPI41_DOCSIS_DS_Q_18",\ "PAL_CPPI41_DOCSIS_DS_Q_19",\ "PAL_CPPI41_DOCSIS_DS_Q_20",\ "PAL_CPPI41_DOCSIS_DS_Q_21",\ "PAL_CPPI41_DOCSIS_DS_Q_22",\ "PAL_CPPI41_DOCSIS_DS_Q_23",\ "PAL_CPPI41_DOCSIS_DS_Q_24",\ "PAL_CPPI41_DOCSIS_DS_Q_25",\ "PAL_CPPI41_DOCSIS_DS_Q_26",\ "PAL_CPPI41_DOCSIS_DS_Q_27",\ "PAL_CPPI41_DOCSIS_DS_Q_28",\ "PAL_CPPI41_DOCSIS_DS_Q_29",\ "PAL_CPPI41_DOCSIS_DS_Q_30",\ "PAL_CPPI41_DOCSIS_DS_Q_31",\ "PAL_CPPI41_DOCSIS_DS_Q_32",\ "PAL_CPPI41_DOCSIS_DS_Q_33",\ "PAL_CPPI41_DOCSIS_DS_Q_34",\ "PAL_CPPI41_DOCSIS_DS_Q_35",\ "PAL_CPPI41_DOCSIS_DS_Q_36",\ "PAL_CPPI41_DOCSIS_DS_Q_37",\ "PAL_CPPI41_DOCSIS_DS_Q_38",\ "PAL_CPPI41_DOCSIS_DS_Q_39",\ "PAL_CPPI41_DOCSIS_DS_Q_40",\ "PAL_CPPI41_DOCSIS_DS_Q_41",\ "PAL_CPPI41_DOCSIS_DS_Q_42",\ "PAL_CPPI41_DOCSIS_DS_Q_43",\ "PAL_CPPI41_DOCSIS_DS_Q_44",\ "PAL_CPPI41_DOCSIS_DS_Q_45",\ "PAL_CPPI41_DOCSIS_DS_Q_46",\ "PAL_CPPI41_DOCSIS_DS_Q_47",\ "PAL_CPPI41_DOCSIS_DS_Q_48",\ "PAL_CPPI41_DOCSIS_DS_Q_49",\ "PAL_CPPI41_DOCSIS_DS_Q_50",\ "PAL_CPPI41_DOCSIS_DS_Q_51",\ "PAL_CPPI41_DOCSIS_DS_Q_52",\ "PAL_CPPI41_DOCSIS_DS_Q_53",\ "PAL_CPPI41_DOCSIS_DS_Q_54",\ "PAL_CPPI41_DOCSIS_DS_Q_55",\ "PAL_CPPI41_DOCSIS_DS_Q_56",\ "PAL_CPPI41_DOCSIS_DS_Q_57",\ "PAL_CPPI41_DOCSIS_DS_FD_EMB_Q", /* PAL_CPPI41_DOCSIS_DS_Q_58, */\ "PAL_CPPI41_DOCSIS_DS_Q_59",\ "PAL_CPPI41_DOCSIS_DS_Q_60",\ "PAL_CPPI41_DOCSIS_DS_Q_61",\ "PAL_CPPI41_DOCSIS_DS_Q_62",\ "PAL_CPPI41_DOCSIS_DS_Q_63",\ } #define PAL_CPPI41_DOCSIS_DS_FD_EMB_DESC_SIZE 128 #define PAL_CPPI41_DOCSIS_DS_FD_EMB_DESC_COUNT 64 /********************************************************************************************************************** ######## ## ## ######## ######## ######## ######## ## ## ### ## ## ### ###### ######## ######## ## ## ## ## ## ## ## ## ## ### ### ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## #### #### ## ## #### ## ## ## ## ## ## ## ######## ## ## ###### ###### ###### ######## ## ### ## ## ## ## ## ## ## ## ## #### ###### ######## ## ## ## ## ## ## ## ## ## ## ## ######### ## #### ######### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ### ## ## ## ## ## ## ## ######## ####### ## ## ######## ## ## ## ## ## ## ## ## ## ## ###### ######## ## ## pool# pool size buf size RefC Usage 0 0 0 0 1 0 0 0 2 4096 256 0 DOCSIS RX Low 256B nonMC evenCh 3 4096 256 0 DOCSIS RX Low 256B nonMC oddCh 4 4096 512 0 DOCSIS RX Low 512B nonMC 5 2048 2048 0 DOCSIS RX Low 2KB nonMC 6 64 2048 1 DOCSIS RX Low 2KB MC 7 64 2048 0 DOCSIS RX High 8 64 1024 0 DOCSIS RX VOICE 9 256 2048 0 Host-->PP Infra 10 1024 256 1 LanPrxPDSP 256B 11 1024 2048 1 LanPrxPDSP 2KB 12 64 256 1 MPEG 13 64 128 0 MPEG Encap 17 512 1024 0 C55 Voice DSP **********************************************************************************************************************/ #define PAL_CPPI41_NUM_BUF_MGR 2 /**< Number of buffer managers in the system */ #define PAL_CPPI41_BUF_MGR_PARTITION_SR 0 #define PAL_CPPI41_BUF_MGR_PARTITION_DOCSIS 1 #define PAL_CPPI41_BUF_MGR_PARTITION_DOCSIS_DS_GROUP 0 typedef enum PAL_CPPI41_BUFFER_POOL_MANAGERS { BUF_POOL_MGR0, BUF_POOL_MGR1, PAL_CPPI41_BUFFER_POOL_MAX_MANAGERES }PAL_CPPI41_BUFFER_POOL_MANAGERS_e; typedef enum PAL_CPPI41_BUFFER_POOL_NUM { PAL_CPPI41_BMGR_POOL0, PAL_CPPI41_BMGR_POOL1, PAL_CPPI41_BMGR_POOL2, PAL_CPPI41_BMGR_POOL3, PAL_CPPI41_BMGR_POOL4, PAL_CPPI41_BMGR_POOL5, PAL_CPPI41_BMGR_POOL6, PAL_CPPI41_BMGR_POOL7, PAL_CPPI41_BMGR_POOL8, PAL_CPPI41_BMGR_POOL9, PAL_CPPI41_BMGR_POOL10, PAL_CPPI41_BMGR_POOL11, PAL_CPPI41_BMGR_POOL12, PAL_CPPI41_BMGR_POOL13, PAL_CPPI41_BMGR_POOL14, PAL_CPPI41_BMGR_POOL15, PAL_CPPI41_BMGR_POOL16, PAL_CPPI41_BMGR_POOL17, PAL_CPPI41_BMGR_MAX_POOLS = 18 }PAL_CPPI41_BUFFER_POOL_NUM_e; /* +-+-+-+-+-+-+ +-+-+-+-+-+-+-+ +-+ |B|u|f|f|e|r| |M|a|n|a|g|e|r| |0| +-+-+-+-+-+-+ +-+-+-+-+-+-+-+ +-+ */ /* Buffer Manager0 number of buffers per pool */ #define BMGR0_POOL00_BUF_COUNT 0 /* */ #define BMGR0_POOL01_BUF_COUNT 0 /* */ #define BMGR0_POOL02_BUF_COUNT 4096 /* DOCSIS RX Low 256B nonMC evenCh */ #define BMGR0_POOL03_BUF_COUNT 4096 /* DOCSIS RX Low 256B nonMC oddCh */ #define BMGR0_POOL04_BUF_COUNT 4096 /* DOCSIS RX Low 512B nonMC */ #define BMGR0_POOL05_BUF_COUNT 2048 /* DOCSIS RX Low 2KB nonMC */ #define BMGR0_POOL06_BUF_COUNT 64 /* DOCSIS RX Low 2KB MC */ #define BMGR0_POOL07_BUF_COUNT 64 /* DOCSIS RX High */ #define BMGR0_POOL08_BUF_COUNT 64 /* DOCSIS RX VOICE */ #define BMGR0_POOL09_BUF_COUNT 256 /* Host-->PP Infra */ #define BMGR0_POOL10_BUF_COUNT 1024 /* LanPrxPDSP 256B */ #define BMGR0_POOL11_BUF_COUNT 1024 /* LanPrxPDSP 2KB */ #define BMGR0_POOL12_BUF_COUNT 64 /* MPEG */ #define BMGR0_POOL13_BUF_COUNT 64 /* MPEG Encap */ #define BMGR0_POOL17_BUF_COUNT 512 /* C55 Voice DSP */ /* Buffer Manager0 size of buffers per pool */ #define BMGR0_POOL00_BUF_SIZE 0 /* */ #define BMGR0_POOL01_BUF_SIZE 0 /* */ #define BMGR0_POOL02_BUF_SIZE 256 /* DOCSIS RX Low 256B nonMC evenCh */ #define BMGR0_POOL03_BUF_SIZE 256 /* DOCSIS RX Low 256B nonMC oddCh */ #define BMGR0_POOL04_BUF_SIZE 512 /* DOCSIS RX Low 512B nonMC */ #define BMGR0_POOL05_BUF_SIZE 2048 /* DOCSIS RX Low 2KB nonMC */ #define BMGR0_POOL06_BUF_SIZE 2048 /* DOCSIS RX Low 2KB MC */ #define BMGR0_POOL07_BUF_SIZE 2048 /* DOCSIS RX High */ #define BMGR0_POOL08_BUF_SIZE 1024 /* DOCSIS RX VOICE */ #define BMGR0_POOL09_BUF_SIZE 2048 /* Host-->PP Infra */ #define BMGR0_POOL10_BUF_SIZE 256 /* LanPrxPDSP 256B */ #define BMGR0_POOL11_BUF_SIZE 2048 /* LanPrxPDSP 2KB */ #define BMGR0_POOL12_BUF_SIZE 256 /* MPEG */ #define BMGR0_POOL13_BUF_SIZE 128 /* MPEG Encap */ #define BMGR0_POOL17_BUF_SIZE 1024 /* C55 Voice DSP */ /* Buffer Manager0 reference counter indication per pool */ #define BMGR0_POOL00_REF_CNT 0 /* */ #define BMGR0_POOL01_REF_CNT 0 /* */ #define BMGR0_POOL02_REF_CNT 0 /* DOCSIS RX Low 256B nonMC evenCh */ #define BMGR0_POOL03_REF_CNT 0 /* DOCSIS RX Low 256B nonMC oddCh */ #define BMGR0_POOL04_REF_CNT 0 /* DOCSIS RX Low 512B nonMC */ #define BMGR0_POOL05_REF_CNT 0 /* DOCSIS RX Low 2KB nonMC */ #define BMGR0_POOL06_REF_CNT 1 /* DOCSIS RX Low 2KB MC */ #define BMGR0_POOL07_REF_CNT 0 /* DOCSIS RX High */ #define BMGR0_POOL08_REF_CNT 0 /* DOCSIS RX VOICE */ #define BMGR0_POOL09_REF_CNT 0 /* Host-->PP Infra */ #define BMGR0_POOL10_REF_CNT 1 /* LanPrxPDSP 256B */ #define BMGR0_POOL11_REF_CNT 1 /* LanPrxPDSP 2KB */ #define BMGR0_POOL12_REF_CNT 1 /* MPEG */ #define BMGR0_POOL13_REF_CNT 0 /* MPEG Encap */ #define BMGR0_POOL17_REF_CNT 0 /* C55 Voice DSP */ /* +-+-+-+-+-+-+ +-+-+-+-+-+-+-+ +-+ |B|u|f|f|e|r| |M|a|n|a|g|e|r| |1| +-+-+-+-+-+-+ +-+-+-+-+-+-+-+ +-+ */ #define BMGR1_POOL00_BUF_COUNT 256 /* DOCSIS TX CoP After */ #define BMGR1_POOL00_BUF_SIZE 2048 #define BMGR1_POOL00_REF_CNT 1 /* +-+-+-+-+-+-+ +-+-+-+-+-+-+-+ +-+-+-+ |B|u|f|f|e|r| |M|a|n|a|g|e|r| |D|S|G| +-+-+-+-+-+-+ +-+-+-+-+-+-+-+ +-+-+-+ */ #define BUF_POOL_DS_GROUP_MGR 0 #define BMGR_DS_GROUP_POOL00_BUF_COUNT 128 #define BMGR_DS_GROUP_POOL00_BUF_SIZE 512 #define BMGR_DS_GROUP_POOL00_REF_CNT 0 /********************************************************************************************************************** ######## ## ## ### ###### ## ## ### ## ## ## ## ######## ## ###### ## ## ### ### ## ## ## ## ## ## ## ## ### ## ### ## ## ## ## ## ## ## #### #### ## ## ## ## ## ## ## #### ## #### ## ## ## ## ## ## ## ### ## ## ## ## ######### ## ## ## ## ## ## ## ## ###### ## ###### ## ## ## ## ######### ## ## ## ######### ## #### ## #### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ### ## ### ## ## ## ## ######## ## ## ## ## ###### ## ## ## ## ## ## ## ## ######## ######## ###### **********************************************************************************************************************/ typedef enum PAL_CPPI41_SR_DMA_BLOCKS { PAL_CPPI41_DMA_BLOCK0, PAL_CPPI41_DMA_BLOCK1, PAL_CPPI41_DMA_BLOCK2, PAL_CPPI41_DMA_BLOCK3, PAL_CPPI41_NUM_DMA_BLOCK }PAL_CPPI41_SR_DMA_BLOCKS_e; #define PAL_CPPI41_SR_DMA_MAX_TX_CHANNELS 22 /**< Max CPPI4.1 Tx channles that could be opened */ #define PAL_CPPI41_SR_DMA_MAX_RX_CHANNELS 22 /**< Max CPPI4.1 Rx channles that could be opened */ #define PAL_CPPI41_NUM_TOTAL_CHAN 22 /**< Number of total channels */ /* +-+-+-+ +-+-+ +-+-+ +-+-+-+-+-+-+-+-+ |D|M|A| |0|1| |R|X| |C|h|a|n|n|e|l|s| +-+-+-+ +-+-+ +-+-+ +-+-+-+-+-+-+-+-+ */ // PAL_CPPI41_SR_DOCSIS_DS_CoP_LOW0_DMA01_RX_CH_NUM typedef enum PAL_CPPI41_SR_DMA01_RX_CHANNELS { PAL_CPPI41_SR_DOCSIS_DS_CoP_MGMT_DMA01_RX_CH_NUM, // 0 PAL_CPPI41_SR_DOCSIS_DS_CoP_COE_DMA01_RX_CH_NUM, // 1 PAL_CPPI41_SR_DOCSIS_DS_CoP_DATA_FIRST_RX_CH, PAL_CPPI41_SR_DOCSIS_DS_CoP_LOW_256B_NONMC_EVEN_DMA01_RX_CH_NUM = PAL_CPPI41_SR_DOCSIS_DS_CoP_DATA_FIRST_RX_CH, // 2 PAL_CPPI41_SR_DOCSIS_DS_CoP_LOW_256B_NONMC_ODD_DMA01_RX_CH_NUM, // 3 PAL_CPPI41_SR_DOCSIS_DS_CoP_LOW_512B_NONMC_DMA01_RX_CH_NUM, // 4 PAL_CPPI41_SR_DOCSIS_DS_CoP_LOW_2KB_NONMC_DMA01_RX_CH_NUM, // 5 PAL_CPPI41_SR_DOCSIS_DS_CoP_LOW_2KB_MC_DMA01_RX_CH_NUM, // 6 PAL_CPPI41_SR_DOCSIS_DS_CoP_HIGH_DMA01_RX_CH_NUM, // 7 PAL_CPPI41_SR_DOCSIS_DS_CoP_VOICE_DMA01_RX_MAX_CH, // 8 PAL_CPPI41_SR_DOCSIS_DS_CoP_DATA_LAST_RX_CH = PAL_CPPI41_SR_DOCSIS_DS_CoP_VOICE_DMA01_RX_MAX_CH, PAL_CPPI41_SR_RESERVED_DMA01_RX_CH_NUM_9, // 9 PAL_CPPI41_SR_RESERVED_DMA01_RX_CH_NUM_10, // 10 PAL_CPPI41_SR_RESERVED_DMA01_RX_CH_NUM_11, // 11 PAL_CPPI41_SR_RESERVED_DMA01_RX_CH_NUM_12, // 12 PAL_CPPI41_SR_RESERVED_DMA01_RX_CH_NUM_13, // 13 PAL_CPPI41_SR_DMA01_RX_CHANNELS = 14 }PAL_CPPI41_SR_DMA01_RX_CHANNELS_e; #define PAL_CPPI41_SR_DOCSIS_DS_CoP_DATA_NUM_RX_CH (PAL_CPPI41_SR_DOCSIS_DS_CoP_DATA_LAST_RX_CH - PAL_CPPI41_SR_DOCSIS_DS_CoP_DATA_FIRST_RX_CH + 1) /* +-+-+-+ +-+ +-+-+ +-+-+-+-+-+-+-+-+ |D|M|A| |2| |T|X| |C|h|a|n|n|e|l|s| +-+-+-+ +-+ +-+-+ +-+-+-+-+-+-+-+-+ */ typedef enum PAL_CPPI41_SR_DMA2_TX_CHANNELS { /* US MACPHY channels */ PAL_CPPI41_SR_DOCSIS_TX_US0_DMA2_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US1_DMA2_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US2_DMA2_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US3_DMA2_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US4_DMA2_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US5_DMA2_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US6_DMA2_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US7_DMA2_TX_CH_NUM, /* US CoP TX CH*/ PAL_CPPI41_SR_DOCSIS_TX_COP_DMA2_TX_CH_NUM, /* Reserved */ PAL_CPPI41_SR_RESERVED_DMA2_TX_CH_NUM_9, PAL_CPPI41_SR_RESERVED_DMA2_TX_CH_NUM_10, PAL_CPPI41_SR_RESERVED_DMA2_TX_CH_NUM_11, /* Network Devices Infrastructure TX CH */ PAL_CPPI41_SR_CNI_LOW_INFRA_DMA2_TX_CH_NUM, PAL_CPPI41_SR_CNI_HIGH_INFRA_DMA2_TX_CH_NUM, PAL_CPPI41_SR_L2SW_INFRA_DMA2_TX_CH_BASE, PAL_CPPI41_SR_L2SW_DATA0_INFRA_DMA2_TX_CH_NUM = PAL_CPPI41_SR_L2SW_INFRA_DMA2_TX_CH_BASE, // 14 PAL_CPPI41_SR_L2SW_MGMT0_INFRA_DMA2_TX_CH_NUM, // 15 PAL_CPPI41_SR_L2SW_INFRA_DMA2_TX_CH_LAST = PAL_CPPI41_SR_L2SW_MGMT0_INFRA_DMA2_TX_CH_NUM, /* Voice Infrastructure DMA channel */ PAL_CPPI41_SR_C55_INFRA_DMA2_TX_CH_NUM, /* Unused Infrastructure TX CH */ PAL_CPPI41_SR_RESERVED_INFRA5_DMA2_TX_CH_NUM_17, PAL_CPPI41_SR_RESERVED_INFRA6_DMA2_TX_CH_NUM_18, PAL_CPPI41_SR_RESERVED_INFRA7_DMA2_TX_CH_NUM_19, PAL_CPPI41_SR_RESERVED_INFRA8_DMA2_TX_CH_NUM_20, PAL_CPPI41_SR_RESERVED_INFRA9_DMA2_TX_CH_NUM_21, PAL_CPPI41_SR_DMA2_MAX_TX_CHANNELS }PAL_CPPI41_SR_DMA2_TX_CHANNELS_e; /* +-+-+-+ +-+ +-+-+ +-+-+-+-+-+-+-+-+ |D|M|A| |2| |R|X| |C|h|a|n|n|e|l|s| +-+-+-+ +-+ +-+-+ +-+-+-+-+-+-+-+-+ */ typedef enum PAL_CPPI41_SR_DMA2_RX_CHANNELS { /* Reserved */ PAL_CPPI41_SR_RESERVED_DMA2_RX_CH_NUM_0, PAL_CPPI41_SR_RESERVED_DMA2_RX_CH_NUM_1, PAL_CPPI41_SR_RESERVED_DMA2_RX_CH_NUM_2, PAL_CPPI41_SR_RESERVED_DMA2_RX_CH_NUM_3, PAL_CPPI41_SR_RESERVED_DMA2_RX_CH_NUM_4, PAL_CPPI41_SR_RESERVED_DMA2_RX_CH_NUM_5, PAL_CPPI41_SR_RESERVED_DMA2_RX_CH_NUM_6, PAL_CPPI41_SR_RESERVED_DMA2_RX_CH_NUM_7, PAL_CPPI41_SR_RESERVED_DMA2_RX_CH_NUM_8, /* US CoP RX CH*/ PAL_CPPI41_SR_DOCSIS_TX_COP0_DMA2_RX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_COP1_DMA2_RX_CH_NUM, /* Reserved */ PAL_CPPI41_SR_RESERVED_DMA2_RX_CH_NUM_11, /* Netword Devices Infrastructure RX CH */ PAL_CPPI41_SR_CNI_LOW_INFRA_DMA2_RX_CH_NUM, PAL_CPPI41_SR_CNI_HIGH_INFRA_DMA2_RX_CH_NUM, PAL_CPPI41_SR_L2SW_INFRA_DMA2_RX_CH_BASE, PAL_CPPI41_SR_L2SW_DATA0_INFRA_DMA2_RX_CH_NUM = PAL_CPPI41_SR_L2SW_INFRA_DMA2_RX_CH_BASE, // 14 PAL_CPPI41_SR_L2SW_MGMT0_INFRA_DMA2_RX_CH_NUM, // 15 PAL_CPPI41_SR_L2SW_INFRA_DMA2_RX_CH_LAST = PAL_CPPI41_SR_L2SW_MGMT0_INFRA_DMA2_RX_CH_NUM, /* Voice Infrastructure DMA channel */ PAL_CPPI41_SR_C55_INFRA_DMA2_RX_CH_NUM, /* Unused Infrastructure RX CH */ PAL_CPPI41_SR_RESERVED_INFRA5_DMA2_RX_CH_NUM_17, PAL_CPPI41_SR_RESERVED_INFRA6_DMA2_RX_CH_NUM_18, PAL_CPPI41_SR_RESERVED_INFRA7_DMA2_RX_CH_NUM_19, PAL_CPPI41_SR_RESERVED_INFRA8_DMA2_RX_CH_NUM_20, PAL_CPPI41_SR_RESERVED_INFRA9_DMA2_RX_CH_NUM_21, PAL_CPPI41_SR_DMA2_MAX_RX_CHANNELS }PAL_CPPI41_SR_DMA2_RX_CHANNELS_e; /* +-+-+-+ +-+ +-+-+ +-+-+-+-+-+-+-+-+ |D|M|A| |3| |T|X| |C|h|a|n|n|e|l|s| +-+-+-+ +-+ +-+-+ +-+-+-+-+-+-+-+-+ */ typedef enum PAL_CPPI41_SR_DMA3_TX_CHANNELS { /* US MACPHY channels */ PAL_CPPI41_SR_DOCSIS_TX_US0_DMA3_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US1_DMA3_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US2_DMA3_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US3_DMA3_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US4_DMA3_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US5_DMA3_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US6_DMA3_TX_CH_NUM, PAL_CPPI41_SR_DOCSIS_TX_US7_DMA3_TX_CH_NUM, /* Reserved */ PAL_CPPI41_SR_RESERVED_DMA3_TX_CH_NUM_8, /* MPEG OUT TX CH*/ PAL_CPPI41_SR_MPEG_OUT_PROGRAM0_DMA3_TX_CH_NUM, PAL_CPPI41_SR_MPEG_OUT_PROGRAM1_DMA3_TX_CH_NUM, PAL_CPPI41_SR_RESERVED_DMA3_TX_CH_NUM_11, /* Infrastructure TX CH */ PAL_CPPI41_SR_HOST_TO_PP_LOW_INFRA_DMA3_TX_CH_NUM, PAL_CPPI41_SR_HOST_TO_PP_HIGH_INFRA_DMA3_TX_CH_NUM, /* Unused infrastructure TX CH */ PAL_CPPI41_SR_RESERVED_INFRA2_DMA3_TX_CH_NUM_14, PAL_CPPI41_SR_RESERVED_INFRA3_DMA3_TX_CH_NUM_15, PAL_CPPI41_SR_RESERVED_INFRA4_DMA3_TX_CH_NUM_16, PAL_CPPI41_SR_RESERVED_INFRA5_DMA3_TX_CH_NUM_17, PAL_CPPI41_SR_RESERVED_INFRA6_DMA3_TX_CH_NUM_18, PAL_CPPI41_SR_RESERVED_INFRA7_DMA3_TX_CH_NUM_19, PAL_CPPI41_SR_RESERVED_INFRA8_DMA3_TX_CH_NUM_20, /* Recycle Infra TX CH */ PAL_CPPI41_SR_RECYCLING_INFRA_DMA3_TX_CH_NUM, PAL_CPPI41_DMA3_MAX_TX_CHANNELS }PAL_CPPI41_SR_DMA3_TX_CHANNELS_e; /* +-+-+-+ +-+ +-+-+ +-+-+-+-+-+-+-+-+ |D|M|A| |3| |R|X| |C|h|a|n|n|e|l|s| +-+-+-+ +-+ +-+-+ +-+-+-+-+-+-+-+-+ */ typedef enum PAL_CPPI41_SR_DMA3_RX_CHANNELS { /* Reserved */ PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_0, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_1, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_2, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_3, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_4, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_5, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_6, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_7, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_8, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_9, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_10, PAL_CPPI41_SR_RESERVED_DMA3_RX_CH_NUM_11, /* Infrastructure TX CH */ PAL_CPPI41_SR_HOST_TO_PP_LOW_INFRA_DMA3_RX_CH_NUM, PAL_CPPI41_SR_HOST_TO_PP_HIGH_INFRA_DMA3_RX_CH_NUM, /* Unused infrastructure TX CH */ PAL_CPPI41_SR_RESERVED_INFRA2_DMA3_RX_CH_NUM_14, PAL_CPPI41_SR_RESERVED_INFRA3_DMA3_RX_CH_NUM_15, PAL_CPPI41_SR_RESERVED_INFRA4_DMA3_RX_CH_NUM_16, PAL_CPPI41_SR_RESERVED_INFRA5_DMA3_RX_CH_NUM_17, PAL_CPPI41_SR_RESERVED_INFRA6_DMA3_RX_CH_NUM_18, PAL_CPPI41_SR_RESERVED_INFRA7_DMA3_RX_CH_NUM_19, PAL_CPPI41_SR_RESERVED_INFRA8_DMA3_RX_CH_NUM_20, /* Recycle Infra RX CH */ PAL_CPPI41_SR_RECYCLING_INFRA_DMA3_RX_CH_NUM, PAL_CPPI41_DMA3_MAX_RX_CHANNELS }PAL_CPPI41_SR_DMA3_RX_CHANNELS_e; #define PAL_CPPI41_SR_CNI_INFRA_DMA_CH_COUNT (PAL_CPPI41_SR_CNI_HIGH_INFRA_DMA2_TX_CH_NUM - PAL_CPPI41_SR_CNI_LOW_INFRA_DMA2_TX_CH_NUM + 1) #define PAL_CPPI41_SR_CNI_INFRA_DMA_CH_NUM(idx) (PAL_CPPI41_SR_CNI_LOW_INFRA_DMA2_TX_CH_NUM + (idx)) #define PAL_CPPI41_SR_DOCSIS_TX_DMA_NUM(idx) (PAL_CPPI41_DMA_BLOCK2 + ((idx)/4)) #define PAL_CPPI41_SR_DOCSIS_TX_DMA_CH_COUNT (8) #define PAL_CPPI41_SR_DOCSIS_TX_DMA_CH_NUM(idx) (PAL_CPPI41_SR_DOCSIS_TX_US0_DMA2_TX_CH_NUM + (idx)) #define PAL_CPPI41_SR_DOCSIS_TX_COP_DMA_TX_CH_NUM (PAL_CPPI41_SR_DOCSIS_TX_COP_DMA2_TX_CH_NUM) #define PAL_CPPI41_SR_DOCSIS_TX_COP_DMA_RX_CH_NUM (PAL_CPPI41_SR_DOCSIS_TX_COP0_DMA2_RX_CH_NUM) #define PAL_CPPI41_SR_HOST_TO_PP_INFRA_DMA_CH_COUNT 2 #define PAL_CPPI41_SR_HOST_TO_PP_INFRA_DMA_CH_NUM(idx) (PAL_CPPI41_SR_HOST_TO_PP_LOW_INFRA_DMA3_TX_CH_NUM + (idx)) #define PAL_CPPI41_SR_L2SW_INFRA_DMA_CH_COUNT (PAL_CPPI41_SR_L2SW_INFRA_DMA2_TX_CH_LAST - PAL_CPPI41_SR_L2SW_INFRA_DMA2_TX_CH_BASE + 1) #define PAL_CPPI41_SR_L2SW_INFRA_DMA_TX_CH_NUM(idx) (PAL_CPPI41_SR_L2SW_INFRA_DMA2_TX_CH_BASE + (idx)) #define PAL_CPPI41_SR_L2SW_INFRA_DMA_RX_CH_NUM(idx) (PAL_CPPI41_SR_L2SW_INFRA_DMA2_RX_CH_BASE + (idx)) /* MPEG OUT TX CH*/ #define PAL_CPPI41_SR_MPEG_OUT_DMA_CH_COUNT 2 #define PAL_CPPI41_SR_MPEG_OUT_DMA_CH_NUM(idx) (PAL_CPPI41_SR_MPEG_OUT_PROGRAM0_DMA3_TX_CH_NUM + (idx)) /********************************************************************************************************************** ### ###### ###### ## ## ## ## ## ## ## ### ######## ####### ######## ## ## ## ## ## ## ## ## ### ### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## #### #### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ### ## ## ## ## ## ## ## ## ## ######## ######### ## ## ## ## ## ## ## ## ## ######### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ###### ###### ####### ## ## ####### ######## ## ## ## ####### ## ## Accumulator Configuration ========================= Channel INTD Usage ------------------------------------------- 0 0 HOST to PP Tx Complete LOW 1 HOST to PP Tx Complete HIGH ------------------------------------------- 2 1 Reserved 3 4 5 ------------------------------------------- 6 2 DOCSIS Management Rx ------------------------------------------- 7 3 L2SW DATA0 Rx ------------------------------------------- 8 4 L2SW MGMT0 Rx ------------------------------------------- 9 5 CNI Low ------------------------------------------- 10 6 CNI High ------------------------------------------- 11 7 ------------------------------------------- 12 8 ------------------------------------------- 13 9 ------------------------------------------- 14 10 Voice DSP Rx ------------------------------------------- 15 11 MPEG Rx ------------------------------------------- 16 12 17 18 19 ------------------------------------------- 20 13 21 22 23 ------------------------------------------- 24 14 25 26 27 ------------------------------------------- 28 15 29 30 31 ------------------------------------------- **********************************************************************************************************************/ /* +-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ |A|c|c|u|m|u|l|a|t|o|r| |C|h|a|n|n|e|l|s| +-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ */ typedef enum PAL_CPPI41_ACCUMULATOR_CHANNELS { PAL_CPPI41_TX_COMPLETE_ACC_CH_BASE, PAL_CPPI41_TX_COMPLETE_LOW_ACC_CH_NUM = PAL_CPPI41_TX_COMPLETE_ACC_CH_BASE, // 0 PAL_CPPI41_TX_COMPLETE_HIGH_ACC_CH_NUM, // 1 PAL_CPPI41_TX_COMPLETE_ACC_CH_LAST = PAL_CPPI41_TX_COMPLETE_HIGH_ACC_CH_NUM, PAL_CPPI41_RESERVED_ACC_CH_NUM_2, // 2 PAL_CPPI41_RESERVED_ACC_CH_NUM_3, // 3 PAL_CPPI41_RESERVED_ACC_CH_NUM_4, // 4 PAL_CPPI41_RESERVED_ACC_CH_NUM_5, // 5 PAL_CPPI41_DOCSIS_RX_MGMT_ACC_CH_NUM, // 6 PAL_CPPI41_L2SW_ACC_CH_BASE, PAL_CPPI41_L2SW_DATA0_ACC_CH_NUM = PAL_CPPI41_L2SW_ACC_CH_BASE, // 7 PAL_CPPI41_L2SW_MGMT0_ACC_CH_NUM, // 8 PAL_CPPI41_L2SW_ACC_CH_LAST = PAL_CPPI41_L2SW_MGMT0_ACC_CH_NUM, PAL_CPPI41_CNI_LOW_ACC_CH_NUM, // 9 PAL_CPPI41_CNI_HIGH_ACC_CH_NUM, // 10 PAL_CPPI41_RESERVED_ACC_CH_NUM_11, // 11 PAL_CPPI41_RESERVED_ACC_CH_NUM_12, // 12 PAL_CPPI41_RESERVED_ACC_CH_NUM_13, // 13 PAL_CPPI41_VOICE_DSP_C55_ACC_RX_CH_NUM, // 14 PAL_CPPI41_MPEG_ACC_RX_CH_NUM, // 15 PAL_CPPI41_ACCUMULATOR_NUM_CHANNELS, PAL_CPPI41_ACCUMULATOR_MAX_CHANNELS = 32 }PAL_CPPI41_ACCUMULATOR_CHANNELS_e; #define PAL_CPPI41_TX_COMPLETE_ACC_CH_NUM(pri) (PAL_CPPI41_TX_COMPLETE_ACC_CH_BASE + (pri)) #define PAL_CPPI41_TX_COMPLETE_ACC_CH_COUNT (PAL_CPPI41_TX_COMPLETE_HIGH_ACC_CH_NUM - PAL_CPPI41_TX_COMPLETE_LOW_ACC_CH_NUM + 1) #define PAL_CPPI41_CNI_ACC_CH_NUM(pri) (PAL_CPPI41_CNI_LOW_ACC_CH_NUM + (pri)) #define PAL_CPPI41_L2SW_ACC_CH_NUM(devInstance) (PAL_CPPI41_L2SW_DATA0_ACC_CH_NUM + (devInstance)) /* +-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+ |A|c|c|u|m|u|l|a|t|o|r| |I|n|t|e|r|r|u|p|t| |V|e|c|t|o|r|s| +-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+ */ typedef enum PAL_CPPI41_ACCUMULATOR_INTERRUPT_VECTORS { PAL_CPPI41_TX_COMPLETE_ACC_INTV_NUM, // 0 PAL_CPPI41_RESERVED_ACC_INTV_NUM_1, // 1 PAL_CPPI41_DOCSIS_RX_MGMT_ACC_INTV_NUM, // 2 PAL_CPPI41_L2SW_ACC_INTV_BASE, PAL_CPPI41_L2SW_DATA0_ACC_INTV_NUM = PAL_CPPI41_L2SW_ACC_INTV_BASE, // 3 PAL_CPPI41_L2SW_MGMT0_ACC_INTV_NUM, // 4 PAL_CPPI41_L2SW_ACC_INTV_LAST = PAL_CPPI41_L2SW_MGMT0_ACC_INTV_NUM, PAL_CPPI41_CNI_LOW_ACC_CH_INTV_NUM, // 5 PAL_CPPI41_CNI_HIGH_ACC_CH_INTV_NUM, // 6 PAL_CPPI41_RESERVED_ACC_INTV_NUM_7, // 7 PAL_CPPI41_RESERVED_ACC_INTV_NUM_8, // 8 PAL_CPPI41_RESERVED_ACC_INTV_NUM_9, // 9 PAL_CPPI41_VOICE_DSP_C55_ACC_RX_INTV_NUM, // 10 PAL_CPPI41_MPEG_ACC_RX_INTV_NUM, // 11 PAL_CPPI41_RESERVED_ACC_INTV_NUM_12, // 12 PAL_CPPI41_RESERVED_ACC_INTV_NUM_13, // 13 PAL_CPPI41_RESERVED_ACC_INTV_NUM_14, // 14 PAL_CPPI41_RESERVED_ACC_INTV_NUM_15, // 15 PAL_CPPI41_ACCUMULATOR_NUM_INTERRUPT_VECTORS, PAL_CPPI41_ACCUMULATOR_MAX_INTERRUPT_VECTORS = 16 }PAL_CPPI41_ACCUMULATOR_INTERRUPT_VECTORS_e; #define PAL_CPPI41_L2SW_ACC_INTV_NUM(devInstance) (PAL_CPPI41_L2SW_ACC_INTV_BASE + (devInstance)) /********************************************************************************************************************** ###### ####### ## ## ######## ###### ######## ######## ####### ######## ######## ###### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ###### ## ## ## ## ######## ## ###### ######## ## ## ######## ## ###### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ###### ####### ####### ## ## ###### ######## ## ####### ## ## ## ###### **********************************************************************************************************************/ typedef enum PAL_CPPI41_SOURCE_PORTS { PAL_CPPI41_SOURCE_PORT_L2SW_DATA0, // 0 PAL_CPPI41_SOURCE_PORT_L2SW_MGMT0, // 1 PAL_CPPI41_RESERVED_SOURCE_PORT_2, // 2 PAL_CPPI41_RESERVED_SOURCE_PORT_3, // 3 PAL_CPPI41_RESERVED_SOURCE_PORT_4, // 4 PAL_CPPI41_RESERVED_SOURCE_PORT_5, // 5 PAL_CPPI41_SOURCE_PORT_DOCSIS, // 6 - HW restriction PAL_CPPI41_SOURCE_PORT_VOICE_DSP_C55, PAL_CPPI41_MAX_SOURCE_PORTS }PAL_CPPI41_SOURCE_PORTS_e; #define CPPI41_SRCPORT_VOICE_DSP_C55 PAL_CPPI41_SOURCE_PORT_VOICE_DSP_C55 /************************************************************************/ /* MPEG definitions - for backward compatible */ /************************************************************************/ #define MPEG_CPPI4x_RX_DMA_CHNUM PAL_CPPI41_SR_RESERVED_DMA01_RX_CH_NUM_9 #define MPEG_BD_SIZE 64 #define MPEG_ENCAP_BD_SIZE 128 #define MPEGOUT_CPPI4x_CHNUM PAL_CPPI41_SR_RESERVED_DMA01_RX_CH_NUM_10 #define DMAC_MPEG_RX_EMBEDDED_BD_NUM 512 #define DMAC_MPEG_ENCAP_RX_EMBEDDED_BD_NUM 256 #define MPEG_CPPI4x_TX_SESSION_QNUM(i) PAL_CPPI41_SR_PrxPDSP_Q_LAST - 1 /************************************************************************/ /* */ /* ____ ____ ____ ____ ____ ____ */ /* / ___| ___| ___| | _ \/ ___|| _ \ */ /* | | |___ \___ \ | | | \___ \| |_) | */ /* | |___ ___) |__) | | |_| |___) | __/ */ /* \____|____/____/ |____/|____/|_| */ /* */ /* */ /************************************************************************/ #define PAL_CPPI41_VOICE_DSP_C55_QMGR PAL_CPPI41_QUEUE_MGR_PARTITION_SR #define PAL_CPPI41_VOICE_DSP_C55_ACC_RX_INTV PAL_CPPI41_VOICE_DSP_C55_ACC_RX_INTV_NUM #define PAL_CPPI41_VOICE_DSP_C55_ACC_RX_CHNUM PAL_CPPI41_VOICE_DSP_C55_ACC_RX_CH_NUM #define PAL_CPPI41_VOICE_DSP_C55_INFRA_CHN PAL_CPPI41_SR_C55_INFRA_DMA2_TX_CH_NUM #define PAL_CPPI41_VOICE_DSP_C55_INFRA_DMA_ID PAL_CPPI41_DMA_BLOCK2 #define PAL_CPPI41_VOICE_DSP_C55_INFRA_QMGR PAL_CPPI41_QUEUE_MGR_PARTITION_SR #define PAL_CPPI41_VOICE_DSP_C55_INFRA_TD_QNUM PAL_CPPI41_SR_DMA_FD_TEARDOWN_Q_NUM #define PAL_CPPI41_VOICE_DSP_C55_INFRA_INPUT_LOW_Q_NUM (PAL_CPPI41_SR_DMA2_C55_INFRA_INPUT_LOW_Q_NUM) #ifdef CONFIG_INTEL_KERNEL_VOICE_SUPPORT #define PAL_CPPI41_VOICE_DSP_C55_EMB_BD_COUNT 256 #define PAL_CPPI41_SR_VOICE_DSP_VNI_FD_EMB_Q_COUNT ((PAL_CPPI41_VOICE_DSP_C55_EMB_BD_COUNT) / 2) #define PAL_CPPI41_SR_VOICE_INFRA_FD_EMB_Q_COUNT ((PAL_CPPI41_VOICE_DSP_C55_EMB_BD_COUNT) / 2) #define PAL_CPPI41_VOICE_DSP_C55_EMB_BD_SIZE 64 #else #define PAL_CPPI41_VOICE_DSP_C55_EMB_BD_COUNT 0 #define PAL_CPPI41_SR_VOICE_DSP_VNI_FD_EMB_Q_COUNT 0 #define PAL_CPPI41_SR_VOICE_INFRA_FD_EMB_Q_COUNT 0 #define PAL_CPPI41_VOICE_DSP_C55_EMB_BD_SIZE 0 #endif #define PAL_CPPI41_VOICE_DSP_C55_INPUT_QNUM PAL_CPPI41_SR_VOICE_DSP_C55_INPUT_Q_NUM #define PAL_CPPI41_VOICE_DSP_C55_HOST_RX_Q_NUM PAL_CPPI41_SR_VOICE_DSP_C55_HOST_RX_Q_NUM #define PAL_CPPI41_VOICE_NI_OUTPUT_QNUM PAL_CPPI41_SR_HOST_TO_QPDSP_EMB_TYPE_Q_NUM(PAL_CPPI4x_PRTY_HIGH) #endif