/* This file is provided under a dual BSD/GPLv2 license. When using or redistributing this file, you may do so under either license. GPL LICENSE SUMMARY Copyright(c) 2011-2018 Intel Corporation. All rights reserved. This program is free software; you can redistribute it and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. The full GNU General Public License is included in this distribution in the file called LICENSE.GPL. Contact Information: Intel Corporation 2200 Mission College Blvd. Santa Clara, CA 97052 BSD LICENSE Copyright(c) 2017 Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef MMC_BP_H #define MMC_BP_H #define BP_DIR_READ 0x0 /* Read direction */ #define BP_DIR_WRITE 0x1 /* Write direction */ #define MMC_BLK_IOCTL_BP_GETINFO 0x8820 /* Get boot partition info */ #define MMC_BLK_IOCTL_BP_RDWR 0x8821 /* Read/write boot partition */ #define MMC_BLK_IOCTL_GP_GETINFO 0x8822 /* Get general purpose partition info */ #define MMC_BLK_IOCTL_GP_RDWR 0x8823 /* Read/write general purpose partition */ #define MMC_BLK_IOCTL_ARB_CMD 0x8830 /* Arbitrary command */ #define MMC_BLK_IOCTL_CARD_INFO 0x8831 /* Get card info, such as RCA */ #define MMC_BLK_IOCTL_CLAIM_HOST 0x8832 /* Claim mmc host device */ #define MMC_BLK_IOCTL_RELEASE_HOST 0x8833 /* Release mmc host device */ #define MMC_BLK_IOCTL_RESET_HOST_CTRL 0x8834 /* Claim mmc host controller */ #define MMC_BLK_IOCTL_SET_IOS_HOST_CTRL 0x8835 /* Set host controller IOS*/ #define MMC_BLK_IOCTL_INIT_CARD 0x8836 /* Release mmc host controller */ /* Standard MMC commands opcodes (5.1) */ /* ------------------------------------ */ /* Basic Commands (class0 and Class1) */ #define MMC_CMD_GO_IDLE_STATE 0 #define MMC_CMD_SEND_OP_COND 1 #define MMC_CMD_ALL_SEND_CID 2 #define MMC_CMD_SET_RELATIVE_ADDR 3 #define MMC_CMD_SET_DSR 4 #define MMC_CMD_SLEEP_AWAKE 5 #define MMC_CMD_SWITCH 6 #define MMC_CMD_SELECT_CARD 7 #define MMC_CMD_SEND_EXT_CSD 8 #define MMC_CMD_SEND_CSD 9 #define MMC_CMD_SEND_CID 10 #define MMC_CMD_STOP_TRANSMISSION 12 #define MMC_CMD_SEND_STATUS 13 #define MMC_CMD_BUS_TEST_R 14 #define MMC_CMD_GO_INACTIVE_STATE 15 #define MMC_CMD_BUS_TEST_W 19 /* Block-oriented read commands (class 2) */ #define MMC_CMD_SET_BLOCKLEN 16 #define MMC_CMD_READ_SINGLE_BLOCK 17 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 #define MMC_CMD_SEND_TUNING_BLOCK 21 /* Block-oriented write commands (class 4) */ #define MMC_CMD_SET_BLOCK_COUNT 23 #define MMC_CMD_WRITE_BLOCK 24 #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 #define MMC_CMD_PROGRAM_CID 26 #define MMC_CMD_PROGRAM_CSD 27 #define MMC_CMD_SET_TIME 49 /* Erase commands (class 5) */ #define MMC_CMD_ERASE_GROUP_START 35 #define MMC_CMD_ERASE_GROUP_END 36 #define MMC_CMD_ERASE 38 /* Block-oriented write protection commands (class 6) */ #define MMC_CMD_SET_WRITE_PROT 28 #define MMC_CMD_CLR_WRITE_PROT 29 #define MMC_CMD_SEND_WRITE_PROT 30 #define MMC_CMD_SEND_WRITE_PROT_TYPE 31 /* Lock Device commands (class 7) */ #define MMC_CMD_LOCK_UNLOCK 42 /* Application-specific commands (class 8) */ #define MMC_CMD_APP_CMD 55 #define MMC_CMD_GEN_CMD 56 /* I/O mode commands (class 9) */ #define MMC_CMD_FAST_IO 39 #define MMC_CMD_GO_IRQ_STATE 40 /* Security Protocols (class 10) */ #define MMC_CMD_PROTOCOL_RD 53 #define MMC_CMD_PROTOCOL_WR 54 /* Command Queue (Class 11) */ #define MMC_CMD_QUEUED_TASK_PARAMS 44 #define MMC_CMD_QUEUED_TASK_ADDRESS 45 #define MMC_CMD_EXECUTE_READ_TASK 46 #define MMC_CMD_EXECUTE_WRITE_TASK 47 #define MMC_CMD_CMDQ_TASK_MGMT 48 #define MMC_CMD_VENDOR_60 60 #define MMC_CMD_VENDOR_61 61 #define MMC_CMD_VENDOR_62 62 #define MMC_CMD_VENDOR_63 63 /* Standard MMC commands Types (5.1) */ /* ------------------------------------ */ #define MMC_CMD_TYPE_AC 0 /* addressed commands */ #define MMC_CMD_TYPE_ADTC 1 /* addressed data transfer commands */ #define MMC_CMD_TYPE_BC 2 /* broadcast commands */ #define MMC_CMD_TYPE_BCR 3 /* broadcast commands with response */ /* Standard MMC Response Types (5.1) */ /* ------------------------------------ */ #define MMC_CMD_RSP_NONE 0 #define MMC_CMD_RSP_R1 1 #define MMC_CMD_RSP_R1B 2 #define MMC_CMD_RSP_R2 3 #define MMC_CMD_RSP_R3 4 #define MMC_CMD_RSP_R4 5 #define MMC_CMD_RSP_R5 6 /* MMC Standard (5.1) - R1 Response Card Status */ /* -------------------------------------------- */ #define R1_STATUS_OUT_OF_RANGE (1 << 31) #define R1_STATUS_ADDRESS_ERROR (1 << 30) #define R1_STATUS_BLOCK_LEN_ERROR (1 << 29) #define R1_STATUS_ERASE_SEQ_ERROR (1 << 28) #define R1_STATUS_ERASE_PARAM (1 << 27) #define R1_STATUS_WP_VIOLATION (1 << 26) #define R1_STATUS_CARD_IS_LOCKED (1 << 25) #define R1_STATUS_LOCK_UNLOCK_FAILED (1 << 24) #define R1_STATUS_COM_CRC_ERROR (1 << 23) #define R1_STATUS_ILLEGAL_COMMAND (1 << 22) #define R1_STATUS_CARD_ECC_FAILED (1 << 21) #define R1_STATUS_CC_ERROR (1 << 20) #define R1_STATUS_ERROR (1 << 19) #define R1_STATUS_UNDERRUN (1 << 18) #define R1_STATUS_OVERRUN (1 << 17) #define R1_STATUS_CID_CSD_OVERWRITE (1 << 16) #define R1_STATUS_WP_ERASE_SKIP (1 << 15) #define R1_STATUS_CARD_ECC_DISABLED (1 << 14) #define R1_STATUS_ERASE_RESET (1 << 13) #define R1_STATUS_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) #define R1_STATUS_STATE_IDLE 0 #define R1_STATUS_STATE_READY 1 #define R1_STATUS_STATE_IDENT 2 #define R1_STATUS_STATE_STBY 3 #define R1_STATUS_STATE_TRAN 4 #define R1_STATUS_STATE_DATA 5 #define R1_STATUS_STATE_RCV 6 #define R1_STATUS_STATE_PRG 7 #define R1_STATUS_STATE_DIS 8 #define R1_STATUS_READY_FOR_DATA (1 << 8) #define R1_STATUS_SWITCH_ERROR (1 << 7) #define R1_STATUS_EXCEPTION_EVENT (1 << 6) #define R1_STATUS_APP_CMD (1 << 5) /* MMC Standard (5.1) - R3 Response OCR Register */ /* -------------------------------------------- */ #define R3_OCR_MMC_CARD_BUSY (1 << 31) /* Card Power up status bit */ /* MMC Standard (5.1) - MMC_SWITCH CMD6 definitions (partial) */ /* -------------------------------------------- --------------*/ // Access Mode #define MMC_SWITCH_ACCESS_MODE_WRITE_BYTE 0x03 // Cmd Set #define MMC_SWITCH_CMD_SET_NORMAL 0 // EXT CSD indexes #define EXT_CSD_IDX_HS_TIMING 185 #define EXT_CSD_IDX_BUS_WIDTH 183 // EXT CSD values #define EXT_CSD_VAL_BUS_WIDTH_8 2 #define EXT_CSD_VAL_HS 1 #define MMC_BP_UNIT_SIZE (128 * 1024) /*Boot partition is an integer multiple of 128 kB in size */ #define MMC_SECTOR_SIZE 512 /*A sector size is 512Byte*/ #define MAX_NUM_OF_SECTORS_ADMA2_PAGE 128 /*Only 128 sectors (64Kb) can be transfered at one ADMA2 page */ #define ADMA2_PAGE_SIZE (MAX_NUM_OF_SECTORS_ADMA2_PAGE * MMC_SECTOR_SIZE) #define MAX_NUM_OF_BOOT_PARTITIONS 1 /*Only 2 boot partitions are supported, partition 0 & partition 1*/ #define MMC_BOOT_EN_USER 0 #define MMC_BOOT_EN_BP0 1 #define MMC_BOOT_EN_BP1 2 #define MMC_BOOT_EN_NONE 3 #define MMC_BOOT_EN_RESV 4 struct mmc_bp_info { unsigned long sectors; unsigned long booten; }; struct mmc_gp_info { unsigned long sectors[4]; }; struct mmc_bp_rw { unsigned char which; unsigned char dir; void *buf; unsigned long st_sector; unsigned long nr_sectors; /* max 128 */ }; struct mmc_card_info { unsigned int rca; unsigned int ocr; }; struct mmc_arb_cmd { unsigned int opcode; /* Command index */ unsigned int arg; /* Command argument */ unsigned int type; /* Command type */ unsigned int rsp; /* Response type */ void *resp; /* Command response, this buffer should be four 32 bits, i.e. 16 bytes */ void *databuf; /* Data buffer for read/write */ unsigned int datalen; /* Data length in byte, should be multiples of 512, max is 64K */ unsigned int datadir; /* Data transfer direction, 0 is read, >0 is write */ unsigned int dataready; /* Whether check for card program finish and ready for data, 0 is not check, >0 is check */ unsigned int stop; /* Whether should issue stop command, 0 is not issue, >0 is issue */ }; struct mmc_host_ctrl_ios { unsigned int ios_op_code; /* clock rate */ #define MMC_HOST_CTRL_IOS_SET_HIGH_SPEED 1 #define MMC_HOST_CTRL_IOS_SET_CLK 2 #define MMC_HOST_CTRL_IOS_SET_BUS_WIDTH 3 unsigned char timing; /* timing specification used */ #define MMC_HOST_CTRL_TIMING_LEGACY 0 #define MMC_HOST_CTRL_TIMING_MMC_HS 1 unsigned int clock; /* clock rate */ #define MMC_HOST_CTRL_MAX_CLK (-1) unsigned char bus_width; /* data bus width */ #define MMC_HOST_CTRL_BUS_WIDTH_1 0 #define MMC_HOST_CTRL_BUS_WIDTH_4 2 #define MMC_HOST_CTRL_BUS_WIDTH_8 3 }; #endif