--- zzzz-none-000/linux-4.9.279/arch/arm/include/asm/memory.h	2021-08-08 06:38:54.000000000 +0000
+++ puma7-arm-6591-750/linux-4.9.279/arch/arm/include/asm/memory.h	2023-02-08 10:58:12.000000000 +0000
@@ -10,6 +10,12 @@
  *
  *  Note: this file should not be included by non-asm/.h files
  */
+
+/*
+ * Includes Intel Corporation's changes/modifications dated: 2017.
+ * Changed/modified portions - Copyright (c) 2017, Intel Corporation.
+ */
+
 #ifndef __ASM_ARM_MEMORY_H
 #define __ASM_ARM_MEMORY_H
 
@@ -132,7 +138,11 @@
  * have CONFIG_ARM_PATCH_PHYS_VIRT. Assembly code must always use
  * PLAT_PHYS_OFFSET and not PHYS_OFFSET.
  */
+#ifdef CONFIG_ARCH_AVALANCHE
+#define PLAT_PHYS_OFFSET        UL(CONFIG_ARM_AVALANCHE_SDRAM_ADDRESS)
+#else
 #define PLAT_PHYS_OFFSET	UL(CONFIG_PHYS_OFFSET)
+#endif
 
 #ifdef CONFIG_XIP_KERNEL
 /*
@@ -168,6 +178,9 @@
  */
 #define __PV_BITS_31_24	0x81000000
 #define __PV_BITS_7_0	0x81
+#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
+#define __PV_BITS_23_16	0x00810000
+#endif
 
 extern unsigned long __pv_phys_pfn_offset;
 extern u64 __pv_offset;
@@ -212,6 +225,9 @@
 
 	if (sizeof(phys_addr_t) == 4) {
 		__pv_stub(x, t, "add", __PV_BITS_31_24);
+#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
+		__pv_stub(t, t, "add", __PV_BITS_23_16);
+#endif
 	} else {
 		__pv_stub_mov_hi(t);
 		__pv_add_carry_stub(x, t);
@@ -230,6 +246,9 @@
 	 * in place where 'r' 32 bit operand is expected.
 	 */
 	__pv_stub((unsigned long) x, t, "sub", __PV_BITS_31_24);
+#ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
+	__pv_stub(t, t, "sub", __PV_BITS_23_16);
+#endif
 	return t;
 }