--- zzzz-none-000/linux-4.9.279/arch/arm/kernel/head.S	2021-08-08 06:38:54.000000000 +0000
+++ puma7-arm-6591-750/linux-4.9.279/arch/arm/kernel/head.S	2023-02-08 10:58:12.000000000 +0000
@@ -11,6 +11,12 @@
  *
  *  Kernel startup code for all 32-bit CPUs
  */
+
+/*
+ * Includes Intel Corporation's changes/modifications dated: 2017.
+ * Changed/modified portions - Copyright (c) 2017, Intel Corporation.
+ */
+
 #include <linux/linkage.h>
 #include <linux/init.h>
 
@@ -616,8 +622,13 @@
 	mov	r0, r8, lsr #PAGE_SHIFT	@ convert to PFN
 	str	r0, [r6]	@ save computed PHYS_OFFSET to __pv_phys_pfn_offset
 	strcc	ip, [r7, #HIGH_OFFSET]	@ save to __pv_offset high bits
+#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
 	mov	r6, r3, lsr #24	@ constant for add/sub instructions
 	teq	r3, r6, lsl #24 @ must be 16MiB aligned
+#else
+	mov	r6, r3, lsr #16	@ constant for add/sub instructions
+	teq	r3, r6, lsl #16	@ must be 64kiB aligned
+#endif
 THUMB(	it	ne		@ cross section branch )
 	bne	__error
 	str	r3, [r7, #LOW_OFFSET]	@ save to __pv_offset low bits
@@ -638,9 +649,14 @@
 	add	r6, r6, r3
 	ldr	r0, [r6, #HIGH_OFFSET]	@ pv_offset high word
 	ldr	r6, [r6, #LOW_OFFSET]	@ pv_offset low word
+#ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
 	mov	r6, r6, lsr #24
 	cmn	r0, #1
+#endif
 #ifdef CONFIG_THUMB2_KERNEL
+# ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
+#  error ARM_PATCH_PHYS_VIRT_16BIT IS NOT TESTED WITH THUMB2 KERNEL
+# endif
 	moveq	r0, #0x200000	@ set bit 21, mov to mvn instruction
 	lsls	r6, #24
 	beq	2f
@@ -673,8 +689,17 @@
 	ldrcc	r7, [r4], #4	@ use branch for delay slot
 	bcc	1b
 	bx	lr
-#else
+#else /* CONFIG_THUMB2_KERNEL */
+# ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
 	moveq	r0, #0x400000	@ set bit 22, mov to mvn instruction
+# else
+#  ifdef CONFIG_CPU_ENDIAN_BE8
+#   error ARM_PATCH_PHYS_VIRT_16BIT IS NOT TESTED WITH ENABLED CONFIG_CPU_ENDIAN_BE8
+#  endif
+	lsr	r0, r6, #16
+	and	r0, r0, #255	@ offset bits 23-16
+	lsr	r6, r6, #24	@ offset bits 31-24
+# endif
 	b	2f
 1:	ldr	ip, [r7, r3]
 #ifdef CONFIG_CPU_ENDIAN_BE8
@@ -686,10 +711,16 @@
 	orreq	ip, ip, r0, ror #8  @ mask in offset bits 7-0
 #else
 	bic	ip, ip, #0x000000ff
+# ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
+	tst	ip, #0x400	@ rotate shift tells us LS or MS byte
+	orrne	ip, ip, r6	@ mask in offset bits 31-24
+	orreq	ip, ip, r0	@ mask in offset bits 23-16
+# else
 	tst	ip, #0xf00	@ check the rotation field
 	orrne	ip, ip, r6	@ mask in offset bits 31-24
 	biceq	ip, ip, #0x400000	@ clear bit 22
 	orreq	ip, ip, r0	@ mask in offset bits 7-0
+# endif
 #endif
 	str	ip, [r7, r3]
 2:	cmp	r4, r5