/* * Copyright (C) 2020-2022 MaxLinear, Inc. * Copyright (C) 2014-2020 Intel Corporation * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2, as published * by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, see http://www.gnu.org/licenses/. * * SPDX-License-Identifier: GPL-2.0-only */ /*! \file puma7_cppi.c \brief Puma-7 CPPI initialization. Contains Puma-7 specific initialization. The numbers (addresses etc) are Puma-7 specific. The static structures are filled in with Puma-6 specific data and the generic CPPI4.1 init function gets called in the end with this data. */ /* This definition must be before include */ #define pr_fmt(fmt) "%s:%u: " fmt, __func__, __LINE__ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "intel_logger.h" #if (!defined(CONFIG_INTEL_KERNEL_PP_DRIVER_LOCAL) && defined(CONFIG_MRPC_CPPI_CLIENT)) #include #include #include #include #include #endif /* CONFIG_CABLE_MPEG_VFE - support in polling mode CONFIG_CABLE_MPEG_VFE_INT_MODE - support in interrupt mode */ #if (defined(CONFIG_CABLE_MPEG_VFE) && defined(CONFIG_CABLE_MPEG_VFE_INT_MODE)) #error "CONFIG_CABLE_MPEG_VFE and CONFIG_CABLE_MPEG_VFE_INT_MODE can't be configure together" #endif #ifdef CPPI4_DEBUG #define CPPI_DBG(fmt, args...) INTEL_DBG_PRINTK("%s:%d " fmt, __FUNCTION__ , __LINE__ , ## args) #define CPPI_ERR(fmt, args...) INTEL_ERR_PRINTK("%s:%d " fmt, __FUNCTION__ , __LINE__ , ## args) #else #define CPPI_DBG(...) no_printk(__VA_ARGS__) /* No debug prints on production image */ #define CPPI_ERR INTEL_ERR_PRINTK #endif #define CPPI_INFO INTEL_INFO_PRINTK static int memProfile = 0; static pal_cppi_dbg_cfg_t puma7_pp_dbg_cfg; static PAL_Result cppi_pp_proc_init (Ptr hnd, Ptr param); static Int32 cppi_init_pp_docsis_ral_and_qsmon(PAL_Handle palHandle); static Int32 cppi_pp_configure_qsmon(PAL_Handle pal_handle, Uint32 manager, qsmonRal_t *qsmon, Bool setCount); static Uint32 cppi_init_pp_buffer_pools(PAL_Handle palHandle); static Int32 cppi_init_pp_dma_channels(PAL_Handle palHandle); /* This CPPI 4.1 global initialization structure. Contains static initialization * information for the whole CPPI subsystem. Details regarding structure fields * can be obtained from PAL documentation. Some comments on how the structure * can be populated/extended are thrown here as well. * * *** IMPORTANT *** *** ALWAYS REMEMBER *** *** FOLLOW THESE RULES *** * * - Keep all base addresses of descriptor regions in ascending order. * Where descriptor is allocated by CPPI from SDRAM, the base here is * specified as zero. Treat the zero as SDRAM base address while ensuring * the ascending order. Keep all desc regiosns meant to be on SDRAM * together. * * - Sort the desc regions defined on SDRAM (base == 0) in descending order of * desc size. This is required to ensure easy alignment (bit 14 aligned to * bit 15 and so on.) * * - Apply these rules to each queue manager in the system *separately*. * * - Read the PAL CPPI documentation (especially the Cppi4InitCfg structure doc) * before starting to modify this structure. * */ static Cppi4InitCfg gCppiDsgInitCfg; Cppi4InitCfg gCppiPpInitCfg; EXPORT_SYMBOL(gCppiPpInitCfg); /*******************/ /* Add Pools names */ /*******************/ #undef PAL_CPPI_BMGR_P_ADD #define PAL_CPPI_BMGR_P_ADD(pName) #pName, Uint8 *PalCppiPpbmgrNames[PAL_CPPI41_BMGR_MAX_POOLS] = { PAL_CPPI_PP_BMGR_POOL_LIST }; EXPORT_SYMBOL(PalCppiPpbmgrNames); /**************/ /* Add Q names*/ /**************/ #undef PAL_CPPI_QMGR_Q_ADD #define PAL_CPPI_QMGR_Q_ADD(qName) "LO." #qName, Uint8 *PalCppiPpLqmgrNames[PAL_CPPI_PP_QMGR_LOCAL_TOTAL_Q_COUNT] = { PAL_CPPI_PP_QMGR_LOCAL_Q_LIST }; EXPORT_SYMBOL(PalCppiPpLqmgrNames); #undef PAL_CPPI_QMGR_Q_ADD #define PAL_CPPI_QMGR_Q_ADD(qName) "G0." #qName, Uint8 *PalCppiPpGqmgr0Names[PAL_CPPI_PP_QMGR_G0_TOTAL_Q_COUNT] = { PAL_CPPI_PP_QMGR_G0_Q_LIST }; EXPORT_SYMBOL(PalCppiPpGqmgr0Names); #undef PAL_CPPI_QMGR_Q_ADD #define PAL_CPPI_QMGR_Q_ADD(qName) "G1." #qName, Uint8 *PalCppiPpGqmgr1Names[PAL_CPPI_PP_QMGR_G1_TOTAL_Q_COUNT] = { PAL_CPPI_PP_QMGR_G1_Q_LIST }; EXPORT_SYMBOL(PalCppiPpGqmgr1Names); #undef PAL_CPPI_QMGR_Q_ADD #define PAL_CPPI_QMGR_Q_ADD(qName) "G2." #qName, Uint8 *PalCppiPpGqmgr2Names[PAL_CPPI_PP_QMGR_G2_TOTAL_Q_COUNT] = { PAL_CPPI_PP_QMGR_G2_Q_LIST }; EXPORT_SYMBOL(PalCppiPpGqmgr2Names); #undef PAL_CPPI_QMGR_Q_ADD #define PAL_CPPI_QMGR_Q_ADD(qName) "DSG0." #qName, Uint8 *PalCppiDsg0qmgrNames[PAL_CPPI_DSG_QMGR_TOTAL_Q_COUNT] = { PAL_CPPI_DSG_QMGR_Q_LIST }; #undef PAL_CPPI_QMGR_Q_ADD #define PAL_CPPI_QMGR_Q_ADD(qName) "DSG1." #qName, Uint8 *PalCppiDsg1qmgrNames[PAL_CPPI_DSG_QMGR_TOTAL_Q_COUNT] = { PAL_CPPI_DSG_QMGR_Q_LIST }; #undef PAL_CPPI_QMGR_Q_ADD #define PAL_CPPI_QMGR_Q_ADD(qName) "DSG2." #qName, Uint8 *PalCppiDsg2qmgrNames[PAL_CPPI_DSG_QMGR_TOTAL_Q_COUNT] = { PAL_CPPI_DSG_QMGR_Q_LIST }; #undef PAL_CPPI_QMGR_Q_ADD Uint32 g_proc_qsm = 1; Uint32 g_threshold_0 = THRESHOLD_0_VALUE; Uint32 g_threshold_1 = THRESHOLD_1_VALUE; /* The previous state of rx dma channels (before disable them). */ static Uint32 g_original_dma_channels_configuration[PAL_CPPI41_NUM_DMA_BLOCK]; /* proc interface */ static PAL_Handle gPpPalHnd; static PAL_Handle gDsgPalHnd; typedef enum { CPPI_POST_INIT_OK, CPPI_POST_INIT_ERR_PAL_HND, CPPI_POST_INIT_ERR_BUFF_INIT, CPPI_POST_INIT_ERR_DMA_CH, CPPI_POST_INIT_ERR_SKB_SH } cppi_post_init_return_error_e; #define DEF_FD_Q(qM, qid, descR, descC, descS, bP, descT, allocT ) \ {.qMgr = qM, .qId = qid, .descRegion = descR, .descCount = descC, .descSize = descS, .bPool = bP, .descType = descT, .allocType = allocT } #define SKB_DESCRIPTOR_BP (PAL_CPPI41_BMGR_MAX_POOLS+1) FDqueue_t gPpFDqueues[] = { /****************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************/ /* QUEUE MANAGER QUEUE ID DESCRIPTOR REGION DESCRIPTOR COUNT DESCRIPTOR SIZE BUFFER POOL DESCRIPTOR TYPE ALLOCATION TYPE */ /****************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************/ DEF_FD_Q( PAL_CPPI_PP_QMGR_LOCAL, PAL_CPPI_PP_QMGR_LOCAL_PP_INTERNAL_EMB_FD_Q_NUM, PAL_CPPI_PP_INTERNAL_EMB_GLOBAL_DESC_REGION, PAL_CPPI_PP_QMGR_LOCAL_PREFETCH_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_LOCAL_PREFETCH_FD_DESC_SIZE, PAL_CPPI41_BMGR_MAX_POOLS, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G1_US_FW_MONO_FD_Q_NUM, PAL_CPPI_PP_US_FW_MONO_DESC_REGION, PAL_CPPI_PP_US_FW_MONO_FD_DESC_COUNT, PAL_CPPI_PP_US_FW_MONO_FD_DESC_SIZE, PAL_CPPI41_BMGR_MAX_POOLS, CPPI41_DESC_TYPE_MONOLITHIC, PAL_CPPI_ALLOC_NONE ), #ifdef CONFIG_IPSEC_SUPPORT // IPSEC on-chip free Q. Descriptors are of type Embedded, but are used as contiguous desc+buffer blocks (as expressed by 2K desc size) DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_IPSEC_MONOLITHIC_FD_Q_NUM, PAL_CPPI_PP_IPSEC_MONOLITHIC_GLOBAL_DESC_REGION, PAL_CPPI_PP_IPSEC_MONOLITHIC_FD_DESC_COUNT, PAL_CPPI_PP_IPSEC_MONOLITHIC_FD_DESC_SIZE, PAL_CPPI41_BMGR_MAX_POOLS, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), // Free Q for descriptors to be used by crypto driver to pass to PP DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_IPSEC_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_IPSEC_HOST_FD_DESC_COUNT, PAL_CPPI_PP_IPSEC_HOST_FD_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), #endif DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DOCSIS_LOW_INFRA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_DOCSIS_LOW_INFRA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DOCSIS_HI_INFRA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_DOCSIS_HI_INFRA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_LOW_INFRA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_SHARED_LOW_INFRA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_SKB ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_ATOM_HI_INFRA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_ATOM_HI_INFRA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_SKB ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII0_HI_INFRA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_RGMII0_HI_INFRA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_SKB ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII1_HI_INFRA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_RGMII1_HI_INFRA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_SKB ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SGMII0_HI_INFRA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_SGMII0_HI_INFRA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_SKB ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SGMII1_HI_INFRA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_SGMII1_HI_INFRA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_SKB ), #ifdef CONFIG_WIFI_PROXY DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_WIFI_INFRA_HOST_RX_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_WIFI_INFRA_HOST_RX_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_SKB ), #endif DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DOCSIS_TX_MGMT_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_DOCSIS_TX_MGMT_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI41_BMGR_MAX_POOLS, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_CALLOC ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_LOW_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_HOST2PP_LOW_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_SKB ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_HI_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_HOST2PP_HI_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_SKB ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION, PAL_CPPI_PP_RX_LOW_SHARED_PACKET_RAM_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_RX_LOW_0_SHARED_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_0_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_RX_LOW_1_SHARED_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_1_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_RX_LOW_XLONG_SHARED_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_4KB_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DOCSIS_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION, PAL_CPPI_PP_DOCSIS_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DOCSIS_DDR_RX_HI_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_DOCSIS_RX_HIGH_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DOCSIS_RX_MGMT_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_DOCSIS_RX_MGMT_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI41_BMGR_MAX_POOLS, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_CALLOC ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_MoCA_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION, PAL_CPPI_PP_MoCA_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), #ifdef CONFIG_WIFI_PROXY DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_WIFI_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION, PAL_CPPI_PP_WIFI_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_WIFI_SHARED_RX_LOW_2KB_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), #endif DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_MoCA_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_MoCA_RX_LOW_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_ATOM_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION, PAL_CPPI_PP_ATOM_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_ATOM_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_ATOM_RX_LOW_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_ATOM_DDR_RX_HIGH_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_ATOM_RX_HIGH_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII0_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION, PAL_CPPI_PP_RGMII0_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII0_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_RGMII0_RX_LOW_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII0_DDR_RX_HIGH_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_RGMII0_RX_HIGH_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII1_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION, PAL_CPPI_PP_RGMII1_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII1_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_RGMII1_RX_LOW_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII1_DDR_RX_HIGH_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_RGMII1_RX_HIGH_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SGMII0_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION, PAL_CPPI_PP_SGMII0_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SGMII0_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_SGMII0_RX_LOW_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SGMII0_DDR_RX_HIGH_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_SGMII0_RX_HIGH_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SGMII1_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION, PAL_CPPI_PP_SGMII1_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SGMII1_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_SGMII1_RX_LOW_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SGMII1_DDR_RX_HIGH_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_SGMII1_RX_HIGH_PRIVATE_DDR_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_INFRA_LOW_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_HOST2PP_LOW_INFRA_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_1_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_INFRA_HIGH_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_HOST2PP_HI_INFRA_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), #ifdef CONFIG_WIFI_PROXY DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_WIFI_SHARED_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_WIFI_FW_RX_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_WIFI_SHARED_RX_LOW_2KB_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_WIFI_FW_RX_REASSEMBLY_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_GLOBAL_DESC_REGION, PAL_CPPI_PP_WIFI_FW_RX_REASSEMBLY_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), #endif #if CONFIG_NP_APP_DATAPIPE DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_NP2APP_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_PPINFO_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_NP2APP_INFRA_PPINFO_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_DATA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_NP2APP_INFRA_DATA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_APP2NP_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_PPINFO_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_APP2NP_INFRA_PPINFO_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_DATA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_APP2NP_INFRA_DATA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_CTRL_PPINFO_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_APP2NP_INFRA_HIGH_PPINFO_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_CTRL_DATA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_APP2NP_INFRA_HIGH_DATA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_CTRL_PPINFO_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_NP2APP_INFRA_HIGH_PPINFO_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_CTRL_DATA_HOST_FD_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_NP2APP_INFRA_HIGH_DATA_HOST_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_NONE ), #endif #ifdef CONFIG_INTEL_KERNEL_VOICE_SUPPORT DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_VOICE_DSP_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_VOICE_GLOBAL_DESC_REGION, PAL_CPPI_PP_VOICE_DSP_RX_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_VOICE_DSP_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_VOICE_INFRA_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_VOICE_GLOBAL_DESC_REGION, PAL_CPPI_PP_VOICE_INFRA_RX_EMB_FD_DESC_COUNT, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE, PAL_CPPI_PP_VOICE_DSP_BUFFER_POOL, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), #endif DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM, PAL_CPPI_PP_TEARDOWN_GLOBAL_DESC_REGION, PAL_CPPI_PP_TEARDOWN_FD_DESC_COUNT, PAL_CPPI_PP_TEARDOWN_FD_DESC_SIZE, PAL_CPPI41_BMGR_MAX_POOLS, CPPI41_DESC_TYPE_TEARDOWN, PAL_CPPI_ALLOC_NONE ), #if (defined(CONFIG_CABLE_MPEG_VFE) || defined(CONFIG_CABLE_MPEG_VFE_INT_MODE)) DEF_FD_Q( PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DS_FW_MPEG_TS_FD_INT_MODE_Q_NUM, PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION, PAL_CPPI_PP_QMGR_DS_FW_MPEG_TS_HOST_DESC_COUNT, PAL_CPPI_PP_QMGR_DS_FW_MPEG_TS_HOST_DESC_SIZE, SKB_DESCRIPTOR_BP, CPPI41_DESC_TYPE_HOST, PAL_CPPI_ALLOC_SKB ) #endif }; EXPORT_SYMBOL(gPpFDqueues); FDqueue_t gDsgFDqueues[] = { /******************************************************************************************************************************************************************************************************************************************************************/ /* QUEUE MANAGER QUEUE ID DESCRIPTOR REGION DESCRIPTOR COUNT DESCRIPTOR SIZE BUFFER POOL DESCRIPTOR TYPE ALLOCATION TYPE */ /******************************************************************************************************************************************************************************************************************************************************************/ DEF_FD_Q( PAL_CPPI_OFDM0_QUEUE_MGR, PAL_CPPI_DSG_QMGR_FD_EMB_Q_NUM, PAL_CPPI_DSG_FD_EMB_DESC_REGION, PAL_CPPI_OFDM0_FD_EMB_DESC_COUNT, PAL_CPPI_DS_DSG_FD_EMB_DESC_SIZE, PAL_CPPI41_BMGR_MAX_POOLS, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_OFDM1_QUEUE_MGR, PAL_CPPI_DSG_QMGR_FD_EMB_Q_NUM, PAL_CPPI_DSG_FD_EMB_DESC_REGION, PAL_CPPI_OFDM1_FD_EMB_DESC_COUNT, PAL_CPPI_DS_DSG_FD_EMB_DESC_SIZE, PAL_CPPI41_BMGR_MAX_POOLS, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ), DEF_FD_Q( PAL_CPPI_SC_QAM0_QUEUE_MGR, PAL_CPPI_DSG_QMGR_FD_EMB_Q_NUM, PAL_CPPI_DSG_FD_EMB_DESC_REGION, PAL_CPPI_SC_QAM0_FD_EMB_DESC_COUNT, PAL_CPPI_DS_DSG_FD_EMB_DESC_SIZE, PAL_CPPI41_BMGR_MAX_POOLS, CPPI41_DESC_TYPE_EMBEDDED, PAL_CPPI_ALLOC_NONE ) }; EXPORT_SYMBOL(gDsgFDqueues); #define DEF_QSM(qsmId, qsmE, qM, qN, dir, qsmTr ) \ {.qsmonThread = qsmId, .qsmonChEn = qsmE, .fdQueue.qMgr = qM, .fdQueue.qNum = qN, .direction = dir, .qsmonThreshold = qsmTr} qsmonRal_t gQsmon1[] = { /*******************************************************************************************************************************************************/ /* QSM_ID ENABLED QUEUE MANAGER QUEUE NUMBER DIRECCION THRESHOLD */ /*******************************************************************************************************************************************************/ DEF_QSM( 0, True, PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G1_RGMII0_TX_HI_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 1, True, PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G1_RGMII1_TX_HI_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 2, True, PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G1_SGMII0_TX_HI_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 3, True, PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G1_SGMII1_TX_HI_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 4, True, PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G1_ATOM_TX_HI_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 5, True, PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G1_MoCA_TX_HI_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), /* ---- DO NOT USE - These threads are dedicated to the runtime configurable QSM ---- */ DEF_QSM( 6, True, PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G1_MoCA_TX_HI_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 7, True, PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G1_MoCA_TX_HI_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 8, True, PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G1_MoCA_TX_HI_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ) /* ---------------------------------------------------------------------------------- */ }; qsmonRal_t gQsmon2[] = { /*******************************************************************************************************************************************************/ /* QSM_ID ENABLED QUEUE MANAGER QUEUE NUMBER DIRECCION THRESHOLD */ /*******************************************************************************************************************************************************/ DEF_QSM( 0, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_RX_LOW_SHARED_PACKET_RAM_EMB_FD_DESC_COUNT ), DEF_QSM( 1, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_RX_LOW_0_SHARED_DDR_EMB_FD_DESC_COUNT ), DEF_QSM( 2, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_RX_LOW_1_SHARED_DDR_EMB_FD_DESC_COUNT ), DEF_QSM( 3, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_TX_COMPLETE_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 4, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_NP2APP_HOST_FD_DESC_COUNT ), DEF_QSM( 5, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_PPINFO_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_NP2APP_INFRA_PPINFO_HOST_FD_DESC_COUNT ), DEF_QSM( 6, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_DATA_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_NP2APP_INFRA_DATA_HOST_FD_DESC_COUNT ), DEF_QSM( 7, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_CTRL_DATA_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_NP2APP_INFRA_HIGH_DATA_HOST_FD_DESC_COUNT ), DEF_QSM( 8, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_APP2NP_HOST_FD_DESC_COUNT ), DEF_QSM( 9, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_PPINFO_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_APP2NP_INFRA_PPINFO_HOST_FD_DESC_COUNT ), DEF_QSM( 10, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_DATA_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_APP2NP_INFRA_DATA_HOST_FD_DESC_COUNT ), DEF_QSM( 11, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_CTRL_DATA_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_APP2NP_INFRA_HIGH_DATA_HOST_FD_DESC_COUNT ), DEF_QSM( 12, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_TX_COMPLETE_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), #ifdef CONFIG_IPSEC_SUPPORT DEF_QSM( 13, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_ENCRYPT_HOST_IN_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 14, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DECRYPT_HOST_IN_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 15, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_IPSEC_MONOLITHIC_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_IPSEC_MONOLITHIC_FD_DESC_COUNT ), DEF_QSM( 16, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_CRYPTO_AES_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 17, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_CRYPTO_HCU_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), #else DEF_QSM( 13, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_MoCA_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_MoCA_RX_LOW_PRIVATE_DDR_EMB_FD_DESC_COUNT ), #ifdef CONFIG_WIFI_PROXY DEF_QSM( 14, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_WIFI_INFRA_HOST_RX_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_WIFI_INFRA_HOST_RX_FD_DESC_COUNT ), DEF_QSM( 15, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_WIFI_SHARED_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_WIFI_FW_RX_EMB_FD_DESC_COUNT ), #endif DEF_QSM( 16, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DOCSIS_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_DOCSIS_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT ), DEF_QSM( 17, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DOCSIS_DDR_RX_HI_EMB_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_DOCSIS_RX_HIGH_PRIVATE_DDR_EMB_FD_DESC_COUNT ), #endif DEF_QSM( 18, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SEQUENCER_LOW_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 19, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SEQUENCER_MED_LOW_Q_NUM, PAL_CPPI_QSMON_DIRECTION_UP, 0 ), DEF_QSM( 20, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DOCSIS_LOW_INFRA_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_DOCSIS_LOW_INFRA_HOST_FD_DESC_COUNT ), DEF_QSM( 21, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_LOW_INFRA_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_SHARED_LOW_INFRA_HOST_FD_DESC_COUNT ), DEF_QSM( 22, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII0_HI_INFRA_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_RGMII0_HI_INFRA_HOST_FD_DESC_COUNT ), DEF_QSM( 23, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII1_HI_INFRA_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_RGMII1_HI_INFRA_HOST_FD_DESC_COUNT ), DEF_QSM( 24, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SGMII0_HI_INFRA_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_SGMII0_HI_INFRA_HOST_FD_DESC_COUNT ), DEF_QSM( 25, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SGMII1_HI_INFRA_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_SGMII1_HI_INFRA_HOST_FD_DESC_COUNT ), DEF_QSM( 26, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_LOW_HOST_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_HOST2PP_LOW_HOST_FD_DESC_COUNT ), DEF_QSM( 27, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_INFRA_LOW_EMB_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_HOST2PP_LOW_INFRA_EMB_FD_DESC_COUNT ), DEF_QSM( 28, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_INFRA_HIGH_EMB_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_HOST2PP_HI_INFRA_EMB_FD_DESC_COUNT ), /* ---- DO NOT USE - These threads are dedicated to the runtime configurable QSM ---- */ DEF_QSM( 29, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_INFRA_HIGH_EMB_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_HOST2PP_HI_INFRA_EMB_FD_DESC_COUNT ), DEF_QSM( 30, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_INFRA_HIGH_EMB_FD_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_HOST2PP_HI_INFRA_EMB_FD_DESC_COUNT ), DEF_QSM( 31, True, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_DS_FW_MPEG_TS_FD_INT_MODE_Q_NUM, PAL_CPPI_QSMON_DIRECTION_DOWN, PAL_CPPI_PP_QMGR_DS_FW_MPEG_TS_HOST_DESC_COUNT ), /* ---------------------------------------------------------------------------------- */ }; /***************************/ /* QSM Configurable queues */ /***************************/ #define QSMON_SIZE(num) (sizeof(gQsmon##num) / sizeof(gQsmon##num[0])) #define QSMON_CONF_MGR_THREADS(num) {QSMON_SIZE(num)-3, QSMON_SIZE(num)-2, QSMON_SIZE(num)-1} #define QSMON_CONF_MAX_THREADS 3 #define QSMON_CONF_HISTORY_NUM_ENTRIES 2 typedef struct { Uint32 qsmonThread; Uint32 qMgr; Uint32 qNum; Bool direction; Uint32 qsmonThreshold; } qsmonConfHistory_t; qsmonConfHistory_t qsmonConfHistory[QSMON_CONF_HISTORY_NUM_ENTRIES]; int qsmonConfThreadNums[2][QSMON_CONF_MAX_THREADS] = { QSMON_CONF_MGR_THREADS(1), QSMON_CONF_MGR_THREADS(2) }; qsmonRal_t gBsmon[PAL_CPPI41_BMGR_MAX_POOLS] = { /**************************************************************************************************************************************************************************************/ /* BSM THREAD ENABLED STATUS MANAGER BUFFER POOL DIRECCION THRESHOLD */ /**************************************************************************************************************************************************************************************/ DEF_QSM( PAL_CPPI_PP_SHARED_RX_LOW_2KB_0_BUFFER_POOL, True , PAL_CPPI_PP_BSMON_MGR, PAL_CPPI_PP_SHARED_RX_LOW_2KB_0_BUFFER_POOL , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // qsmonThreshold initialized runtime DEF_QSM( PAL_CPPI_PP_SHARED_RX_LOW_2KB_1_BUFFER_POOL, True , PAL_CPPI_PP_BSMON_MGR, PAL_CPPI_PP_SHARED_RX_LOW_2KB_1_BUFFER_POOL , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // qsmonThreshold initialized runtime DEF_QSM( PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL, True , PAL_CPPI_PP_BSMON_MGR, PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // qsmonThreshold initialized runtime DEF_QSM( PAL_CPPI_PP_WIFI_SHARED_RX_LOW_2KB_BUFFER_POOL, True , PAL_CPPI_PP_BSMON_MGR, PAL_CPPI_PP_WIFI_SHARED_RX_LOW_2KB_BUFFER_POOL , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // qsmonThreshold initialized runtime DEF_QSM( PAL_CPPI_PP_BUFFER_POOL4, False, PAL_CPPI_PP_BSMON_MGR, PAL_CPPI41_BMGR_MAX_POOLS , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // Disabled, using dummy parameters DEF_QSM( PAL_CPPI_PP_BUFFER_POOL5, False, PAL_CPPI_PP_BSMON_MGR, PAL_CPPI41_BMGR_MAX_POOLS , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // Disabled, using dummy parameters DEF_QSM( PAL_CPPI_PP_BUFFER_POOL6, False, PAL_CPPI_PP_BSMON_MGR, PAL_CPPI41_BMGR_MAX_POOLS , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // Disabled, using dummy parameters DEF_QSM( PAL_CPPI_PP_BUFFER_POOL7, False, PAL_CPPI_PP_BSMON_MGR, PAL_CPPI41_BMGR_MAX_POOLS , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // Disabled, using dummy parameters DEF_QSM( PAL_CPPI_PP_BUFFER_POOL8, False, PAL_CPPI_PP_BSMON_MGR, PAL_CPPI41_BMGR_MAX_POOLS , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // Disabled, using dummy parameters DEF_QSM( PAL_CPPI_PP_SHARED_RX_LOW_4KB_BUFFER_POOL, True , PAL_CPPI_PP_BSMON_MGR, PAL_CPPI_PP_SHARED_RX_LOW_4KB_BUFFER_POOL , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // qsmonThreshold initialized runtime DEF_QSM( PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL, True , PAL_CPPI_PP_BSMON_MGR, PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ), // qsmonThreshold initialized runtime DEF_QSM( PAL_CPPI_PP_VOICE_DSP_BUFFER_POOL, True , PAL_CPPI_PP_BSMON_MGR, PAL_CPPI_PP_VOICE_DSP_BUFFER_POOL , PAL_CPPI_QSMON_DIRECTION_DOWN, 0 ) // qsmonThreshold initialized runtime }; EXPORT_SYMBOL(gBsmon); #define PAL_CPPI_DSG_PSI_SIZE 5 typedef struct { Cppi4EmbdDesc hw; Uint32 psi[PAL_CPPI_DSG_PSI_SIZE]; } DsgCppiDescType_t; /* Docsis DS Co-Processor commands templates Co-Processor command: Word0[31-28] Command index Word0[27-24] Command length Word0[23] Next 0 - indicate last command 1 - indicate there are more commands Word0[22-0] command specific Word1 optional 0x21 - BPI command template, (BPI command id, command length of 1) 0x41 - CRC command template, (CRC command id, command length of 1) 0x11 - PHS command template, (PHS command id, command length of 1) 0x72 - RX command template, (RX command id, command length of 2) */ #define DS_EMBEDDED_DESC_BPI_CMD_TEMPLATE 0x21800000 /* TBD - Idan - please comment how we get to these magic numbers */ #define DS_EMBEDDED_DESC_CRC_CMD_TEMPLATE 0x41800000 #define DS_EMBEDDED_DESC_PHS_CMD_TEMPLATE 0x11800000 #define DS_EMBEDDED_DESC_RX_FIFO_0_CMD_TEMPLATE 0x72000000 #define DS_EMBEDDED_DESC_RX_FIFO_1_CMD_TEMPLATE 0x080404C1 #define DSG_INTERNAL_ADDR_MASK ((Uint32)(1 << 19) - 1) #define DSG_INTERNAL_OFFSET(addr) ((addr) & DSG_INTERNAL_ADDR_MASK) #define GQMGR_MAX_QUEUES(qMgr) \ (qMgr == PAL_CPPI_PP_QMGR_G0 ? PAL_CPPI_PP_QMGR_G0_TOTAL_Q_COUNT : \ (qMgr == PAL_CPPI_PP_QMGR_G1 ? PAL_CPPI_PP_QMGR_G1_TOTAL_Q_COUNT : \ (qMgr == PAL_CPPI_PP_QMGR_G2 ? PAL_CPPI_PP_QMGR_G2_TOTAL_Q_COUNT : \ PAL_CPPI_PP_QMGR_LOCAL_TOTAL_Q_COUNT))) #define CPPI_DESC_TYPE_STR(type) \ (type == CPPI41_DESC_TYPE_EMBEDDED ? "Embedded " : \ (type == CPPI41_DESC_TYPE_HOST ? "Host " : \ (type == CPPI41_DESC_TYPE_MONOLITHIC ? "Monolithic" : \ (type == CPPI41_DESC_TYPE_TEARDOWN ? "Teardown " : \ "Invalid")))) #define IS_DESC_TYPE_VALID(desc) \ ((CPPI41_DESC_TYPE_EMBEDDED <= desc) && (desc <= CPPI41_DESC_TYPE_TEARDOWN)) #define IS_DESC_REGION_VALID(region) \ ((PAL_CPPI_PP_VOICE_GLOBAL_DESC_REGION <= region) && \ (region < PAL_CPPI41_MAX_DESC_REGIONS)) #define IS_QMGR_ID_VALID(qMgr) \ ((PAL_CPPI_PP_QMGR_G0 <= qMgr) && (qMgr < PAL_CPPI41_NUM_QUEUE_MGR)) #define IS_QUEUE_ID_VALID(qId, qMgr) \ ((0 <= qId) && (qId < GQMGR_MAX_QUEUES(qMgr))) #define CPPI_QMGR_MAX_DESC_SUPPORT (64*1024) #if (!defined(CONFIG_INTEL_KERNEL_PP_DRIVER_LOCAL) && defined(CONFIG_MRPC_CPPI_CLIENT)) #define INIT_BUFFER_POOLS_MAX_ITER 250 static void init_buffer_pools(struct work_struct *work); static int init_buffer_pools_iterations; extern Uint32 avalanche_cppi_get_skb_shared_info_size( void ); #endif static Uint32 b_pool_count[PAL_CPPI41_BMGR_MAX_POOLS]; static Uint32 max_b_pool_count[PAL_CPPI41_BMGR_MAX_POOLS] = { 16*1024, // POOL 0 16*1024, // POOL 1 16*1024, // POOL 2 16*1024, // POOL 3 16*1024, // POOL 4 16*1024, // POOL 5 16*1024, // POOL 6 16*1024, // POOL 7 2*1024, // POOL 8 2*1024, // POOL 9 2*1024, // POOL 10 1024}; // POOL 11 static int get_bPool_info(Cppi4Queue *queue, Cppi4BufPool *bufPool) { int i; for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) { if (gPpFDqueues[i].qId == queue->qNum && gPpFDqueues[i].qMgr == queue->qMgr) { bufPool->bMgr = PAL_CPPI_PP_BUF_MGR; // There's only one buffer manager bufPool->bPool = gPpFDqueues[i].bPool; CPPI_DBG("Queue %u.%u uses bPool %u.%u\n", queue->qMgr, queue->qNum, bufPool->bMgr, bufPool->bPool); return 0; } } CPPI_ERR("No bPool assigned to queue %u.%u\n", queue->qMgr, queue->qNum); return 1; } static ssize_t cppi_pp_dump_all_stats(struct seq_file *m, void *v) { PAL_CPPI_PP_QMGRs_e qMgr; Uint16 qNum; Uint16 maxQNum; Cppi4Queue cppiQueue; Uint32 pktCount; Uint32 expectedCount; Uint32 i; for (qMgr = 0; qMgr < PAL_CPPI41_NUM_QUEUE_MGR; qMgr++) { maxQNum = (qMgr == PAL_CPPI_PP_QMGR_G0 ? PAL_CPPI_PP_QMGR_G0_TOTAL_Q_COUNT : (qMgr == PAL_CPPI_PP_QMGR_G1 ? PAL_CPPI_PP_QMGR_G1_TOTAL_Q_COUNT : (qMgr == PAL_CPPI_PP_QMGR_G2 ? PAL_CPPI_PP_QMGR_G2_TOTAL_Q_COUNT : PAL_CPPI_PP_QMGR_LOCAL_TOTAL_Q_COUNT))); for (qNum = 0; qNum < maxQNum; qNum++) { cppiQueue.qMgr = qMgr; cppiQueue.qNum = qNum; PAL_cppi4Control(gPpPalHnd, PAL_CPPI41_IOCTL_GET_QUEUE_ENTRY_COUNT, &cppiQueue, &pktCount); expectedCount = 0; for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) { if (gPpFDqueues[i].qMgr == qMgr && gPpFDqueues[i].qId == qNum) { expectedCount = gPpFDqueues[i].descCount; break; } } if (pktCount != expectedCount) seq_printf(m, "%4d %-65s : %4d [%d]\n", qNum, PAL_CPPI_PP_QMGR_GET_Q_NAME(qMgr, qNum), pktCount, expectedCount); } } return 0; } static int cppi_pp_proc_open(struct inode *inode, struct file *file) { return single_open(file, cppi_pp_dump_all_stats, NULL); } static const struct proc_ops cppi_pp_proc_fops = { .proc_open = cppi_pp_proc_open, .proc_read = seq_read, .proc_lseek = seq_lseek, .proc_release = single_release, }; static ssize_t cppi_qsm_dump(struct seq_file *m, void *v) { CSL_QSMon_RegsOvly qsmon; PAL_CPPI_PP_QSMON_MGRs_e mngr; Uint32 thread; CSL_Reg32 reg; // check if we want to reset counters if (g_proc_qsm == 0) { for (mngr = PAL_CPPI_PP_QSMON_MGR1; mngr <= PAL_CPPI_PP_QSMON_MGR2; mngr++) { qsmon = (Ptr) gCppiPpInitCfg.qsmon[mngr]; for (thread = 0; thread < 32; thread++) { reg = qsmon->Cmds[thread].Register_B; if (reg & (1 << QSMON_CONFIG_MONITORED_QUEUE_EN_SHIFT)) qsmon->Depth[thread].Stats_Qdepth_Watermark = qsmon->Depth[thread].Stats_Qdepth_Cnt; } } // reset the value so that we don't reset counters unless explicitly asked g_proc_qsm = 1; } seq_printf(m, "| QSM | Thread | Queue | Watermark | Current | Min/Max | Qname\n"); seq_printf(m, "|-----|--------|-------|-----------|---------|---------|------\n"); for (mngr = PAL_CPPI_PP_QSMON_MGR1; mngr <= PAL_CPPI_PP_QSMON_MGR2; mngr++) { qsmon = (Ptr) gCppiPpInitCfg.qsmon[mngr]; for (thread = 0; thread < 32; thread++) { reg = qsmon->Cmds[thread].Register_B; if (reg & (1 << QSMON_CONFIG_MONITORED_QUEUE_EN_SHIFT)) seq_printf(m, "| %d | %2d | %d.%3d | %5d | %5d | %s | %s\n", mngr, thread, mngr, (reg & QSMON_CONFIG_MONITORED_QUEUE_NUM_MASK), qsmon->Depth[thread].Stats_Qdepth_Watermark, qsmon->Depth[thread].Stats_Qdepth_Cnt, (reg & (1 << QSMON_CONFIG_MONITORED_QUEUE_DIR_SHIFT)) ? "Min" : "Max", PAL_CPPI_PP_QMGR_GET_Q_NAME(mngr, (reg & QSMON_CONFIG_MONITORED_QUEUE_NUM_MASK))); } } return 0; } static int cppi_qsm_proc_open(struct inode *inode, struct file *file) { return single_open(file, cppi_qsm_dump, NULL); } static ssize_t cppi_qsm_write_proc(struct file *fp, const char __user * buf, size_t count, loff_t *ppos) { unsigned char local_buf[10]; int ret_val = 0; if (count >= 10) { CPPI_ERR("Buffer Overflow\n"); return -EFAULT; } if (copy_from_user(local_buf, buf, count)) return -EFAULT; local_buf[count]='\0'; ret_val = count; // set a global flag to signal to the read proc called later whether we want to reset counters sscanf(local_buf, "%u", &g_proc_qsm); return ret_val; } static const struct proc_ops cppi_qsm_proc_fops = { .proc_open = cppi_qsm_proc_open, .proc_read = seq_read, .proc_lseek = seq_lseek, .proc_release = single_release, .proc_write = cppi_qsm_write_proc }; static ssize_t cppi_qsmcfg_dump(struct seq_file *m, void *v) { Uint32 history_idx; seq_printf(m, "| | QSM | Thread | Queue | Min/Max |\n"); seq_printf(m, "|---------|-----|--------|-------|---------|\n"); for (history_idx = 0; history_idx < QSMON_CONF_HISTORY_NUM_ENTRIES; ++history_idx) { seq_printf(m, "| %s | %d | %2d | %d.%3d | %s |\n", (history_idx ? " NEW " : "DELETED"), qsmonConfHistory[history_idx].qMgr, qsmonConfHistory[history_idx].qsmonThread, qsmonConfHistory[history_idx].qMgr, qsmonConfHistory[history_idx].qNum, qsmonConfHistory[history_idx].direction ? "Min" : "Max"); } return 0; } static int cppi_qsmcfg_proc_open(struct inode *inode, struct file *file) { return single_open(file, cppi_qsmcfg_dump, NULL); } static ssize_t cppi_qsmcfg_write_proc(struct file *fp, const char __user * buf, size_t count, loff_t *ppos) { char *token, *str; char *sep = ", \t."; char buffer[128]; Uint32 qMgr = 0; Uint32 qNum = 0; Uint32 qsmonThreshold = 0; Uint32 qsmonThread; Bool direction = 0; PAL_Handle palHandle; static Uint32 qsmonCurTh[2] = {0}; qsmonRal_t *qsmon; palHandle = PAL_cppi4Init (NULL,(Ptr)CPPI41_DOMAIN_PP); if (palHandle == NULL) { CPPI_ERR("palHandle is NULL\n"); return -1; } if (count >= 10) { CPPI_ERR("Buffer Overflow\n"); return -EFAULT; } if (copy_from_user(buffer, buf, count)) { CPPI_ERR("copy_from_user failed\n"); return -EFAULT; } buffer[count] = '\0'; str = &buffer[0]; // Get qMgr token = strsep(&str, sep); qMgr = (Uint32)simple_strtol(token, NULL, 0); if (qMgr < 1 || qMgr > 2) { CPPI_ERR("Invalid qMgr index %d [valid: 1/2]", qMgr); return -EINVAL; } // Get qNum token = strsep(&str, sep); qNum = (Uint32)simple_strtol(token, NULL, 0); if (qNum < 0 || qNum > 511) { CPPI_ERR("Invalid qNum index %d [valid: 0-511]", qNum); return -EINVAL; } // Get direction token = strsep(&str, sep); direction = (Bool)simple_strtol(token, NULL, 0); if (direction != PAL_CPPI_QSMON_DIRECTION_DOWN && direction != PAL_CPPI_QSMON_DIRECTION_UP) { CPPI_ERR("Invalid direction index %d [valid: 0/1 - UP/DOWN]", direction); return -EINVAL; } switch (qMgr) { case PAL_CPPI_PP_QSMON_MGR1: qsmon = gQsmon1; break; case PAL_CPPI_PP_QSMON_MGR2: qsmon = gQsmon2; break; default: break; } qsmonThread = qsmonConfThreadNums[qMgr - 1][qsmonCurTh[qMgr - 1]]; // For direction DOWN set qsmonThreshold to the number of descriptors in queue if ( PAL_CPPI_QSMON_DIRECTION_DOWN == direction ) { if ( PAL_cppi4QueueGetEntryCount(palHandle, qsmon[qsmonThread].fdQueue, &qsmonThreshold) != PAL_SOK ) { CPPI_ERR("Failed to set qsmonThreshold according to PAL_cppi4QueueGetEntryCount\n\n"); return -EFAULT; } } // Set "DELETED" history entry qsmonConfHistory[0] = (qsmonConfHistory_t){ qsmon[qsmonThread].qsmonThread, qsmon[qsmonThread].fdQueue.qMgr, qsmon[qsmonThread].fdQueue.qNum, qsmon[qsmonThread].direction, qsmon[qsmonThread].qsmonThreshold }; qsmon[qsmonThread].fdQueue.qNum = qNum; qsmon[qsmonThread].direction = direction; qsmon[qsmonThread].qsmonThreshold = qsmonThreshold; if(cppi_pp_configure_qsmon(palHandle, qMgr, &qsmon[qsmonThread], False) != PAL_SOK) { CPPI_ERR("cppi_pp_configure_qsmon Failed\n\n"); return -EFAULT; } if(cppi_pp_configure_qsmon(palHandle, qMgr, &qsmon[qsmonThread], True) != PAL_SOK) { CPPI_ERR("cppi_pp_configure_qsmon Failed\n\n"); return -EFAULT; } // Set "New" history entry qsmonConfHistory[1] = (qsmonConfHistory_t) { qsmonThread, qMgr, qNum, direction, qsmonThreshold }; // Update next thread to be qsmonCurTh[qMgr - 1] = (qsmonCurTh[qMgr - 1] + 1) % QSMON_CONF_MAX_THREADS; return count; } static const struct proc_ops cppi_qsmcfg_proc_fops = { .proc_open = cppi_qsmcfg_proc_open, .proc_read = seq_read, .proc_lseek = seq_lseek, .proc_release = single_release, .proc_write = cppi_qsmcfg_write_proc }; static ssize_t cppi_bsm_dump(struct seq_file *m, void *v) { CSL_QSMon_RegsOvly bsmon; Uint32 i, pool_id, pool_size; CSL_Reg32 reg; seq_printf(m, "| Pool | Watermark | Current | Init | Pool Name |\n"); seq_printf(m, "|------|-----------|-----------|-----------|------------------------------------------------|\n"); bsmon = (Ptr) gCppiPpInitCfg.qsmon[PAL_CPPI_PP_BSMON_MGR]; for (i = 0; i < ARRAY_SIZE(gBsmon); i++) { if (gBsmon[i].qsmonChEn) { reg = bsmon->Cmds[gBsmon[i].qsmonThread].Register_B; pool_size = 0; pool_id = reg & QSMON_CONFIG_MONITORED_QUEUE_NUM_MASK; if (pool_id < PAL_CPPI41_BMGR_MAX_POOLS) pool_size = b_pool_count[pool_id]; else seq_printf(m, "Error: bPool number %d is invalid\n", pool_id); seq_printf(m, "| %2d | %5d | %5d | %5d | %-46s |\n", pool_id, bsmon->Depth[gBsmon[i].qsmonThread].Stats_Qdepth_Watermark, bsmon->Depth[gBsmon[i].qsmonThread].Stats_Qdepth_Cnt, pool_size, PalCppiPpbmgrNames[(reg & QSMON_CONFIG_MONITORED_QUEUE_NUM_MASK)]); } } return 0; } static int cppi_bsm_proc_open(struct inode *inode, struct file *file) { return single_open(file, cppi_bsm_dump, NULL); } static const struct proc_ops cppi_bsm_proc_fops = { .proc_open = cppi_bsm_proc_open, .proc_read = seq_read, .proc_lseek = seq_lseek, .proc_release = single_release, }; static int __get_desc_type(struct seq_file *f, u32 *virt_addr) { u32 dtype, dinfo; dinfo = *(virt_addr); /* get descriptor 1st word */ dtype = dinfo & PAL_CPPI4_HOSTDESC_DESC_TYPE_MASK; dtype = dtype >> PAL_CPPI4_HOSTDESC_DESC_TYPE_SHIFT; if (dtype == PAL_CPPI4_HOSTDESC_DESC_TYPE_HOST) return CPPI41_DESC_TYPE_HOST; if (dtype == PAL_CPPI4_MONODESC_DESC_TYPE_MONO) return CPPI41_DESC_TYPE_MONOLITHIC; if (dtype == PAL_CPPI4_TDDESC_DESC_TYPE_TD) return CPPI41_DESC_TYPE_TEARDOWN; dtype = dinfo & CPPI41_EM_DESCINFO_DTYPE_MASK; dtype = dtype >> CPPI41_EM_DESCINFO_DTYPE_SHIFT; if (dtype == CPPI41_EM_DESCINFO_DTYPE_EMB) return CPPI41_DESC_TYPE_EMBEDDED; return -1; } static int __get_desc_ret_qmgr(struct seq_file *f, void *virt_addr, u32 dtype) { u32 retqmgr, pktinfo; if (dtype == CPPI41_DESC_TYPE_HOST) { Cppi4HostDescLinux *hdesc = (Cppi4HostDescLinux *)virt_addr; pktinfo = hdesc->hw.pktInfo; retqmgr = pktinfo & PAL_CPPI4_HOSTDESC_PKT_RETQMGR_MASK; return retqmgr >> PAL_CPPI4_HOSTDESC_PKT_RETQMGR_SHIFT; } else if (dtype == CPPI41_DESC_TYPE_EMBEDDED) { Cppi4EmbdDescPp* edesc = (Cppi4EmbdDescPp *)virt_addr; pktinfo = edesc->pktInfo; retqmgr = pktinfo & CPPI41_EM_PKTINFO_RETQMGR_MASK; return retqmgr >> CPPI41_EM_PKTINFO_RETQMGR_SHIFT; } else { return -1; } } static int __get_desc_ret_queue(struct seq_file *f, void *virt_addr, u32 dtype) { u32 retq, pktinfo; if (dtype == CPPI41_DESC_TYPE_HOST) { Cppi4HostDescLinux *hdesc = (Cppi4HostDescLinux *)virt_addr; pktinfo = hdesc->hw.pktInfo; retq = pktinfo & PAL_CPPI4_HOSTDESC_PKT_RETQNUM_MASK; return retq >> PAL_CPPI4_HOSTDESC_PKT_RETQNUM_SHIFT; } else if (dtype == CPPI41_DESC_TYPE_EMBEDDED) { Cppi4EmbdDescPp* edesc = (Cppi4EmbdDescPp *)virt_addr; pktinfo = edesc->pktInfo; retq = pktinfo & CPPI41_EM_PKTINFO_RETQ_MASK; return retq >> CPPI41_EM_PKTINFO_RETQ_SHIFT; } else { return -1; } } static int cppi_free_queues_check_dbg(struct seq_file *f) { u32 i, region_desc_cnt[PAL_CPPI41_MAX_DESC_REGIONS] = { 0 }; Cppi4DescReg *region; FDqueue_t *fq; u32 total_desc_num = 0; seq_printf(f, " Verifying all free queues are well configured...\n"); seq_printf(f, "-------------------------------------------------------------------------------------------------------\n"); seq_printf(f, " Queue name | qID | region | count | size | type \n"); seq_printf(f, "-------------------------------------------------------------------------------------------------------\n"); for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) { fq = &gPpFDqueues[i]; if (!IS_QMGR_ID_VALID(fq->qMgr)) { seq_printf(f, " Verification Failed: Config entry %u: queue mgr %u isn't valid\n", i, fq->qMgr); continue; } if (!IS_QUEUE_ID_VALID(fq->qId, fq->qMgr)) { seq_printf(f, " Verification Failed: Config entry %u: queue %u isn't valid\n", i, fq->qId); continue; } if (!IS_DESC_REGION_VALID(fq->descRegion)) { seq_printf(f, " Verification Failed: Config entry %u %s: descRegion %u isn't valid\n", i, PAL_CPPI_PP_QMGR_GET_Q_NAME(fq->qMgr, fq->qId), fq->descRegion); continue; } if (!IS_DESC_TYPE_VALID(fq->descType)) { seq_printf(f, " Verification Failed: Config entry %u %s: descType %u isn't valid\n", i, PAL_CPPI_PP_QMGR_GET_Q_NAME(fq->qMgr, fq->qId), fq->descType); continue; } region = &gCppiPpInitCfg.queueMgrInfo[0].descRegion[fq->descRegion]; if (fq->descSize != region->szDesc) { seq_printf(f, " Verification Failed: Config entry %u %s: descSize %u doesn't match region %u descSize %u\n", i, PAL_CPPI_PP_QMGR_GET_Q_NAME(fq->qMgr, fq->qId), fq->descSize, fq->descRegion, region->szDesc); continue; } seq_printf(f, "%-64s | %3u | %7u| %7u | %4u | %u\n", PAL_CPPI_PP_QMGR_GET_Q_NAME(fq->qMgr, fq->qId), fq->qId, fq->descRegion, fq->descCount, fq->descSize, fq->descType); region_desc_cnt[fq->descRegion] += fq->descCount; } seq_printf(f, "------------------------------------------------------------------------------------------------------\n"); seq_printf(f, " \n Verifying descriptors regions are configured according to the free queues...\n"); for (i = PAL_CPPI_PP_VOICE_GLOBAL_DESC_REGION; i < PAL_CPPI41_MAX_DESC_REGIONS; i++) { region = &gCppiPpInitCfg.queueMgrInfo[0].descRegion[i]; total_desc_num += region->numDesc; seq_printf(f, " Region %2u: desc num %5u, desc size %4u, on %s\n", i, region->numDesc, region->szDesc, region->isOnChip ? "chip" : "ddr"); if (region->numDesc != region_desc_cnt[i]) { seq_printf(f, " Region %u desc count is %u while queues array count is %u\n", i, region->numDesc, region_desc_cnt[i]); } } if (total_desc_num > CPPI_QMGR_MAX_DESC_SUPPORT) { seq_printf(f, " Verification Failed: %u descriptors in the regions exceeds the maximum of %u (delta: %u)\n", total_desc_num, CPPI_QMGR_MAX_DESC_SUPPORT, (total_desc_num - CPPI_QMGR_MAX_DESC_SUPPORT)); return -1; } seq_printf(f, " Total number of descriptors configured to the regions: %u\n", total_desc_num); seq_printf(f, "------------------------------------------------------------------------------------------------------\n"); return 0; } static int cppi_descriptors_check_dbg(struct seq_file *f) { PAL_Cppi4QueueHnd qhnd = NULL; PAL_Handle phnd; void *desc_virt; FDqueue_t *fq; Cppi4Queue retq, qinfo; u32 desc_type, desc_phys, q_desc_num; u32 i; Bool qOk = 1; seq_printf(f, "\n Verifying all descriptors within each free queue...\n"); phnd = PAL_cppi4Init(NULL, CPPI41_DOMAIN_PP); if (!phnd) { seq_printf(f, " Failed to get PP pal handle\n"); return -1; } for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) { fq = &gPpFDqueues[i]; /* check only embedded and host descriptors */ if (gPpFDqueues[i].descType != CPPI41_DESC_TYPE_EMBEDDED && gPpFDqueues[i].descType != CPPI41_DESC_TYPE_HOST) continue; if (!fq->descCount) continue; /* get queue handle */ qinfo.qMgr = fq->qMgr; qinfo.qNum = fq->qId; qhnd = PAL_cppi4QueueOpenNoReset(phnd, qinfo); if (!qhnd) { seq_printf(f, " Failed to get queue %s handle\n", PAL_CPPI_PP_QMGR_GET_Q_NAME(fq->qMgr, fq->qId)); continue; } qOk = 1; PAL_cppi4QueueGetEntryCount(phnd, qinfo, &q_desc_num); seq_printf(f, " Scan Queue %s(%u) (descCount = %u[%u]) .... ", PAL_CPPI_PP_QMGR_GET_Q_NAME(fq->qMgr, fq->qId), fq->qId, q_desc_num, fq->descCount); if (fq->descCount < q_desc_num) { seq_printf(f, "\n Error: number of descriptors (%u) is bigger than initial one (%u)", q_desc_num, fq->descCount); qOk = 0; } while (q_desc_num--) { desc_phys = (u32)PAL_cppi4QueuePop(qhnd); if (!desc_phys) { seq_printf(f, "\n Error: got NULL descriptor"); qOk = 0; break; } if (fq->qId == PAL_CPPI_PP_QMGR_G2_VOICE_DSP_RX_EMB_FD_Q_NUM || fq->qId == PAL_CPPI_PP_QMGR_G2_VOICE_INFRA_RX_EMB_FD_Q_NUM) { desc_virt = (Ptr)avalanche_no_OperSys_memory_phys_to_virt(desc_phys); if (desc_virt == (void*) -1) { seq_printf(f, "\n Error: fail to convert descriptor phy address %#x", desc_phys); PAL_cppi4QueuePush(qhnd, (Ptr)desc_phys, PAL_CPPI4_DESCSIZE_2_QMGRSIZE(fq->descSize), 0); qOk = 0; continue; } } else { desc_virt = PAL_CPPI4_PHYS_2_VIRT(desc_phys); // try ddr if (!virt_addr_valid(desc_virt)) { // not ddr if (IO_PHY_VALID(desc_phys)) // try io { desc_virt = (Ptr)IO_PHY2VIRT(desc_phys); } else { seq_printf(f, "\n Error: fail to convert descriptor phy address %#x", desc_phys); PAL_cppi4QueuePush(qhnd, (Ptr)desc_phys, PAL_CPPI4_DESCSIZE_2_QMGRSIZE(fq->descSize), 0); qOk = 0; continue; } } } desc_type = __get_desc_type(f, desc_virt); if (desc_type == -1) { seq_printf(f, "\n Error: fail to get descriptor %#x type", desc_phys); PAL_cppi4QueuePush(qhnd, (Ptr)desc_phys, PAL_CPPI4_DESCSIZE_2_QMGRSIZE(fq->descSize), 0); qOk = 0; continue; } if (desc_type != fq->descType) { seq_printf(f, "\n Error: found descriptor %#x with wrong type %s(%u), expected %s", desc_phys, CPPI_DESC_TYPE_STR(desc_type), desc_type, CPPI_DESC_TYPE_STR(fq->descType)); qOk = 0; } retq.qMgr = __get_desc_ret_qmgr(f, desc_virt, desc_type); if (!IS_QMGR_ID_VALID(retq.qMgr)) { seq_printf(f, "\n Error: found descriptor %#x with invalid qMgr %u", desc_phys, retq.qMgr); qOk = 0; } retq.qNum = __get_desc_ret_queue(f, desc_virt, desc_type); if (!IS_QUEUE_ID_VALID(retq.qNum, retq.qMgr)) { seq_printf(f, "\n Error: found descriptor %#x with invalid return qId %u", desc_phys, retq.qNum); qOk = 0; } if ((retq.qNum || retq.qMgr) && (retq.qMgr != fq->qMgr || retq.qNum != fq->qId)) { Uint16 qMgr_qId = PAL_CPPI_NETDEV_BUILD_Q_INFO(fq->qMgr, fq->qId); Uint16 ret_qMgr_qId = PAL_CPPI_NETDEV_BUILD_Q_INFO(retq.qMgr, retq.qNum); /* In some cases like the ones which require completion * indication it is expected to find a different retQ than the * queue itself. Do not count those as an error */ if (!((qMgr_qId == PAL_CPPI_NETDEV_BUILD_Q_INFO(PAL_CPPI_PP_QMGR_LOCAL, PAL_CPPI_PP_QMGR_LOCAL_PP_INTERNAL_EMB_FD_Q_NUM)) || (qMgr_qId == PAL_CPPI_NETDEV_BUILD_Q_INFO(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_LOW_HOST_FD_Q_NUM) && ret_qMgr_qId == PAL_CPPI_NETDEV_BUILD_Q_INFO(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_LOW_TX_COMPLETE_Q_NUM)) || (qMgr_qId == PAL_CPPI_NETDEV_BUILD_Q_INFO(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_HI_HOST_FD_Q_NUM) && ret_qMgr_qId == PAL_CPPI_NETDEV_BUILD_Q_INFO(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_HOST2PP_HI_TX_COMPLETE_Q_NUM)) || (qMgr_qId == PAL_CPPI_NETDEV_BUILD_Q_INFO(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_HOST_FD_Q_NUM) && ret_qMgr_qId == PAL_CPPI_NETDEV_BUILD_Q_INFO(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_NP2APP_TX_COMPLETE_Q_NUM)) || (qMgr_qId == PAL_CPPI_NETDEV_BUILD_Q_INFO(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_HOST_FD_Q_NUM) && ret_qMgr_qId == PAL_CPPI_NETDEV_BUILD_Q_INFO(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_APP2NP_TX_COMPLETE_Q_NUM)))) { seq_printf(f, "\n Error: found descriptor %#x from different free queue - %s(%u)", desc_phys, PAL_CPPI_PP_QMGR_GET_Q_NAME(retq.qMgr, retq.qNum), retq.qNum); qOk = 0; } } /* push the descriptor back to the queue */ PAL_cppi4QueuePush(qhnd, (Ptr)desc_phys, PAL_CPPI4_DESCSIZE_2_QMGRSIZE(fq->descSize), 0); } if (qOk) seq_printf(f,"OK \n"); else seq_printf(f,"\n"); } return 0; } static ssize_t cppi_verification_dbg(struct seq_file *f, void *v) { seq_printf(f, " CPPI Sanity Verification Test Start\n"); seq_printf(f, "=========================================\n"); cppi_free_queues_check_dbg(f); cppi_descriptors_check_dbg(f); return 0; } static int cppi_verification_open(struct inode *inode, struct file *file) { return single_open(file, cppi_verification_dbg, NULL); } static const struct proc_ops cppi_verification_fops = { .proc_open = cppi_verification_open, .proc_read = seq_read, .proc_lseek = seq_lseek, .proc_release = single_release, }; /* Post init for atom buffers allocation */ static int cppi_post_init( void ) { PAL_Handle palHandle; Uint32 err; #if (!defined(CONFIG_INTEL_KERNEL_PP_DRIVER_LOCAL) && defined(CONFIG_MRPC_CPPI_CLIENT)) Uint32 skb_shared_info_size; #endif palHandle = PAL_cppi4Init(&gCppiPpInitCfg, CPPI41_DOMAIN_PP); if(palHandle == NULL) { CPPI_ERR("PAL_cppi4Init of CPPI41_DOMAIN_PP failed!\n"); return CPPI_POST_INIT_ERR_PAL_HND; } /************************************************************************/ /*********** Init PP buffer pools used in the system ********************/ /************************************************************************/ err = cppi_init_pp_buffer_pools(palHandle); if (err) { CPPI_DBG("PAL_cppi4BufPoolInit for pool %d [CPPI41_DOMAIN_PP] FAILED\n", err-1); return CPPI_POST_INIT_ERR_BUFF_INIT; } #if (!defined(CONFIG_INTEL_KERNEL_PP_DRIVER_LOCAL) && defined(CONFIG_MRPC_CPPI_CLIENT)) /*************************************************************/ /************ Get skb_shared_info size from ATOM ************/ /*************************************************************/ skb_shared_info_size = avalanche_cppi_get_skb_shared_info_size(); if (!skb_shared_info_size) { CPPI_ERR("avalanche_cppi_get_skb_shared_info_size [CPPI41_DOMAIN_PP] FAILED\n"); return CPPI_POST_INIT_ERR_SKB_SH; } g_threshold_0 = PAL_CPPI_PP_SHARED_RX_LOW_2KB_BUFFER_SIZE - PAL_CPPI_PP_START_OF_PACKET_OFFSET - skb_shared_info_size; g_threshold_1 = PAL_CPPI_PP_SHARED_RX_LOW_2KB_BUFFER_SIZE - PAL_CPPI_PP_START_OF_PACKET_OFFSET - skb_shared_info_size; CPPI_DBG("avalanche_cppi_get_skb_shared_info_size: g_threshold_0 = %d\n", g_threshold_0); #endif /******************************************/ /*********** Setup DMA channels ***********/ /******************************************/ if (cppi_init_pp_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } #ifdef CONFIG_MRPC_HANDSHAKE_SERVER boot_status_report(HANDSHAKE_ID_CPPI); #endif return CPPI_POST_INIT_OK; } static PAL_Result cppi_pp_proc_init(Ptr hnd, Ptr param) { struct proc_dir_entry * dir_1 = (struct proc_dir_entry *)param; struct proc_dir_entry * dir_2 = NULL; gPpPalHnd = (PAL_Handle)hnd; puma7_pp_dbg_cfg.handle = (PAL_Handle)hnd; puma7_pp_dbg_cfg.allocQueue.qNum = -1; puma7_pp_dbg_cfg.allocBuf.bPool = -1; puma7_pp_dbg_cfg.outputQueue.qNum = -1; puma7_pp_dbg_cfg.dataLen = 0; /* CPPI production API */ if (NULL == (dir_1 = proc_mkdir("sr", dir_1))) { CPPI_ERR("....\n"); return -1; } if (NULL == (dir_2 = proc_mkdir("stats", dir_1))) { CPPI_ERR("....\n"); return -1; } if (NULL == proc_create("pmInfo", 0, dir_1, &PAL_cppi4PM_fops)) { CPPI_ERR("....\n"); return -1; } if (NULL == proc_create("bsm" , 0, dir_1, &cppi_bsm_proc_fops)) { CPPI_ERR("....\n"); return -1; } if (NULL == proc_create("all" , 0, dir_2, &cppi_pp_proc_fops)) { CPPI_ERR("....\n"); return -1; } /* CPPI debug API */ #ifdef CONFIG_CPPI_DEBUG_API if (NULL == proc_create_data("dbg" , 0, dir_1, &PAL_cppi4dbg_fops, (void *)&puma7_pp_dbg_cfg)) { CPPI_ERR("....\n"); return -1; } if (NULL == proc_create_data("dbgCfg" ,0, dir_1, &PAL_cppi4dbgCfg_fops, (void *)&puma7_pp_dbg_cfg)) { CPPI_ERR("....\n"); return -1; } if (NULL == proc_create ("qsm" , 0, dir_1, &cppi_qsm_proc_fops)) { CPPI_ERR("....\n"); return -1; } if (NULL == proc_create ("qsmcfg" ,0, dir_1, &cppi_qsmcfg_proc_fops)) { CPPI_ERR("....\n"); return -1; } if (NULL == proc_create ("verifyCppiSanity", 0, dir_1, &cppi_verification_fops)) { CPPI_ERR("....\n"); return -1; } #endif return (0); } int cppi_dsg_dump_all_stats(struct seq_file *m, void *v) { PAL_CPPI_DSG_QUEUE_MNGRS_e qMgr = (PAL_CPPI_DSG_QUEUE_MNGRS_e)m->private; Uint16 qNum; Cppi4Queue cppiQueue; Uint32 pktCount; Uint32 expectedCount; Uint32 i; for (qNum = 0; qNum < PAL_CPPI_DSG_QMGR_TOTAL_Q_COUNT; qNum++) { cppiQueue.qMgr = qMgr; cppiQueue.qNum = qNum; PAL_cppi4Control(gDsgPalHnd, PAL_CPPI41_IOCTL_GET_QUEUE_ENTRY_COUNT, &cppiQueue, &pktCount); expectedCount = 0; for (i = 0; i < ARRAY_SIZE(gDsgFDqueues); i++) { if (gDsgFDqueues[i].qMgr == qMgr && gDsgFDqueues[i].qId == qNum) { expectedCount = gDsgFDqueues[i].descCount; break; } } if (pktCount != expectedCount) seq_printf(m, "%4d %-65s : %4d [%d]\n", qNum, PAL_CPPI_DSG_QMGR_GET_Q_NAME(qMgr, qNum), pktCount, expectedCount); } return (0); } static int cppi_dsg_proc_open(struct inode *inode, struct file *file) { return single_open(file, cppi_dsg_dump_all_stats, PDE_DATA(file_inode(file))); } static const struct proc_ops cppi_dsg_proc_fops = { .proc_open = cppi_dsg_proc_open, .proc_read = seq_read, .proc_lseek = seq_lseek, .proc_release = single_release, }; static struct proc_dir_entry *dir_main; #ifdef CONFIG_CPPI_DEBUG_API static PAL_Result cppi_dsg_proc_init(Ptr hnd, Ptr param) { struct proc_dir_entry *dir_1; gDsgPalHnd = (PAL_Handle)hnd; dir_1 = (struct proc_dir_entry *)param; dir_main = dir_1; if (NULL == (dir_1 = proc_mkdir("dsg0", dir_1))) { CPPI_ERR("....\n"); return -1; } if (NULL == (dir_1 = proc_mkdir("stats", dir_1))) { CPPI_ERR("....\n"); return -1; } if (NULL == proc_create_data("all", 0, dir_1, &cppi_dsg_proc_fops, (void *)0 )) { CPPI_ERR("....\n"); return -1; } dir_1 = (struct proc_dir_entry *)param; if (NULL == (dir_1 = proc_mkdir("dsg1", dir_1))) { CPPI_ERR("....\n"); return -1; } if (NULL == (dir_1 = proc_mkdir("stats", dir_1))) { CPPI_ERR("....\n"); return -1; } if (NULL == proc_create_data("all", 0, dir_1, &cppi_dsg_proc_fops, (void *)1 )) { CPPI_ERR("....\n"); return -1; } dir_1 = (struct proc_dir_entry *)param; if (NULL == (dir_1 = proc_mkdir("dsg2", dir_1))) { CPPI_ERR("....\n"); return -1; } if (NULL == (dir_1 = proc_mkdir("stats", dir_1))) { CPPI_ERR("....\n"); return -1; } if (NULL == proc_create_data("all", 0, dir_1, &cppi_dsg_proc_fops, (void *)2 )) { CPPI_ERR("....\n"); return -1; } return (0); } #endif void Puma_DOCSIS_CPPI_exit(void) { remove_proc_entry("dsg0/stats/all", dir_main); remove_proc_entry("dsg1/stats/all", dir_main); remove_proc_entry("dsg2/stats/all", dir_main); } EXPORT_SYMBOL(Puma_DOCSIS_CPPI_exit); static void cppi_init_pp_queue_managers(void) { /* LQMGR */ gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].queueMgrRgnBase = (Ptr) PAL_CPPI_PP_QMGR_LOCAL_REGS_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].descMemRgnBase = (Ptr) PAL_CPPI_PP_QMGR_LOCAL_DESC_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].queueMgmtRgnBase = (Ptr) PAL_CPPI_PP_QMGR_LOCAL_QUEUES_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].queueStatusRgnBase = (Ptr) PAL_CPPI_PP_QMGR_LOCAL_Q_STATS_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].queueProxyRgnBase = NULL; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].totalQNum = PAL_CPPI_PP_QMGR_LOCAL_TOTAL_Q_COUNT; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].LinkingRAM0Base = PAL_CPPI_PP_QMGR_LOCAL_LINKING_RAM_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].LinkingRAM0Size = PAL_CPPI_PP_QMGR_LOCAL_LINKING_RAM_SIZE; /* GQMGR0 */ gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G0].queueMgrRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G0_REGS_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G0].descMemRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G0_DESC_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G0].queueMgmtRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G0_QUEUES_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G0].queueStatusRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G0_Q_STATS_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G0].queueProxyRgnBase = NULL; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G0].totalQNum = PAL_CPPI_PP_QMGR_G0_TOTAL_Q_COUNT; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G0].LinkingRAM0Base = PAL_CPPI_PP_QMGR_GLOBAL_LINKING_RAM_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G0].LinkingRAM0Size = PAL_CPPI_PP_QMGR_GLOBAL_LINKING_RAM_SIZE; /* GQMGR1 */ gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G1].queueMgrRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G1_REGS_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G1].descMemRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G1_DESC_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G1].queueMgmtRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G1_QUEUES_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G1].queueStatusRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G1_Q_STATS_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G1].queueProxyRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G1_Q_PROXY_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G1].totalQNum = PAL_CPPI_PP_QMGR_G1_TOTAL_Q_COUNT; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G1].LinkingRAM0Base = PAL_CPPI_PP_QMGR_GLOBAL_LINKING_RAM_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G1].LinkingRAM0Size = PAL_CPPI_PP_QMGR_GLOBAL_LINKING_RAM_SIZE; /* GQMGR2 */ gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G2].queueMgrRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G2_REGS_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G2].descMemRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G2_DESC_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G2].queueMgmtRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G2_QUEUES_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G2].queueStatusRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G2_Q_STATS_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G2].queueProxyRgnBase = (Ptr) PAL_CPPI_PP_QMGR_G2_Q_PROXY_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G2].totalQNum = PAL_CPPI_PP_QMGR_G2_TOTAL_Q_COUNT; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G2].LinkingRAM0Base = PAL_CPPI_PP_QMGR_GLOBAL_LINKING_RAM_BASE; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_G2].LinkingRAM0Size = PAL_CPPI_PP_QMGR_GLOBAL_LINKING_RAM_SIZE; } void cppi_init_pp_queue_status_monitors_managers(void) { gCppiPpInitCfg.qsmon[PAL_CPPI_PP_QSMON_MGR0] = (CSL_QSMon_RegsOvly)PAL_CPPI_QSMON_0_CTRL_REGS_BASE; gCppiPpInitCfg.qsmon[PAL_CPPI_PP_QSMON_MGR1] = (CSL_QSMon_RegsOvly)PAL_CPPI_QSMON_1_CTRL_REGS_BASE; gCppiPpInitCfg.qsmon[PAL_CPPI_PP_QSMON_MGR2] = (CSL_QSMon_RegsOvly)PAL_CPPI_QSMON_2_CTRL_REGS_BASE; gCppiPpInitCfg.qsmon[PAL_CPPI_PP_QSMON_MGR3] = (CSL_QSMon_RegsOvly)PAL_CPPI_QSMON_3_CTRL_REGS_BASE; gCppiPpInitCfg.qsmon[PAL_CPPI_PP_QSMON_MGR4] = (CSL_QSMon_RegsOvly)PAL_CPPI_QSMON_4_CTRL_REGS_BASE; gCppiPpInitCfg.qsmon[PAL_CPPI_PP_BSMON_MGR] = (CSL_QSMon_RegsOvly)PAL_CPPI_BSMON_CTRL_REGS_BASE; } static int cppi_desc_regions_check(void) { u32 total_desc_num = 0; u32 i; /* Note: Check only queue manager 0 as all queue managers share the same configuration */ for (i = PAL_CPPI_PP_VOICE_GLOBAL_DESC_REGION; i < PAL_CPPI41_MAX_DESC_REGIONS; i++) { total_desc_num += gCppiPpInitCfg.queueMgrInfo[0].descRegion[i].numDesc; /* debug prints */ CPPI_INFO("Region %2u: desc num %5u, desc size %4u, on %s\n", i, gCppiPpInitCfg.queueMgrInfo[0].descRegion[i].numDesc, gCppiPpInitCfg.queueMgrInfo[0].descRegion[i].szDesc, gCppiPpInitCfg.queueMgrInfo[0].descRegion[i].isOnChip ? "chip" : "ddr"); } if (total_desc_num > CPPI_QMGR_MAX_DESC_SUPPORT) { CPPI_ERR("CPPI regions cfg error: total number of descriptors %u exceeds the maximum of %u (delta: %u)\n", total_desc_num, CPPI_QMGR_MAX_DESC_SUPPORT, (total_desc_num - CPPI_QMGR_MAX_DESC_SUPPORT)); return -1; } return 0; } static int cppi_free_queues_check(void) { u32 i; FDqueue_t *fq; for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) { fq = &gPpFDqueues[i]; if (!IS_QMGR_ID_VALID(fq->qMgr)) { CPPI_ERR("Config entry %u: queue mgr %u isn't valid\n", i, fq->qMgr); return -EINVAL; } if (!IS_QUEUE_ID_VALID(fq->qId, fq->qMgr)) { CPPI_ERR("Config entry %u: queue %u isn't valid\n", i, fq->qId); return -EINVAL; } if (!IS_DESC_REGION_VALID(fq->descRegion)) { CPPI_ERR("Config entry %u %s: descRegion %u isn't valid\n", i, PAL_CPPI_PP_QMGR_GET_Q_NAME(fq->qMgr, fq->qId), fq->descRegion); return -EINVAL; } if (!IS_DESC_TYPE_VALID(fq->descType)) { CPPI_ERR("Config entry %u %s: descType %u isn't valid\n", i, PAL_CPPI_PP_QMGR_GET_Q_NAME(fq->qMgr, fq->qId), fq->descType); return -EINVAL; } if (fq->qMgr != PAL_CPPI_PP_QMGR_LOCAL && fq->descSize != gCppiPpInitCfg.queueMgrInfo[fq->qMgr].descRegion[fq->descRegion].szDesc && IS_QMGR_ID_VALID(fq->qMgr) && IS_DESC_REGION_VALID(fq->descRegion)) { CPPI_ERR("Config entry %u %s: descSize %u doesn't match region %u descSize %u\n", i, PAL_CPPI_PP_QMGR_GET_Q_NAME(fq->qMgr, fq->qId), fq->descSize, fq->descRegion, gCppiPpInitCfg.queueMgrInfo[fq->qMgr].descRegion[fq->descRegion].szDesc); return -EINVAL; } /* debug prints */ CPPI_INFO("Region %2u, count %5u, size %3u, type %u, %s[%u]\n", fq->descRegion, fq->descCount, fq->descSize, fq->descType, PAL_CPPI_PP_QMGR_GET_Q_NAME(fq->qMgr, fq->qId), fq->qId); } return 0; } static int cppi_verification(void) { int ret; ret = cppi_desc_regions_check(); ret |= cppi_free_queues_check(); return ret; } static Int32 cppi_init_pp_descriptor_regions(void) { Uint32 i, j; #ifdef CONFIG_INTEL_KERNEL_VOICE_SUPPORT Uint32 *voicePoolPhysAddr; if (avalanche_alloc_no_OperSys_memory(eNO_OperSys_VoiceNI, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE * PAL_CPPI_PP_VOICE_DSP_C55_EMB_BD_COUNT, (Uint32 *)&voicePoolPhysAddr) != 0) { CPPI_ERR("avalanche_alloc_no_OperSys_memory for voice descriptors failed\n"); return -1; } #endif /* LQMGR */ gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].descRegion[PAL_CPPI_PP_INTERNAL_EMB_LOCAL_DESC_REGION].isOnChip = 1; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].descRegion[PAL_CPPI_PP_INTERNAL_EMB_LOCAL_DESC_REGION].base = (Ptr) IO_VIRT2PHY(PAL_CPPI_PP_QMGR_LOCAL_PREFETCH_FD_BASE); gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].descRegion[PAL_CPPI_PP_INTERNAL_EMB_LOCAL_DESC_REGION].numDesc = PAL_CPPI_PP_QMGR_LOCAL_PREFETCH_FD_DESC_COUNT; gCppiPpInitCfg.queueMgrInfo[PAL_CPPI_PP_QMGR_LOCAL].descRegion[PAL_CPPI_PP_INTERNAL_EMB_LOCAL_DESC_REGION].szDesc = PAL_CPPI_PP_QMGR_LOCAL_PREFETCH_FD_DESC_SIZE; /* GQMGRs */ for (i = PAL_CPPI_PP_QMGR_G0; i <= PAL_CPPI_PP_QMGR_G2; i++) { /* Internal emb global*/ gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_INTERNAL_EMB_GLOBAL_DESC_REGION].isOnChip = 1; gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_INTERNAL_EMB_GLOBAL_DESC_REGION].base = (Ptr) IO_VIRT2PHY(PAL_CPPI_PP_QMGR_LOCAL_PREFETCH_FD_BASE); gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_INTERNAL_EMB_GLOBAL_DESC_REGION].szDesc = PAL_CPPI_PP_QMGR_LOCAL_PREFETCH_FD_DESC_SIZE; /* IPSEC Monolithic */ gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_IPSEC_MONOLITHIC_GLOBAL_DESC_REGION].isOnChip = 1; gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_IPSEC_MONOLITHIC_GLOBAL_DESC_REGION].base = (Ptr)IO_VIRT2PHY(PAL_CPPI_PP_IPSEC_MONOLITHIC_FD_BASE); gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_IPSEC_MONOLITHIC_GLOBAL_DESC_REGION].szDesc = PAL_CPPI_PP_IPSEC_MONOLITHIC_FD_DESC_SIZE; /* Packet RAM */ gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION].isOnChip = 1; gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION].base = (Ptr) IO_VIRT2PHY( PAL_CPPI_PP_PACKET_RAM_SHARED_FD_BASE ); gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION].szDesc = PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE; /* US FW */ gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_US_FW_MONO_DESC_REGION].isOnChip = 1; gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_US_FW_MONO_DESC_REGION].base = (Ptr) IO_VIRT2PHY( PAL_CPPI_PP_US_FW_MONO_FD_BASE ); gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_US_FW_MONO_DESC_REGION].szDesc = PAL_CPPI_PP_US_FW_MONO_FD_DESC_SIZE; /* Rx Global*/ gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_RX_GLOBAL_DESC_REGION].isOnChip = 0; gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_RX_GLOBAL_DESC_REGION].szDesc = PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE; /* RX Short + Non DOCSIS Infrastructures */ gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION].isOnChip = 0; gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION].szDesc = PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE; /* Teardown */ gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_TEARDOWN_GLOBAL_DESC_REGION].isOnChip = 0; gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_TEARDOWN_GLOBAL_DESC_REGION].szDesc = PAL_CPPI_PP_TEARDOWN_FD_DESC_SIZE; #ifdef CONFIG_INTEL_KERNEL_VOICE_SUPPORT /* VOICE DSP */ gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_VOICE_GLOBAL_DESC_REGION].isOnChip = 0; gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_VOICE_GLOBAL_DESC_REGION].base = voicePoolPhysAddr; gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_VOICE_GLOBAL_DESC_REGION].szDesc = PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE; gCppiPpInitCfg.queueMgrInfo[i].descRegion[PAL_CPPI_PP_VOICE_GLOBAL_DESC_REGION].isPreAllocated = True; #endif } /* Calculate total number of descriptors for each region */ for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) for (j = PAL_CPPI_PP_QMGR_G0; j <= PAL_CPPI_PP_QMGR_G2; j++) gCppiPpInitCfg.queueMgrInfo[j].descRegion[gPpFDqueues[i].descRegion].numDesc += gPpFDqueues[i].descCount; return 0; } static void cppi_init_pp_dmas(void) { Uint32 i; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA00_OFDM0_RX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA00_OFDM0_RX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA00_OFDM0_RX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA00_OFDM0_RX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA00_OFDM0_RX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA00_OFDM0_RX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA00_OFDM0_RX].ralCtrlBase = (Ptr) PAL_CPPI_PP_DMA00_OFDM0_RX_RAL_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA00_OFDM0_RX].schedParams.portNum = PAL_CPPI_PP_OFDM0_RX_SOURCE_PORT; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA00_OFDM0_RX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA00_OFDM0_RX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA00_OFDM0_RX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA01_OFDM1_RX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA01_OFDM1_RX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA01_OFDM1_RX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA01_OFDM1_RX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA01_OFDM1_RX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA01_OFDM1_RX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA01_OFDM1_RX].ralCtrlBase = (Ptr) PAL_CPPI_PP_DMA01_OFDM1_RX_RAL_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA01_OFDM1_RX].schedParams.portNum = PAL_CPPI_PP_OFDM1_RX_SOURCE_PORT; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA01_OFDM1_RX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA01_OFDM1_RX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA01_OFDM1_RX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA02_SC_QAM_RX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA02_SC_QAM_RX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA02_SC_QAM_RX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA02_SC_QAM_RX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA02_SC_QAM_RX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA02_SC_QAM_RX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA02_SC_QAM_RX].ralCtrlBase = (Ptr) PAL_CPPI_PP_DMA02_SC_QAM_RX_RAL_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA02_SC_QAM_RX].schedParams.portNum = PAL_CPPI_PP_SC_QAM_RX_SOURCE_PORT; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA02_SC_QAM_RX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA02_SC_QAM_RX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA02_SC_QAM_RX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA03_SGMII0_RX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA03_SGMII0_RX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA03_SGMII0_RX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA03_SGMII0_RX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA03_SGMII0_RX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA03_SGMII0_RX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA03_SGMII0_RX].ralCtrlBase = (Ptr) PAL_CPPI_PP_DMA03_SGMII0_RX_RAL_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA03_SGMII0_RX].schedParams.portNum = PAL_CPPI_PP_SGMII0_RX_SOURCE_PORT; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA03_SGMII0_RX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA03_SGMII0_RX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA03_SGMII0_RX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA04_SGMII1_RX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA04_SGMII1_RX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA04_SGMII1_RX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA04_SGMII1_RX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA04_SGMII1_RX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA04_SGMII1_RX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA04_SGMII1_RX].ralCtrlBase = (Ptr) PAL_CPPI_PP_DMA04_SGMII1_RX_RAL_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA04_SGMII1_RX].schedParams.portNum = PAL_CPPI_PP_SGMII1_RX_SOURCE_PORT; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA04_SGMII1_RX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA04_SGMII1_RX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA04_SGMII1_RX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA05_RGMII0_RX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA05_RGMII0_RX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA05_RGMII0_RX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA05_RGMII0_RX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA05_RGMII0_RX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA05_RGMII0_RX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA05_RGMII0_RX].ralCtrlBase = (Ptr) PAL_CPPI_PP_DMA05_RGMII0_RX_RAL_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA05_RGMII0_RX].schedParams.portNum = PAL_CPPI_PP_RGMII0_RX_SOURCE_PORT; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA05_RGMII0_RX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA05_RGMII0_RX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA05_RGMII0_RX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA06_MoCA_RX_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA06_MoCA_RX_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA06_MoCA_RX_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA06_MoCA_RX_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA06_MoCA_RX_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA06_MoCA_RX_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA06_MoCA_RX_TX].ralCtrlBase = (Ptr) PAL_CPPI_PP_DMA06_MoCA_RX_RAL_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA06_MoCA_RX_TX].schedParams.portNum = PAL_CPPI_PP_MoCA_RX_SOURCE_PORT; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA06_MoCA_RX_TX].schedParams.noRecycleOnTx = 1; /* For MoCA, we do not want the CDMA to do any recycling */ gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA06_MoCA_RX_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA06_MoCA_RX_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA06_MoCA_RX_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA07_ATOM_RX_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA07_ATOM_RX_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA07_ATOM_RX_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA07_ATOM_RX_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA07_ATOM_RX_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA07_ATOM_RX_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA07_ATOM_RX_TX].ralCtrlBase = (Ptr) PAL_CPPI_PP_DMA07_ATOM_RX_RAL_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA07_ATOM_RX_TX].schedParams.portNum = PAL_CPPI_PP_ATOM_RX_SOURCE_PORT; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA07_ATOM_RX_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA07_ATOM_RX_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA07_ATOM_RX_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA09_INFRA_RX_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA09_INFRA_RX_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA09_INFRA_RX_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA09_INFRA_RX_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA09_INFRA_RX_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA09_INFRA_RX_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA09_INFRA_RX_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA09_INFRA_RX_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA09_INFRA_RX_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA10_INFRA_RX_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA10_INFRA_RX_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA10_INFRA_RX_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA10_INFRA_RX_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA10_INFRA_RX_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA10_INFRA_RX_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA10_INFRA_RX_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA10_INFRA_RX_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA10_INFRA_RX_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA11_INFRA_RX_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA11_INFRA_RX_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA11_INFRA_RX_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA11_INFRA_RX_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA11_INFRA_RX_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA11_INFRA_RX_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA11_INFRA_RX_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA11_INFRA_RX_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA11_INFRA_RX_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA12_OFDM0_TX_QAM_0_3_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA12_OFDM0_TX_QAM_0_3_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA12_OFDM0_TX_QAM_0_3_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA12_OFDM0_TX_QAM_0_3_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA12_OFDM0_TX_QAM_0_3_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA12_OFDM0_TX_QAM_0_3_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA12_OFDM0_TX_QAM_0_3_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA12_OFDM0_TX_QAM_0_3_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA12_OFDM0_TX_QAM_0_3_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA13_OFDM1_TX_QAM_4_7_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA13_OFDM1_TX_QAM_4_7_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA13_OFDM1_TX_QAM_4_7_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA13_OFDM1_TX_QAM_4_7_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA13_OFDM1_TX_QAM_4_7_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA13_OFDM1_TX_QAM_4_7_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA13_OFDM1_TX_QAM_4_7_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA13_OFDM1_TX_QAM_4_7_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA13_OFDM1_TX_QAM_4_7_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA14_SGMII0_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA14_SGMII0_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA14_SGMII0_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA14_SGMII0_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA14_SGMII0_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA14_SGMII0_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA14_SGMII0_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA14_SGMII0_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA14_SGMII0_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA15_SGMII1_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA15_SGMII1_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA15_SGMII1_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA15_SGMII1_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA15_SGMII1_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA15_SGMII1_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA15_SGMII1_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA15_SGMII1_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA15_SGMII1_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA16_RGMII0_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA16_RGMII0_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA16_RGMII0_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA16_RGMII0_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA16_RGMII0_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA16_RGMII0_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA16_RGMII0_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA16_RGMII0_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA16_RGMII0_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA21_US_COP_RX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA21_US_COP_RX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA21_US_COP_RX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA21_US_COP_RX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA21_US_COP_RX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA21_US_COP_RX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA21_US_COP_RX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA21_US_COP_RX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA21_US_COP_RX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA22_US_COP_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA22_US_COP_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA22_US_COP_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA22_US_COP_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA22_US_COP_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA22_US_COP_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA22_US_COP_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA22_US_COP_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA22_US_COP_TX].channelsState = 0; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA23_RGMII1_RX_TX].globalCtrlBase = (Ptr) PAL_CPPI_PP_DMA23_RGMII1_RX_TX_GLOBAL_CTRL_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA23_RGMII1_RX_TX].chCtrlStatusBase = (Ptr) PAL_CPPI_PP_DMA23_RGMII1_RX_TX_CH_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA23_RGMII1_RX_TX].schedCtrlBase = (Ptr) PAL_CPPI_PP_DMA23_RGMII1_RX_TX_SCHEDULER_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA23_RGMII1_RX_TX].ralCtrlBase = (Ptr) PAL_CPPI_PP_DMA23_RGMII1_RX_RAL_CFG_BASE; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA23_RGMII1_RX_TX].schedParams.portNum = PAL_CPPI_PP_RGMII1_RX_SOURCE_PORT; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA23_RGMII1_RX_TX].schedParams.channelArbitrationMode = DMA_SCHED_CTRL_CHANNEL_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA23_RGMII1_RX_TX].schedParams.rxTxArbitrationMode = DMA_SCHED_CTRL_RX_TX_ARBITRATION_RR; gCppiPpInitCfg.dmaBlock[PAL_CPPI_PP_DMA23_RGMII1_RX_TX].channelsState = 0; for (i = 0; i < PAL_CPPI41_NUM_DMA_BLOCK; i++) { gCppiPpInitCfg.dmaBlock[i].tdFQueue.qMgr = PAL_CPPI_PP_QMGR_G2; gCppiPpInitCfg.dmaBlock[i].tdFQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; } } static Uint32 cppi_init_pp_buffer_pools(PAL_Handle palHandle) { Cppi4BufPool tmpBufPool; tmpBufPool.bMgr = PAL_CPPI_PP_BUF_MGR; tmpBufPool.bPool = PAL_CPPI_PP_SHARED_RX_LOW_2KB_0_BUFFER_POOL; if(NULL == PAL_cppi4BufPoolInit(palHandle, tmpBufPool, PAL_CPPI_PP_SHARED_RX_LOW_2KB_BUFFER_REF_CNT, PAL_CPPI_PP_SHARED_RX_LOW_2KB_BUFFER_SIZE, b_pool_count[PAL_CPPI_PP_SHARED_RX_LOW_2KB_0_BUFFER_POOL])) return (tmpBufPool.bPool + 1); tmpBufPool.bPool = PAL_CPPI_PP_SHARED_RX_LOW_2KB_1_BUFFER_POOL; if(NULL == PAL_cppi4BufPoolInit(palHandle, tmpBufPool, PAL_CPPI_PP_SHARED_RX_LOW_2KB_BUFFER_REF_CNT, PAL_CPPI_PP_SHARED_RX_LOW_2KB_BUFFER_SIZE, b_pool_count[PAL_CPPI_PP_SHARED_RX_LOW_2KB_1_BUFFER_POOL])) return (tmpBufPool.bPool + 1); tmpBufPool.bPool = PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL; if(NULL == PAL_cppi4BufPoolInit(palHandle, tmpBufPool, PAL_CPPI_PP_SHARED_RX_LOW_2KB_BUFFER_REF_CNT, PAL_CPPI_PP_SHARED_RX_LOW_2KB_BUFFER_SIZE, b_pool_count[PAL_CPPI_PP_SHARED_RX_LOW_2KB_2_BUFFER_POOL])) return (tmpBufPool.bPool + 1); #if (!defined(CONFIG_INTEL_KERNEL_PP_DRIVER_LOCAL) && defined(CONFIG_MRPC_CPPI_CLIENT)) tmpBufPool.bPool = PAL_CPPI_PP_WIFI_SHARED_RX_LOW_2KB_BUFFER_POOL; if(NULL == PAL_cppi4BufPoolInit(palHandle, tmpBufPool, PAL_CPPI_PP_WIFI_RX_POOL_REF_CNT, PAL_CPPI_PP_WIFI_RX_POOL_BUFFER_SIZE, b_pool_count[PAL_CPPI_PP_WIFI_SHARED_RX_LOW_2KB_BUFFER_POOL])) return (tmpBufPool.bPool + 1); #endif tmpBufPool.bPool = PAL_CPPI_PP_SHARED_RX_LOW_4KB_BUFFER_POOL; if(NULL == PAL_cppi4BufPoolInit(palHandle, tmpBufPool, PAL_CPPI_PP_SHARED_RX_LOW_4KB_BUFFER_REF_CNT, PAL_CPPI_PP_SHARED_RX_LOW_4KB_BUFFER_SIZE, b_pool_count[PAL_CPPI_PP_SHARED_RX_LOW_4KB_BUFFER_POOL])) return (tmpBufPool.bPool + 1); tmpBufPool.bPool = PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL; if(NULL == PAL_cppi4BufPoolInit(palHandle, tmpBufPool, PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_REF_CNT, PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_SIZE, b_pool_count[PAL_CPPI_PP_SHARED_RX_HIGH_BUFFER_POOL])) return (tmpBufPool.bPool + 1); return 0; } u32 cppi_get_pp_free_queues_count(void) { return ARRAY_SIZE(gPpFDqueues); } u32 cppi_get_pp_free_queue_info(u32 idx, FDqueue_t *info) { if (!info) return EFAULT; if (ARRAY_SIZE(gPpFDqueues) <= idx) return EINVAL; memcpy (info, &gPpFDqueues[idx], sizeof(*info)); return 0; } #ifdef CONFIG_AVM_CPPI_DEBUG static void print_FDqueue_info(FDqueue_t *fdq, Ptr start, Ptr phys, Ptr mem, size_t memsize) { Ptr end = start + fdq->descCount * fdq->descSize; char *dtype = "???"; char *atype = "???"; switch (fdq->descType) { case CPPI41_DESC_TYPE_EMBEDDED: dtype = "EMB"; break; case CPPI41_DESC_TYPE_HOST: dtype = "HOST"; break; case CPPI41_DESC_TYPE_MONOLITHIC: dtype = "MONO"; break; case CPPI41_DESC_TYPE_TEARDOWN: dtype = "TEARDOWN"; break; } switch (fdq->allocType) { case PAL_CPPI_ALLOC_NONE: atype = "NONE"; break; case PAL_CPPI_ALLOC_CALLOC: atype = "CALLOC"; break; case PAL_CPPI_ALLOC_MALLOC: atype = "MALLOC"; break; case PAL_CPPI_ALLOC_SKB: atype = "SKB"; break; } if (mem) { pr_info("CPPI: G%u.%-3u %-8s region %2u: %8lx-%8lx (phys %8lu) %5u %-8s mem %8lx-%8lx size %u\n", (unsigned)fdq->qMgr, (unsigned)fdq->qId, dtype, (unsigned)fdq->descRegion, (unsigned long)start, (unsigned long)end, (unsigned long)phys, (unsigned)fdq->descCount, atype, (unsigned long)mem, (unsigned long)(mem + fdq->descCount * memsize), (unsigned)memsize); } else { pr_info("CPPI: G%u.%-3u %-8s region %2u: %8lx-%8lx (phys %8lu) %5u %-8s\n", (unsigned)fdq->qMgr, (unsigned)fdq->qId, dtype, (unsigned)fdq->descRegion, (unsigned long)start, (unsigned long)end, (unsigned long)phys, (unsigned)fdq->descCount, atype); } } #endif u32 cppi_get_pp_desc_region_info(u32 idx, Cppi4DescReg *region_info) { if (!region_info) return EFAULT; if (!IS_DESC_REGION_VALID(idx)) return EINVAL; memcpy (region_info, &gCppiPpInitCfg.queueMgrInfo[0].descRegion[idx], sizeof(*region_info)); return 0; } int cppi_get_pp_free_queue_info_according_to_q_manager_and_num(Cppi4Queue* q, FDqueue_t *info) { int i; if (!q) return -EFAULT; for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) { if ((gPpFDqueues[i].qId == q->qNum) && (gPpFDqueues[i].qMgr == q->qMgr)) { memcpy (info, &gPpFDqueues[i], sizeof(*info)); return 0; } } return -EINVAL; } EXPORT_SYMBOL(cppi_get_pp_free_queue_info_according_to_q_manager_and_num); u32 cppi_get_buffer_pool_bsmon_info(u32 idx, qsmonRal_t *info) { if (!info) return EFAULT; if (ARRAY_SIZE(gBsmon) <= idx) return EINVAL; memcpy (info, &gBsmon[idx], sizeof(*info)); return 0; } /************************************************************************** * FUNCTION NAME : static PAL_Cppi4QueueHnd get_queue_handle( * PAL_Handle pal_handle, Uint32 qMgr, Uint32 qNum) ************************************************************************** * DESCRIPTION : * This function is called to open cppi queue and return a handle to it. **************************************************************************/ static inline PAL_Cppi4QueueHnd get_queue_handle(PAL_Handle pal_handle, Uint32 qMgr, Uint32 qNum) { Cppi4Queue tmpQ = { .qMgr = qMgr, .qNum = qNum }; PAL_Cppi4QueueHnd queue_handle = PAL_cppi4QueueOpen(pal_handle, tmpQ); if (!queue_handle) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return NULL; } return queue_handle; } /************************************************************************** * FUNCTION NAME : static int setup_pp_internal_descriptors( * PAL_Handle palHandle, FDqueue_t free_queue) ************************************************************************** * DESCRIPTION : * This function is called to give descriptors to PP freeeee queues. **************************************************************************/ static int setup_pp_internal_descriptors(PAL_Handle palHandle, FDqueue_t* free_queue) { PAL_Cppi4QueueHnd tmpQHnd; Uint32 currDesc = (Uint32)PAL_CPPI_PP_QMGR_LOCAL_PREFETCH_FD_BASE; Uint32 descriptorsCount; /* PAL_CPPI_PP_INTERNAL_EMB_GLOBAL_DESC_REGION */ if (free_queue->descRegion == PAL_CPPI_PP_INTERNAL_EMB_GLOBAL_DESC_REGION) { tmpQHnd = get_queue_handle(palHandle, free_queue->qMgr, free_queue->qId); if (!tmpQHnd) return -1; CPPI_DBG("Initialization of Free Descriptors for PAL_CPPI_PP_QMGR_LOCAL_PP_INTERNAL_EMB_FD_Q_NUM Q[%d]Mgr[%d]," "base address = 0x%X (PHY: 0x%0X), descCount = %d\n", free_queue->qId, free_queue->qMgr, currDesc, IO_VIRT2PHY((Uint32)currDesc), free_queue->descCount); #ifdef CONFIG_AVM_CPPI_DEBUG print_FDqueue_info(free_queue, (Ptr)currDesc, (Ptr)IO_VIRT2PHY(currDesc), NULL, 0); #endif for (descriptorsCount = 0; descriptorsCount < free_queue->descCount; descriptorsCount++) { PAL_cppi4QueuePush(tmpQHnd, (Ptr)IO_VIRT2PHY((Uint32)currDesc), 0, 0); currDesc += free_queue->descSize; } } return 0; } static Int32 cppi_init_pp_free_q_descriptors(PAL_Handle palHandle) { Uint32 i; #ifdef CONFIG_WIFI_PROXY Cppi4Queue tmpQ; #endif PAL_Cppi4QueueHnd tmpQHnd; Uint32 descCount; void* currDescRegionPtr[PAL_CPPI41_MAX_DESC_REGIONS]; /* Reset descriptors region array. */ memset(currDescRegionPtr, 0, sizeof(currDescRegionPtr)); /* Go over all free decriptors queues list */ for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) { /************************************************************/ /*********** Setup PP Internal descriptors ******************/ /************************************************************/ if (setup_pp_internal_descriptors(palHandle, &gPpFDqueues[i]) < 0) return -1; /********************************************************************************/ /*********** Setup Packet RAM descriptors & Shared descriptors ******************/ /********************************************************************************/ else if (gPpFDqueues[i].descRegion == PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION || gPpFDqueues[i].descRegion == PAL_CPPI_PP_RX_GLOBAL_DESC_REGION || gPpFDqueues[i].descRegion == PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION || gPpFDqueues[i].descRegion == PAL_CPPI_PP_TEARDOWN_GLOBAL_DESC_REGION) { if (PAL_cppi4IsDescRegionAllocated(palHandle, gPpFDqueues[i].qMgr, gPpFDqueues[i].descRegion) == False) { /* This is the first queue within this region - allocate all the region now */ currDescRegionPtr[gPpFDqueues[i].descRegion] = PAL_cppi4AllocDescRegion(palHandle, gPpFDqueues[i].qMgr, gPpFDqueues[i].descRegion); if (currDescRegionPtr[gPpFDqueues[i].descRegion] == NULL) { CPPI_ERR("Descriptor region %d allocation FAILED\n", gPpFDqueues[i].descRegion); return -1; } /* if region memory is on chip */ if (gCppiPpInitCfg.queueMgrInfo[gPpFDqueues[i].qMgr].descRegion[gPpFDqueues[i].descRegion].isOnChip) currDescRegionPtr[gPpFDqueues[i].descRegion] = (Ptr)IO_PHY2VIRT(currDescRegionPtr[gPpFDqueues[i].descRegion]); descCount = gCppiPpInitCfg.queueMgrInfo[gPpFDqueues[i].qMgr].descRegion[gPpFDqueues[i].descRegion].numDesc; PAL_osMemSet(currDescRegionPtr[gPpFDqueues[i].descRegion], 0, descCount * gPpFDqueues[i].descSize); CPPI_DBG("Descriptor region %d allocation, base address = %p, descCount = %d\n", gPpFDqueues[i].descRegion, currDescRegionPtr[gPpFDqueues[i].descRegion], descCount); } tmpQHnd = get_queue_handle(palHandle, gPpFDqueues[i].qMgr, gPpFDqueues[i].qId); if (!tmpQHnd) return -1; CPPI_DBG("Initialization of Free Descriptors Q[%d]Mgr[%d], base address = %p, descCount = %d\n", gPpFDqueues[i].qId, gPpFDqueues[i].qMgr, currDescRegionPtr[gPpFDqueues[i].descRegion], gPpFDqueues[i].descCount); if (gPpFDqueues[i].descType == CPPI41_DESC_TYPE_EMBEDDED) { #ifdef CONFIG_AVM_CPPI_DEBUG FDqueue_t *fdq = &gPpFDqueues[i]; /* * condition copied from * *** Setup Packet RAM descriptors & Shared descriptors *** * please check it, when using new SDK. * * 2018-06-04, calle */ if (gPpFDqueues[i].descRegion == PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION || gPpFDqueues[i].descRegion == PAL_CPPI_PP_RX_GLOBAL_DESC_REGION || gPpFDqueues[i].descRegion == PAL_CPPI_PP_RX_INFRA_HOST_GLOBAL_DESC_REGION || gPpFDqueues[i].descRegion == PAL_CPPI_PP_TEARDOWN_GLOBAL_DESC_REGION) { print_FDqueue_info(fdq, currDescRegionPtr[fdq->descRegion], (Ptr)IO_VIRT2PHY(currDescRegionPtr[fdq->descRegion]), NULL, 0); } else { print_FDqueue_info(fdq, currDescRegionPtr[fdq->descRegion], (Ptr)PAL_CPPI4_VIRT_2_PHYS(currDescRegionPtr[fdq->descRegion]), NULL, 0); } #endif for (descCount = 0; descCount < gPpFDqueues[i].descCount; descCount++) { Cppi4EmbdDescPp* currDesc = NULL; if(NULL == currDescRegionPtr[gPpFDqueues[i].descRegion]) { CPPI_ERR("Cppi4EmbdDescPp region %d FAILED\n", gPpFDqueues[i].descRegion); return -1; } currDesc = (Cppi4EmbdDescPp*)currDescRegionPtr[gPpFDqueues[i].descRegion]; currDesc->descInfo = CPPI41_EM_DESCINFO_DTYPE_EMBEDDED | CPPI41_EM_DESCINFO_SLOTCNT_PP; currDesc->tagInfo = 0x3FFF; currDesc->pktInfo = (PAL_CPPI4_HOSTDESC_PKT_TYPE_ETH << CPPI41_EM_PKTINFO_PKTTYPE_SHIFT) | (PAL_CPPI4_HOSTDESC_PKT_RETPLCY_UNLINKED << CPPI41_EM_PKTINFO_RETPOLICY_SHIFT) | (gPpFDqueues[i].qMgr << CPPI41_EM_PKTINFO_RETQMGR_SHIFT) | (gPpFDqueues[i].qId << CPPI41_EM_PKTINFO_RETQ_SHIFT); PAL_CPPI4_CACHE_WRITEBACK(currDesc, gPpFDqueues[i].descSize); if (gPpFDqueues[i].descRegion == PAL_CPPI_PP_PACKET_RAM_GLOBAL_DESC_REGION) PAL_cppi4QueuePush(tmpQHnd, (Ptr)IO_VIRT2PHY((Uint32)currDesc), PAL_CPPI4_DESCSIZE_2_QMGRSIZE(gPpFDqueues[i].descSize), 0); else PAL_cppi4QueuePush(tmpQHnd, (Ptr)PAL_CPPI4_VIRT_2_PHYS((Uint32)currDesc), PAL_CPPI4_DESCSIZE_2_QMGRSIZE(gPpFDqueues[i].descSize), 0); currDescRegionPtr[gPpFDqueues[i].descRegion] = (Ptr)((Uint32)currDescRegionPtr[gPpFDqueues[i].descRegion] + gPpFDqueues[i].descSize); } } else if (gPpFDqueues[i].descType == CPPI41_DESC_TYPE_HOST) { Ptr currBuffer = NULL; Uint32 bufferSize = PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_BUFF_SIZE; Uint32 descPktType = PAL_CPPI4_HOSTDESC_PKT_TYPE_ETH; Uint32 tag = 0x3FFF; if ((gPpFDqueues[i].qId == PAL_CPPI_PP_QMGR_G2_DS_FW_MPEG_TS_FD_INT_MODE_Q_NUM)) { bufferSize = PAL_CPPI_PP_QMGR_GLOBAL_MPEG_BUFF_SIZE; descPktType = PAL_CPPI4_HOSTDESC_PKT_TYPE_MPEG; tag = ( (PAL_CPPI_PP_DMA02_SC_QAM_RX << PAL_CPPI4_HOSTDESC_DESC_TYPE_SHIFT) | (PAL_CPPI_PP_DMA_DOCSIS_RX_CH_DS_FW_MPEG_TS_DDR << CPPI41_EM_TAGINFO_SRCCHN_SHIFT) | (0x3FFF << PAL_CPPI4_HOSTDESC_PKT_LEN_SHIFT) ); } if (PAL_CPPI_ALLOC_CALLOC == gPpFDqueues[i].allocType) { if (PAL_osMemAlloc(0, gPpFDqueues[i].descCount * bufferSize, 0, (Ptr *)&currBuffer) != PAL_SOK) { CPPI_ERR("Failed to allocate memory for Management buffer queue\n"); return -1; } PAL_osMemSet(currBuffer, 0, gPpFDqueues[i].descCount * bufferSize); } #if !defined(CONFIG_INTEL_KERNEL_PP_DRIVER_LOCAL) if (PAL_CPPI_ALLOC_SKB == gPpFDqueues[i].allocType) { // Cancel the SKB allocation incase PP is not here. gPpFDqueues[i].allocType = PAL_CPPI_ALLOC_NONE; } #endif #ifdef CONFIG_AVM_CPPI_DEBUG { FDqueue_t *fdq = &gPpFDqueues[i]; print_FDqueue_info(fdq, currDescRegionPtr[fdq->descRegion], (Ptr)PAL_CPPI4_VIRT_2_PHYS(currDescRegionPtr[fdq->descRegion]), currBuffer, PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_BUFF_SIZE); } #endif for (descCount = 0; descCount < gPpFDqueues[i].descCount; descCount++) { Cppi4HostDescLinux* currDesc = NULL; if(NULL == currDescRegionPtr[gPpFDqueues[i].descRegion]) { CPPI_ERR("HostDescLinux region %d FAILED\n", gPpFDqueues[i].descRegion); if (currBuffer != NULL) { PAL_osMemFree(0, currBuffer, gPpFDqueues[i].descCount * bufferSize); currBuffer = NULL; } return -1; } currDesc = (Cppi4HostDescLinux*)currDescRegionPtr[gPpFDqueues[i].descRegion]; currDesc->hw.descInfo = PAL_CPPI4_HOSTDESC_DESC_TYPE_HOST << PAL_CPPI4_HOSTDESC_DESC_TYPE_SHIFT; currDesc->hw.tagInfo = tag; currDesc->hw.pktInfo = (descPktType << PAL_CPPI4_HOSTDESC_PKT_TYPE_SHIFT) | (gPpFDqueues[i].qMgr << PAL_CPPI4_HOSTDESC_PKT_RETQMGR_SHIFT) | (gPpFDqueues[i].qId << PAL_CPPI4_HOSTDESC_PKT_RETQNUM_SHIFT); if ((PAL_CPPI_ALLOC_CALLOC == gPpFDqueues[i].allocType)&&(currBuffer != NULL)) { currDesc->hw.orgBuffLen = bufferSize; currDesc->hw.orgBufPtr = PAL_CPPI4_VIRT_2_PHYS(currBuffer); currBuffer = (Ptr)((Uint32)currBuffer + bufferSize); } else if (PAL_CPPI_ALLOC_SKB == gPpFDqueues[i].allocType) { struct sk_buff *skb; skb = dev_alloc_skb(bufferSize); if (NULL == skb) { CPPI_ERR("SKB allocation FAILED\n"); if (currBuffer != NULL) { PAL_osMemFree(0, currBuffer, gPpFDqueues[i].descCount * bufferSize); currBuffer = NULL; } return -1; } skb_reserve (skb, NET_IP_ALIGN); /* 16 bit align the IP fields. */ currDesc->hw.orgBuffLen = bufferSize - NET_IP_ALIGN; currDesc->hw.orgBufPtr = PAL_CPPI4_VIRT_2_PHYS(skb->data); currDesc->skb = skb; } #ifdef CONFIG_WIFI_PROXY else if (gPpFDqueues[i].qId == PAL_CPPI_PP_QMGR_G2_WIFI_FW_RX_REASSEMBLY_HOST_FD_Q_NUM) { /* set return queue to be wifi rx reassembly rx complete queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_QMGR_G2_WIFI_RX_PROXY_REASSEMBLY_HOST_DESC_COMPLETE; currDesc->hw.pktInfo = (PAL_CPPI4_HOSTDESC_PKT_TYPE_ETH << PAL_CPPI4_HOSTDESC_PKT_TYPE_SHIFT) | (tmpQ.qMgr << PAL_CPPI4_HOSTDESC_PKT_RETQMGR_SHIFT) | (tmpQ.qNum << PAL_CPPI4_HOSTDESC_PKT_RETQNUM_SHIFT) | (PAL_CPPI4_HOSTDESC_PKT_RETPLCY_UNLINKED << PAL_CPPI4_HOSTDESC_PKT_RETPLCY_SHIFT); } #endif /* CONFIG_WIFI_PROXY */ else { currDesc->hw.orgBuffLen = 0; currDesc->hw.orgBufPtr = 0; currDesc->skb = NULL; } PAL_CPPI4_CACHE_WRITEBACK(currDesc, gPpFDqueues[i].descSize); PAL_cppi4QueuePush(tmpQHnd, (Ptr)PAL_CPPI4_VIRT_2_PHYS((Uint32)currDesc), PAL_CPPI4_DESCSIZE_2_QMGRSIZE(gPpFDqueues[i].descSize), 0); currDescRegionPtr[gPpFDqueues[i].descRegion] = (Ptr)((Uint32)currDescRegionPtr[gPpFDqueues[i].descRegion] + gPpFDqueues[i].descSize); } } else if (gPpFDqueues[i].descType == CPPI41_DESC_TYPE_TEARDOWN) { tmpQHnd = get_queue_handle(palHandle, gPpFDqueues[i].qMgr, gPpFDqueues[i].qId); if (!tmpQHnd) return -1; #ifdef CONFIG_AVM_CPPI_DEBUG { FDqueue_t *fdq = &gPpFDqueues[i]; print_FDqueue_info(fdq, currDescRegionPtr[fdq->descRegion], (Ptr)PAL_CPPI4_VIRT_2_PHYS(currDescRegionPtr[fdq->descRegion]), NULL, 0); } #endif for (descCount = 0; descCount < gPpFDqueues[i].descCount; descCount++) { Cppi4TeardownDesc *currDesc = NULL; if(NULL == currDescRegionPtr[gPpFDqueues[i].descRegion]) { CPPI_ERR("Cppi4TeardownDesc region %d FAILED\n", gPpFDqueues[i].descRegion); return -1; } currDesc = (Cppi4TeardownDesc*)currDescRegionPtr[gPpFDqueues[i].descRegion]; PAL_CPPI4_CACHE_WRITEBACK(currDesc, gPpFDqueues[i].descSize); PAL_cppi4QueuePush(tmpQHnd, (Ptr)PAL_CPPI4_VIRT_2_PHYS((Uint32)currDesc), PAL_CPPI4_DESCSIZE_2_QMGRSIZE(gPpFDqueues[i].descSize), 0); currDescRegionPtr[gPpFDqueues[i].descRegion] = (Ptr)((Uint32)currDescRegionPtr[gPpFDqueues[i].descRegion] + gPpFDqueues[i].descSize); } } } #ifdef CONFIG_IPSEC_SUPPORT /********************************************************************************/ /*********** Setup Encrypt & Decrypt PDSP Free Q ******************/ /********************************************************************************/ else if (gPpFDqueues[i].descRegion == PAL_CPPI_PP_IPSEC_MONOLITHIC_GLOBAL_DESC_REGION) { Cppi4EmbdDesc *currDesc = (Cppi4EmbdDesc*)PAL_CPPI_PP_IPSEC_MONOLITHIC_FD_BASE; tmpQHnd = get_queue_handle(palHandle, gPpFDqueues[i].qMgr, gPpFDqueues[i].qId); if (!tmpQHnd) return -1; CPPI_DBG("Initialization of Free Descriptors Q[%d]Mgr[%d], base address = 0x%X, descCount = %d\n", gPpFDqueues[i].qId, gPpFDqueues[i].qMgr, PAL_CPPI_PP_IPSEC_MONOLITHIC_FD_BASE, gPpFDqueues[i].descCount); #ifdef CONFIG_AVM_CPPI_DEBUG print_FDqueue_info(&gPpFDqueues[i], currDesc, (Ptr)IO_VIRT2PHY((Uint32)currDesc), NULL, 0); #endif for (descCount = 0; descCount < gPpFDqueues[i].descCount; descCount++) { PAL_cppi4QueuePush(tmpQHnd, (Ptr)IO_VIRT2PHY((Uint32)currDesc), 0, 0); currDesc = (Cppi4EmbdDesc*)((Uint32)currDesc + gPpFDqueues[i].descSize); } } #endif } return 0; } static Int32 cppi_init_pp_host2pp_dma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; Uint32 i; /* Common initializations */ rxCh.dmaNum = PAL_CPPI_PP_HOST2PP_INFRA_DMA_RX_TX; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.sopOffset = PAL_CPPI_PP_START_HEADROOM_OFFSET; rxCh.retryOnStarvation = 0; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; txCh.dmaNum = PAL_CPPI_PP_HOST2PP_INFRA_DMA_RX_TX; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; /* HOST2PP Infrastructure DMA */ for (i = 0; i < PAL_CPPI_PP_HOST2PP_INFRA_DMA_CH_COUNT; i++) { /* Input Queue */ tmpQ.qMgr = PAL_CPPI_PP_HOST2PP_INFRA_INPUT_Q_MGR; tmpQ.qNum = PAL_CPPI_PP_HOST2PP_INFRA_INPUT_Q_NUM(i); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Output Queue */ tmpQ.qMgr = PAL_CPPI_PP_HOST2PP_PP_INPUT_Q_MGR; tmpQ.qNum = PAL_CPPI_PP_HOST2PP_PP_INPUT_Q_NUM(i); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Set up Rx channel */ rxCh.chNum = PAL_CPPI_PP_HOST2PP_INFRA_DMA_CH_NUM(i); rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_HOST2PP_PP_INPUT_Q_MGR; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_HOST2PP_PP_INPUT_Q_NUM(i); rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_HOST2PP_INFRA_EMB_FD_Q_MGR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_HOST2PP_INFRA_EMB_FD_Q_NUM(i); if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n",rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up Tx channel */ txCh.chNum = PAL_CPPI_PP_HOST2PP_INFRA_DMA_CH_NUM(i); txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n",txCh.dmaNum, txCh.chNum); return -1; } /* Enable Tx-Rx channels */ PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); } return 0; } /************************************************************************** * FUNCTION NAME : static void save_ingress_dma_channels_state(void) ************************************************************************** * DESCRIPTION : * This function is called to save the current state of dma channels in the * RAL. **************************************************************************/ static void save_ingress_dma_channels_state(void) { Uint32 i; /* Save the state of rx dma channels before disable them */ for (i = 0; i < PAL_CPPI41_NUM_DMA_BLOCK; i++) { if (gCppiPpInitCfg.dmaBlock[i].ralCtrlBase) g_original_dma_channels_configuration[i] = gCppiPpInitCfg.dmaBlock[i].ralCtrlBase->Control_Reg; else g_original_dma_channels_configuration[i] = 0; } } /************************************************************************** * FUNCTION NAME : static void disable_dma_channels(PAL_Handle* palHandle, * PAL_CPPI_PP_DMA_BLOCKS_e dma_number, Uint32 channels_to_disable_bitmap) ************************************************************************** * DESCRIPTION : * This function is called to disable dma channels in the RAL. **************************************************************************/ static void disable_dma_channels(PAL_Handle* palHandle, PAL_CPPI_PP_DMA_BLOCKS_e dma_number, Uint32 channels_to_disable_bitmap) { Uint32 bitmap = gCppiPpInitCfg.dmaBlock[dma_number].ralCtrlBase->Control_Reg & ~(channels_to_disable_bitmap); PAL_cppi4RalEnable(*palHandle, dma_number, bitmap); } Int32 disable_all_packet_ram_rx_dma_channels(void) { PAL_Handle palHandle = PAL_cppi4Init(&gCppiPpInitCfg, CPPI41_DOMAIN_PP); u32 channels_to_disable_bitmap = 0; if(!palHandle) { CPPI_ERR("PAL_cppi4Init of CPPI41_DOMAIN_PP failed!\n"); return CPPI_POST_INIT_ERR_PAL_HND; } /* Save the current state of rx dma channels. */ save_ingress_dma_channels_state(); /* Disable PACKET RAM Channels for SGMII1, SGMII0, RGMII1, RGMII0, ATOM, MoCA and OFD0 RX DMA */ channels_to_disable_bitmap = (1<descInfo = CPPI41_EM_DESCINFO_DTYPE_EMBEDDED | CPPI41_EM_DESCINFO_SLOTCNT_PP; tmpDesc->tagInfo = 0x3FFF; tmpDesc->pktInfo = (PAL_CPPI4_HOSTDESC_PKT_TYPE_ETH << CPPI41_EM_PKTINFO_PKTTYPE_SHIFT) | (PAL_CPPI4_HOSTDESC_PKT_RETPLCY_UNLINKED << CPPI41_EM_PKTINFO_RETPOLICY_SHIFT) | (tmpQ.qMgr << CPPI41_EM_PKTINFO_RETQMGR_SHIFT) | (tmpQ.qNum << CPPI41_EM_PKTINFO_RETQ_SHIFT); PAL_CPPI4_CACHE_WRITEBACK(tmpDesc, gPpFDqueues[i].descSize); PAL_cppi4QueuePush(tmpQHnd, (Ptr)IO_VIRT2PHY((Uint32)tmpDesc), PAL_CPPI4_DESCSIZE_2_QMGRSIZE(gPpFDqueues[i].descSize), 0); } } } return ret; } /************************************************************************** * FUNCTION NAME : static void restore_dma_channels_status(PAL_Handle* palHandle, * PAL_CPPI_PP_DMA_BLOCKS_e dma_number) ************************************************************************** * DESCRIPTION : * This function is called to restore the saved dma channels status in the RAL. **************************************************************************/ static void restore_dma_channels_status(PAL_Handle* palHandle, PAL_CPPI_PP_DMA_BLOCKS_e dma_number) { PAL_cppi4RalEnable(*palHandle, dma_number, g_original_dma_channels_configuration[dma_number]); } Int32 restore_all_packet_ram_rx_dma_channels(void) { PAL_Handle palHandle = PAL_cppi4Init(&gCppiPpInitCfg, CPPI41_DOMAIN_PP); Int32 ret = 0; ret=restore_packet_ram_desc_info(palHandle); restore_dma_channels_status(&palHandle, PAL_CPPI_PP_DMA04_SGMII1_RX); restore_dma_channels_status(&palHandle, PAL_CPPI_PP_DMA03_SGMII0_RX); restore_dma_channels_status(&palHandle, PAL_CPPI_PP_DMA23_RGMII1_RX_TX); restore_dma_channels_status(&palHandle, PAL_CPPI_PP_DMA05_RGMII0_RX); restore_dma_channels_status(&palHandle, PAL_CPPI_PP_DMA07_ATOM_RX_TX); restore_dma_channels_status(&palHandle, PAL_CPPI_PP_DMA06_MoCA_RX_TX); restore_dma_channels_status(&palHandle, PAL_CPPI_PP_DMA00_OFDM0_RX); restore_dma_channels_status(&palHandle, PAL_CPPI_PP_DMA01_OFDM1_RX); restore_dma_channels_status(&palHandle, PAL_CPPI_PP_DMA02_SC_QAM_RX); return ret; } EXPORT_SYMBOL(restore_all_packet_ram_rx_dma_channels); #if CONFIG_NP_APP_DATAPIPE static Int32 cppi_init_pp_data_pipe_dma_channels(PAL_Handle palHandle) { Int32 ret = -1; Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; /* Common initializations */ rxCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.sopOffset = 0; rxCh.retryOnStarvation = 0; txCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; /**********************************/ /* NP2APP Data Infrastructure DMA */ /**********************************/ /* Input Queue (High) */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA10_INFRA_INPUT_HI_NP2APP_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Input Queue (Low) */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA10_INFRA_INPUT_LOW_NP2APP_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* RX Complete Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_QMGR_G2_NP2APP_RX_COMPLETE_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* TX Complete Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_QMGR_G2_NP2APP_TX_COMPLETE_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Set up Rx channel */ rxCh.chNum = PAL_CPPI_PP_DMA10_NP2APP_INFRA_RX_CH; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_NP2APP_RX_COMPLETE_Q_NUM; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_PPINFO_HOST_FD_Q_NUM; rxCh.u.hostPktCfg.fdbQueue[1].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[1].qNum = PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_DATA_HOST_FD_Q_NUM; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up Tx channel */ txCh.chNum = PAL_CPPI_PP_DMA10_NP2APP_INFRA_TX_CH; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } /* Enable Tx-Rx channels */ PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); /**********************************/ /* NP2APP Ctrl Infrastructure DMA */ /**********************************/ /* Input Ctrl Queue (High) */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA10_INFRA_INPUT_CTRL_HI_NP2APP_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Input Ctrl Queue (Low) */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA10_INFRA_INPUT_CTRL_LOW_NP2APP_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Set up Rx Ctrl channel */ rxCh.chNum = PAL_CPPI_PP_DMA10_NP2APP_INFRA_RX_CTRL_CH; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_NP2APP_RX_COMPLETE_Q_NUM; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_CTRL_PPINFO_HOST_FD_Q_NUM; rxCh.u.hostPktCfg.fdbQueue[1].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[1].qNum = PAL_CPPI_PP_QMGR_G2_NP2APP_INFRA_CTRL_DATA_HOST_FD_Q_NUM; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up Tx Ctrl channel */ txCh.chNum = PAL_CPPI_PP_DMA10_NP2APP_INFRA_CTRL_TX_CH; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } /* Enable Tx-Rx channels */ PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); /**********************************/ /* APP2NP Data Infrastructure DMA */ /**********************************/ /* Input Queue (High) */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA10_INFRA_INPUT_HI_APP2NP_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Input Queue (Low) */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA10_INFRA_INPUT_LOW_APP2NP_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* RX Complete Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_QMGR_G2_APP2NP_RX_COMPLETE_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* TX Complete Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_QMGR_G2_APP2NP_TX_COMPLETE_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Set up Rx channel */ rxCh.chNum = PAL_CPPI_PP_DMA10_APP2NP_INFRA_RX_CH; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_APP2NP_RX_COMPLETE_Q_NUM; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_PPINFO_HOST_FD_Q_NUM; rxCh.u.hostPktCfg.fdbQueue[1].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[1].qNum = PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_DATA_HOST_FD_Q_NUM; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up Tx channel */ txCh.chNum = PAL_CPPI_PP_DMA10_APP2NP_INFRA_TX_CH; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } /* Enable Tx-Rx Data channels */ PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); /**********************************/ /* APP2NP Ctrl Infrastructure DMA */ /**********************************/ /* Ctrl Input Queue (High) */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA10_INFRA_INPUT_CTRL_HI_APP2NP_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Ctrl Input Queue (Low) */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA10_INFRA_INPUT_CTRL_LOW_APP2NP_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Set up Rx Ctrl channel */ rxCh.chNum = PAL_CPPI_PP_DMA10_APP2NP_INFRA_RX_CTRL_CH; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_APP2NP_RX_HI_COMPLETE_Q_NUM; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_CTRL_PPINFO_HOST_FD_Q_NUM; rxCh.u.hostPktCfg.fdbQueue[1].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[1].qNum = PAL_CPPI_PP_QMGR_G2_APP2NP_INFRA_CTRL_DATA_HOST_FD_Q_NUM; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up Tx channel */ txCh.chNum = PAL_CPPI_PP_DMA10_APP2NP_INFRA_CTRL_TX_CH; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } /* Enable Tx-Rx Data channels */ PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); ret = 0; if (rxChHdl) PAL_cppi4RxChDestroy(rxChHdl, NULL); if (txChHdl) PAL_cppi4TxChDestroy(txChHdl, NULL); return ret; } #endif #ifdef CONFIG_WIFI_PROXY static Int32 cppi_init_pp_wifi_rx_dma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; Uint32 i; /****************************/ /* WIFI HOST infrastructure */ /****************************/ /* Common initializations */ rxCh.dmaNum = PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX; rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.sopOffset = 0; rxCh.retryOnStarvation = 0; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_QMGR_G2_WIFI_INFRA_HOST_RX_FD_Q_NUM; txCh.dmaNum = PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; /****************************/ /* WIFI HOST infrastructure */ /****************************/ FOR_EACH_WIFI_DEVICE_ID(i) { CPPI_DBG("Wifi Device %d\n", i); /* output queue */ tmpQ.qMgr = WIFI_DEVICE_TO_WIFI_HOST_RX_INFRA_RX_CH_OUT_Q_MGR; tmpQ.qNum = WIFI_DEVICE_TO_WIFI_HOST_RX_INFRA_RX_CH_OUT_Q(i); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* rx dma channel */ rxCh.chNum = WIFI_DEVICE_TO_WIFI_HOST_RX_INFRA_RX_CH(i); rxCh.rxCompQueue.qMgr = WIFI_DEVICE_TO_WIFI_HOST_RX_INFRA_RX_CH_OUT_Q_MGR; rxCh.rxCompQueue.qNum = WIFI_DEVICE_TO_WIFI_HOST_RX_INFRA_RX_CH_OUT_Q(i); rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } CPPI_DBG("\tHost rx infra rx channel %d: output queue = G%d.%d, free queue = G%d.%d\n", rxCh.chNum, rxCh.rxCompQueue.qMgr, rxCh.rxCompQueue.qNum, rxCh.u.hostPktCfg.fdbQueue[0].qMgr, rxCh.u.hostPktCfg.fdbQueue[0].qNum); /* input queue */ tmpQ.qMgr = WIFI_DEVICE_TO_WIFI_HOST_RX_INFRA_TX_CH_INPUT_Q_MGR; tmpQ.qNum = WIFI_DEVICE_TO_WIFI_HOST_RX_INFRA_TX_CH_INPUT_Q(i); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* tx dma channel */ txCh.chNum = WIFI_DEVICE_TO_WIFI_HOST_RX_INFRA_TX_CH(i); txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } CPPI_DBG("\tHost rx infra tx channel %d: input queue = G%d.%d\n", txCh.chNum, tmpQ.qMgr, tmpQ.qNum); /* Enable Tx-Rx channels */ PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); } return 0; } static Int32 cppi_init_pp_wifi_proxy_rx_reassembly_infradma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; /***********************************/ /* WIFI Proxy RX infrastructure DMA*/ /***********************************/ /* Common initializations */ /* this configuration describes the output of the infraDMA. in our case: the output is embedded descriptor, */ /* so the queue must be a free queue that holds embedded descriptors */ rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.sopOffset = PAL_CPPI_PP_START_OF_PACKET_OFFSET; rxCh.retryOnStarvation = 0; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM; //describes free Queue for the embedded descriptors. if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; /***************************************/ /* WIFI RX FW infrastructure for PDSP0 */ /***************************************/ /* Set up Rx channel: output of the infraDMA */ rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_WIFI_RX_PROXY_REASSEMBLY_EMBEDDED_COMPLETE; /* Open rx channel on infraDMA 11 */ rxCh.dmaNum = PAL_CPPI_PP_DMA11_INFRA_RX_TX; /* channel must be aligned to chosen infraDMA queue's channel 7 (PAL_CPPI_PP_QMGR_G1_CDMA11_INFRA_INPUT_WIFI_RX_FW_REASSEMBLY_CH_7_HI_Q_NUM) */ /* each infraDMA queue is HW wired to a specific channel, so you must configure the appropriate channel of that queue */ rxCh.chNum = PAL_CPPI_PP_DMA11_WIFI_FW_RX_REASSEMBLY_INFRA_RX_CH; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up Tx channel */ /* Open tx channel on infraDMA 11 */ txCh.dmaNum = PAL_CPPI_PP_DMA11_INFRA_RX_TX; /* channel must be aligned to chosen infraDMA queue's channel 7 (PAL_CPPI_PP_QMGR_G1_CDMA11_INFRA_INPUT_WIFI_RX_FW_REASSEMBLY_CH_7_HI_Q_NUM) */ /* each infraDMA queue is HW wired to a specific channel, so you must configure the appropriate channel of that queue */ txCh.chNum = PAL_CPPI_PP_DMA11_WIFI_FW_RX_REASSEMBLY_INFRA_TX_CH; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } /* Open reassembly tx channel input queue: describes the input queue for the infraDMA (the input is linked list of host descriptors) */ tmpQ.qMgr = WIFI_DEVICE_TO_WIFI_TX_FW_INFRA_TX_CH_INPUT_Q_MGR; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA11_INFRA_INPUT_WIFI_RX_FW_REASSEMBLY_CH_7_HI_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Enable Tx-Rx channels */ PAL_cppi4EnableRxChannel(rxChHdl , NULL); PAL_cppi4EnableTxChannel(txChHdl , NULL); /*---------------------------------------------Second infraDMA for PDSP1---------------------------------*/ /***************************************/ /* WIFI RX FW infrastructure for PDSP1 */ /***************************************/ /* Set up Rx channel: output of the infraDMA */ rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_WIFI_RX_PROXY_REASSEMBLY_EMBEDDED_COMPLETE_PDSP1; /* Open rx channel on infraDMA 11 */ rxCh.dmaNum = PAL_CPPI_PP_DMA11_INFRA_RX_TX; /* channel must be aligned to chosen infraDMA queue's channel 6 (PAL_CPPI_PP_QMGR_G1_CDMA11_INFRA_INPUT_WIFI_RX_FW_REASSEMBLY_CH_6_HI_Q_NUM) */ /* each infraDMA queue is HW wired to a specific channel, so you must configure the appropriate channel of that queue */ rxCh.chNum = PAL_CPPI_PP_DMA11_WIFI_FW_RX_REASSEMBLY_INFRA_RX_CH_PDSP1; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up Tx channel */ /* Open tx channel on infraDMA 11 */ txCh.dmaNum = PAL_CPPI_PP_DMA11_INFRA_RX_TX; /* channel must be aligned to chosen infraDMA queue's channel 6 (PAL_CPPI_PP_QMGR_G1_CDMA11_INFRA_INPUT_WIFI_RX_FW_REASSEMBLY_CH_6_HI_Q_NUM) */ /* each infraDMA queue is HW wired to a specific channel, so you must configure the appropriate channel of that queue */ txCh.chNum = PAL_CPPI_PP_DMA11_WIFI_FW_RX_REASSEMBLY_INFRA_TX_CH_PDSP1; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } /* Open reassembly tx channel input queue: describes the input queue for the infraDMA (the input is linked list of host descriptors) */ tmpQ.qMgr = WIFI_DEVICE_TO_WIFI_TX_FW_INFRA_TX_CH_INPUT_Q_MGR; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA11_INFRA_INPUT_WIFI_RX_FW_REASSEMBLY_CH_6_HI_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Enable Tx-Rx channels */ PAL_cppi4EnableRxChannel(rxChHdl , NULL); PAL_cppi4EnableTxChannel(txChHdl , NULL); return 0; } /************************************************************************** * FUNCTION NAME : cppi_init_pp_wifi_tx_dma_channels(PAL_Handle palHandle) ************************************************************************** * DESCRIPTION : * The function initializes InfraDMA11 to handle MultiCast packets * intended for the WiFi Proxy TX in order to support Zero Copy feature. * RETURNS : * 0 - Success * >0 - Error **************************************************************************/ static Int32 cppi_init_pp_wifi_tx_dma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; /* Common initializations */ rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.sopOffset = PAL_CPPI_PP_START_HEADROOM_OFFSET; rxCh.retryOnStarvation = 0; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; /*****************************/ /* WIFI TX FW infrastructure */ /*****************************/ /* output queue */ tmpQ.qMgr = WIFI_DEVICE_TO_WIFI_TX_FW_INFRA_RX_CH_OUT_Q_MGR; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_WIFI_TX_DEV0_INPUT_Q; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Set up Rx channel */ rxCh.rxCompQueue.qMgr = WIFI_DEVICE_TO_WIFI_TX_FW_INFRA_RX_CH_OUT_Q_MGR; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G1_WIFI_TX_DEV0_INPUT_Q; /* Open rx channel on infraDMA 11 */ rxCh.dmaNum = PAL_CPPI_PP_DMA11_INFRA_RX_TX; rxCh.chNum = PAL_CPPI_PP_DMA11_WIFI_DEVICE0_TX_FW_INFRA_RX_CH; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* input queue */ tmpQ.qMgr = WIFI_DEVICE_TO_WIFI_TX_FW_INFRA_TX_CH_INPUT_Q_MGR; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA11_INFRA_INPUT_WIFI_DEVICE_MC_AQM_TX_HI_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Set up Tx channel */ /* Open tx channel on infraDMA 11 */ txCh.dmaNum = PAL_CPPI_PP_DMA11_INFRA_RX_TX; txCh.chNum = PAL_CPPI_PP_DMA11_WIFI_DEVICE0_TX_FW_INFRA_TX_CH; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } /* Enable Tx-Rx channels */ PAL_cppi4EnableRxChannel(rxChHdl , NULL); PAL_cppi4EnableTxChannel(txChHdl , NULL); return 0; } #endif Int32 avalanche_cppi_init_pp_sanity_dma_channels(PAL_Handle palHandle, Cppi4Queue freeQ, Cppi4BufPool freeBuf) { Int32 ret = -1; Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; /* Set up Rx channel */ rxCh.dmaNum = PAL_CPPI_PP_DMA09_INFRA_RX_TX; rxCh.chNum = PAL_CPPI_PP_DMA09_INFRA_RX_CH_2; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.sopOffset = PAL_CPPI_PP_START_OF_PACKET_OFFSET; rxCh.retryOnStarvation = 0; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.u.embeddedPktCfg.fdQueue = freeQ; rxCh.u.embeddedPktCfg.fBufPool[0] = freeBuf; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_LOW_Q_NUM; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } CPPI_DBG("TX FW infra rx channel %d: output queue = G%d.%d, free queue = G%d.%d, freeBuf mgr = %d pool = %d\n", rxCh.chNum, rxCh.rxCompQueue.qMgr, rxCh.rxCompQueue.qNum, rxCh.u.embeddedPktCfg.fdQueue.qMgr, rxCh.u.embeddedPktCfg.fdQueue.qNum, rxCh.u.embeddedPktCfg.fBufPool[0].bMgr, rxCh.u.embeddedPktCfg.fBufPool[0].bPool); /* input queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_QMGR_G2_CDMA9_INFRA_INPUT_LOW_TX_CH_2_HI_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Set up Tx channel */ txCh.dmaNum = PAL_CPPI_PP_DMA09_INFRA_RX_TX; // TODO - return to prev config txCh.chNum = PAL_CPPI_PP_DMA09_INFRA_TX_CH_2; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } CPPI_DBG("TX FW infra tx channel %d: input queue = G%d.%d\n", txCh.chNum, tmpQ.qMgr, tmpQ.qNum); /* Enable Tx-Rx channels */ PAL_cppi4EnableRxChannel(rxChHdl , NULL); PAL_cppi4EnableTxChannel(txChHdl , NULL); ret = 0; if (rxChHdl) PAL_cppi4RxChDestroy(rxChHdl, NULL); if (txChHdl) PAL_cppi4TxChDestroy(txChHdl, NULL); return ret; } EXPORT_SYMBOL(avalanche_cppi_init_pp_sanity_dma_channels); volatile typedef struct moca_rx_cmd1_s { Uint32 ps_flags:4, pkt_type:5, ps_word_cnt:5, desc_type:4, qMgr_idx:2, queue_idx:12; }moca_rx_cmd1_t; volatile typedef struct moca_rx_cfg0_s { Uint32 res:29, no_ps_pop:1, discard_enable:1, ps_location_mode:1; }moca_rx_cfg0_t; volatile typedef struct moca_rx_cfg1_s { Uint32 threshold_1:16, threshold_0:16; }moca_rx_cfg1_t; /**************************************************************************/ /*! \fn static int set_rx_channel_status(PAL_Handle palHandle, * Cppi4RxChInitCfg* rxCh, * Bool enable) ************************************************************************** * \brief Enable/disable a given rx channel. **************************************************************************/ static int set_rx_channel_status(PAL_Handle palHandle, Cppi4RxChInitCfg* rxCh, Bool enable) { PAL_Cppi4RxChHnd rxChHdl = PAL_cppi4RxChOpen(palHandle, rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh->dmaNum, rxCh->chNum); return -1; } if (enable) { PAL_cppi4EnableRxChannel(rxChHdl, NULL); CPPI_DBG("Open and enable dmaNum=%d, rxChNum=%d\n", rxCh->dmaNum, rxCh->chNum); } else { PAL_cppi4DisableRxChannel(rxChHdl, NULL); PAL_cppi4RxChClose(rxChHdl, NULL); CPPI_DBG("Disable and close dmaNum=%d, rxChNum=%d\n", rxCh->dmaNum, rxCh->chNum); } PAL_cppi4RxChDestroy(rxChHdl, NULL); return 0; } /**************************************************************************/ /*! \fn static int set_tx_channel_status(PAL_Handle palHandle, * Cppi4TxChInitCfg* txCh, * Bool enable) ************************************************************************** * \brief Enable/disable a given tx channel. **************************************************************************/ static int set_tx_channel_status(PAL_Handle palHandle, Cppi4TxChInitCfg* txCh, Bool enable) { PAL_Cppi4TxChHnd txChHdl = PAL_cppi4TxChOpen(palHandle, txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh->dmaNum, txCh->chNum); return -1; } if (enable) { PAL_cppi4EnableTxChannel(txChHdl, NULL); CPPI_DBG("Open and enable dmaNum=%d, txChNum=%d\n", txCh->dmaNum, txCh->chNum); } else { PAL_cppi4DisableTxChannel(txChHdl, NULL); PAL_cppi4TxChClose(txChHdl, NULL); CPPI_DBG("Disable and close dmaNum=%d, txChNum=%d\n", txCh->dmaNum, txCh->chNum); } PAL_cppi4TxChDestroy(txChHdl, NULL); return 0; } static Int32 set_pp_moca_rx_dma_channels(PAL_Handle palHandle, Bool enable) { Int32 rc = 0; Cppi4RxChInitCfg rxCh; /* MoCA_RX_CHs */ rxCh.dmaNum = PAL_CPPI_PP_DMA06_MoCA_RX_TX; rxCh.sopOffset = PAL_CPPI_PP_START_OF_PACKET_OFFSET; rxCh.retryOnStarvation = 0; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_LOW_Q_NUM; // CH_0 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_MoCA_DDR_RX_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_1 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_2 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_3 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_8 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // Note that MoCA does not have PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR return rc; } static Int32 set_pp_moca_tx_dma_channels(PAL_Handle palHandle, Bool enable) { Cppi4TxChInitCfg txCh; txCh.dmaNum = PAL_CPPI_PP_DMA06_MoCA_RX_TX; txCh.chNum = PAL_CPPI_PP_DMA06_MoCA_TX_CH; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; return set_tx_channel_status(palHandle, &txCh, enable); } Int32 cppi_init_pp_moca_dma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; moca_rx_cmd1_t *moca_cmd; moca_rx_cfg0_t *moca_cfg0; moca_rx_cfg1_t *moca_cfg1; moca_cmd = (Ptr)PAL_CPPI_PP_DMA06_MoCA_RX_CMD1; moca_cfg0 = (Ptr)PAL_CPPI_PP_DMA06_MoCA_RX_CFG0; moca_cfg1 = (Ptr)PAL_CPPI_PP_DMA06_MoCA_RX_CFG1; /* MoCA_RX_CHs */ if (set_pp_moca_rx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable moca rx dma channels\n"); return -1; } moca_cmd->queue_idx = PAL_CPPI_PP_QMGR_G2_SEQUENCER_LOW_Q_NUM; moca_cmd->qMgr_idx = PAL_CPPI_PP_QMGR_G2; moca_cmd->desc_type = CPPI41_DESC_TYPE_EMBEDDED; moca_cmd->pkt_type = PAL_CPPI4_HOSTDESC_PKT_TYPE_ETH; moca_cfg0->no_ps_pop = True; moca_cfg1->threshold_0 = g_threshold_0; moca_cfg1->threshold_1 = g_threshold_1; /* MoCA_TX_CHs */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_MoCA_TX_HI_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_MoCA_TX_LOW_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } if (set_pp_moca_tx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable moca tx dma channels\n"); return -1; } /* MoCA Infrastructlure DMA */ { /* Input Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_CDMA10_INFRA_INPUT_LOW_MoCA_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Output Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_QMGR_G2_HOST_RX_COMPLETE_MoCA_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } /* Set up RX channel */ rxCh.chNum = PAL_CPPI_PP_DMA10_MoCA_INFRA_RX_CH; rxCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.sopOffset = 0; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_HOST_RX_COMPLETE_MoCA_Q_NUM; rxCh.retryOnStarvation = 0; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_QMGR_G2_SHARED_LOW_INFRA_HOST_FD_Q_NUM; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up TX channel */ txCh.chNum = PAL_CPPI_PP_DMA10_MoCA_INFRA_TX_CH; txCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); PAL_cppi4RxChDestroy(rxChHdl, NULL); PAL_cppi4TxChDestroy(txChHdl, NULL); } return 0; } #ifdef CONFIG_INTEL_PP_NO_MOCA_DESC #define TRUE_IF_MOCA_EN False #else #define TRUE_IF_MOCA_EN True #endif qsmonRal_t mocaRalQsmon[] = { /* NOTE: This configuration will not work on silicon older than B0 stepping since a silicon bug prevents RAL from working properly with queues shared among multiple DMA channels. */ { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_MoCA_DDR_RX_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_12, .qsmonThreshold = PAL_CPPI_QSMON_PRIVATE_THRESHOLD, .qsmonChEn = TRUE_IF_MOCA_EN, .ralQEnable = TRUE_IF_MOCA_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_13, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = TRUE_IF_MOCA_EN, .ralQEnable = TRUE_IF_MOCA_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_14, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = TRUE_IF_MOCA_EN, .ralQEnable = TRUE_IF_MOCA_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel. qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = TRUE_IF_MOCA_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_4 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_5 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_6 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_7 */ // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR */ // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False // MoCA port does not have high priority DMA } }; EXPORT_SYMBOL(mocaRalQsmon); static Int32 cppi_init_pp_moca_ral_and_qsmon(PAL_Handle palHandle) { Uint32 chNum; Uint32 ralQenBitmap = 0; qsmonRal_t qsMonRalConfig; for (chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_0; chNum < PAL_CPPI_PP_DMA_GENERIC_RX_CHANNELS_NUM; chNum++) { qsMonRalConfig = mocaRalQsmon[chNum]; if (qsMonRalConfig.ralQEnable) ralQenBitmap |= (1 << chNum); if (qsMonRalConfig.qsmonChEn) { if (PAL_cppi4QSMonEnable(palHandle, PAL_CPPI_PP_QSMON_MGR3, qsMonRalConfig.qsmonThread, qsMonRalConfig.fdQueue, qsMonRalConfig.qsmonThreshold, PAL_CPPI_QSMON_DIRECTION_UP)) { CPPI_ERR("PAL_cppi4QSMonEnable failed for PAL_CPPI_PP_QSMON_MGR3 qsmonThread=%d\n", qsMonRalConfig.qsmonThread); return -1; } } } if (PAL_cppi4RalEnable(palHandle, PAL_CPPI_PP_DMA06_MoCA_RX_TX, ralQenBitmap)) { CPPI_ERR("PAL_cppi4RalEnable failed for dmaNum=%d, ralQenBitmap=%d\n", PAL_CPPI_PP_DMA06_MoCA_RX_TX, ralQenBitmap); return -1; } return 0; } static Int32 set_pp_atom_rx_dma_channels(PAL_Handle palHandle, Bool enable) { Int32 rc = 0; Cppi4RxChInitCfg rxCh; /* ATOM_RX_CHs */ rxCh.dmaNum = PAL_CPPI_PP_DMA07_ATOM_RX_TX; rxCh.sopOffset = PAL_CPPI_PP_START_OF_PACKET_OFFSET; rxCh.retryOnStarvation = 0; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_LOW_Q_NUM; // CH_0 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_ATOM_DDR_RX_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_1 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_2 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_3 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_8 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_9 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_ATOM_DDR_RX_HIGH_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_HI_Q_NUM; rc |= set_rx_channel_status(palHandle, &rxCh, enable); return rc; } static Int32 set_pp_atom_tx_dma_channels(PAL_Handle palHandle, Bool enable) { Cppi4TxChInitCfg txCh; /* ATOM_TX_CHs */ txCh.dmaNum = PAL_CPPI_PP_DMA07_ATOM_RX_TX; txCh.chNum = PAL_CPPI_PP_DMA07_ATOM_TX_CH; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; return set_tx_channel_status(palHandle, &txCh, enable); } static Int32 cppi_init_pp_atom_dma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; Uint32 chNum; /* ATOM_RX_CHs */ if (set_pp_atom_rx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable atom rx dma channels\n"); return -1; } /* ATOM_TX_CHs */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_ATOM_TX_HI_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_ATOM_TX_LOW_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } if (set_pp_atom_tx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable atom tx dma channels\n"); return -1; } /* ATOM Infrastructure DMA */ for (chNum = 0; chNum < PAL_CPPI_PP_ATOM_INFRA_DMA_CH_COUNT; chNum++) { /* Input Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_ATOM_INFRA_INPUT_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } /* Output Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_ATOM_HOST_RX_COMPLETE_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } /* Set up RX channel */ rxCh.chNum = PAL_CPPI_PP_ATOM_INFRA_DMA_CH_NUM(chNum); rxCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.sopOffset = 0; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_ATOM_HOST_RX_COMPLETE_Q_NUM(chNum); rxCh.retryOnStarvation = 0; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_ATOM_INFRA_HOST_FD_Q_NUM(chNum); rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up TX channel */ txCh.chNum = PAL_CPPI_PP_ATOM_INFRA_DMA_CH_NUM(chNum); txCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); } return 0; } qsmonRal_t atomRalQsmon[] = { /* NOTE: This configuration will not work on silicon older than B0 stepping since a silicon bug prevents RAL from working properly with queues shared among multiple DMA channels. */ { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_ATOM_DDR_RX_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_6, .qsmonThreshold = PAL_CPPI_QSMON_PRIVATE_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_7, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_8, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel. qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_4 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_5 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_6 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_7 */ // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_ATOM_DDR_RX_HIGH_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False } }; EXPORT_SYMBOL(atomRalQsmon); static Int32 cppi_init_pp_atom_ral_and_qsmon(PAL_Handle palHandle) { Uint32 chNum; Uint32 ralQenBitmap = 0; qsmonRal_t qsMonRalConfig; for (chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_0; chNum < PAL_CPPI_PP_DMA_GENERIC_RX_CHANNELS_NUM; chNum++) { qsMonRalConfig = atomRalQsmon[chNum]; if (qsMonRalConfig.ralQEnable) ralQenBitmap |= (1 << chNum); if (qsMonRalConfig.qsmonChEn) { if (PAL_cppi4QSMonEnable(palHandle, PAL_CPPI_PP_QSMON_MGR3, qsMonRalConfig.qsmonThread, qsMonRalConfig.fdQueue, qsMonRalConfig.qsmonThreshold, PAL_CPPI_QSMON_DIRECTION_UP)) { CPPI_ERR("PAL_cppi4QSMonEnable failed for PAL_CPPI_PP_QSMON_MGR3 qsmonThread=%d\n", qsMonRalConfig.qsmonThread); return -1; } } } if (PAL_cppi4RalEnable(palHandle, PAL_CPPI_PP_DMA07_ATOM_RX_TX, ralQenBitmap)) { CPPI_ERR("PAL_cppi4RalEnable failed for dmaNum=%d, ralQenBitmap=%d\n", PAL_CPPI_PP_DMA07_ATOM_RX_TX, ralQenBitmap); return -1; } return 0; } static Int32 set_pp_rgmii0_rx_dma_channels_status(PAL_Handle palHandle, Bool enable) { Int32 rc = 0; Cppi4RxChInitCfg rxCh; /* RGMII0_RX_CHs */ rxCh.dmaNum = PAL_CPPI_PP_DMA05_RGMII0_RX; rxCh.sopOffset = PAL_CPPI_PP_START_OF_PACKET_OFFSET; rxCh.retryOnStarvation = 0; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_LOW_Q_NUM; // CH_0 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_RGMII0_DDR_RX_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_1 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_2 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_3 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_8 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_9 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_RGMII0_DDR_RX_HIGH_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_HI_Q_NUM; rc |= set_rx_channel_status(palHandle, &rxCh, enable); return rc; } static Int32 set_pp_rgmii0_tx_dma_channels(PAL_Handle palHandle, Bool enable) { Cppi4TxChInitCfg txCh; txCh.dmaNum = PAL_CPPI_PP_DMA16_RGMII0_TX; txCh.chNum = PAL_CPPI_PP_DMA16_RGMII0_TX_CH; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; return set_tx_channel_status(palHandle, &txCh, enable); } static Int32 cppi_init_pp_rgmii0_dma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; Uint32 chNum; /* RGMII0_RX_CHs */ if (set_pp_rgmii0_rx_dma_channels_status(palHandle, True)) { CPPI_ERR("Failed to enable rgmii0 rx dma channels\n"); return -1; } /* RGMII0_TX_CHs */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_RGMII0_TX_HI_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_RGMII0_TX_LOW_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } if (set_pp_rgmii0_tx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable rgmii0 tx dma channels\n"); return -1; } /* RGMII0 Infrastructure DMA */ for (chNum = 0; chNum < PAL_CPPI_PP_RGMII0_INFRA_DMA_CH_COUNT; chNum++) { /* Input Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_RGMII0_INFRA_INPUT_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } /* Output Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_RGMII0_HOST_RX_COMPLETE_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } /* Set up RX channel */ rxCh.chNum = PAL_CPPI_PP_RGMII0_INFRA_DMA_CH_NUM(chNum); rxCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.sopOffset = 0; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_RGMII0_HOST_RX_COMPLETE_Q_NUM(chNum); rxCh.retryOnStarvation = 0; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_RGMII0_INFRA_HOST_FD_Q_NUM(chNum); rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up TX channel */ txCh.chNum = PAL_CPPI_PP_RGMII0_INFRA_DMA_CH_NUM(chNum); txCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); } return 0; } #ifdef CONFIG_INTEL_PP_NO_NRGMII0_DESC #define TRUE_IF_RGMII0_EN False #else #define TRUE_IF_RGMII0_EN True #endif qsmonRal_t rgmii0RalQsmon[] = { /* NOTE: This configuration will not work on silicon older than B0 stepping since a silicon bug prevents RAL from working properly with queues shared among multiple DMA channels. */ { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_RGMII0_DDR_RX_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_18, .qsmonThreshold = PAL_CPPI_QSMON_PRIVATE_THRESHOLD, .qsmonChEn = TRUE_IF_RGMII0_EN, .ralQEnable = TRUE_IF_RGMII0_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_19, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = TRUE_IF_RGMII0_EN, .ralQEnable = TRUE_IF_RGMII0_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_20, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = TRUE_IF_RGMII0_EN, .ralQEnable = TRUE_IF_RGMII0_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel. qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = TRUE_IF_RGMII0_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_4 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_5 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_6 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_7 */ // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_RGMII0_DDR_RX_HIGH_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False } }; EXPORT_SYMBOL(rgmii0RalQsmon); static Int32 cppi_init_pp_rgmii0_ral_and_qsmon(PAL_Handle palHandle) { Uint32 chNum; Uint32 ralQenBitmap = 0; qsmonRal_t qsMonRalConfig; for (chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_0; chNum < PAL_CPPI_PP_DMA_GENERIC_RX_CHANNELS_NUM; chNum++) { qsMonRalConfig = rgmii0RalQsmon[chNum]; if (qsMonRalConfig.ralQEnable) ralQenBitmap |= (1 << chNum); if (qsMonRalConfig.qsmonChEn) { if (PAL_cppi4QSMonEnable(palHandle, PAL_CPPI_PP_QSMON_MGR3, qsMonRalConfig.qsmonThread, qsMonRalConfig.fdQueue, qsMonRalConfig.qsmonThreshold, PAL_CPPI_QSMON_DIRECTION_UP)) { CPPI_ERR("PAL_cppi4QSMonEnable failed for PAL_CPPI_PP_QSMON_MGR3 qsmonThread=%d\n", qsMonRalConfig.qsmonThread); return -1; } } } if (PAL_cppi4RalEnable(palHandle, PAL_CPPI_PP_DMA05_RGMII0_RX, ralQenBitmap)) { CPPI_ERR("PAL_cppi4RalEnable failed for dmaNum=%d, ralQenBitmap=%d\n", PAL_CPPI_PP_DMA05_RGMII0_RX, ralQenBitmap); return -1; } return 0; } static Int32 set_pp_rgmii1_rx_dma_channels(PAL_Handle palHandle, Bool enable) { Int32 rc = 0; Cppi4RxChInitCfg rxCh; /* RGMII1_RX_CHs */ rxCh.dmaNum = PAL_CPPI_PP_DMA23_RGMII1_RX_TX; rxCh.sopOffset = PAL_CPPI_PP_START_OF_PACKET_OFFSET; rxCh.retryOnStarvation = 0; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_LOW_Q_NUM; // CH_0 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_RGMII1_DDR_RX_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_1 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_2 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_3 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_8 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_9 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_RGMII1_DDR_RX_HIGH_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_HI_Q_NUM; rc |= set_rx_channel_status(palHandle, &rxCh, enable); return rc; } static Int32 set_pp_rgmii1_tx_dma_channels(PAL_Handle palHandle, Bool enable) { Cppi4TxChInitCfg txCh; txCh.dmaNum = PAL_CPPI_PP_DMA23_RGMII1_RX_TX; txCh.chNum = PAL_CPPI_PP_DMA23_RGMII_TX_CH; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; return set_tx_channel_status(palHandle, &txCh, enable); } static Int32 cppi_init_pp_rgmii1_dma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; Uint32 chNum; /* RGMII1_RX_CHs */ if (set_pp_rgmii1_rx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable rgmii1 rx dma channels\n"); return -1; } /* RGMII1_TX_CHs */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_RGMII1_TX_HI_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_RGMII1_TX_LOW_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } if (set_pp_rgmii1_tx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable rgmii1 tx dma channels\n"); return -1; } /* RGMII1 Infrastructure DMA */ for (chNum = 0; chNum < PAL_CPPI_PP_RGMII1_INFRA_DMA_CH_COUNT; chNum++) { /* Input Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_RGMII1_INFRA_INPUT_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } /* Output Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_RGMII1_HOST_RX_COMPLETE_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } /* Set up RX channel */ rxCh.chNum = PAL_CPPI_PP_RGMII1_INFRA_DMA_CH_NUM(chNum); rxCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.sopOffset = 0; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_RGMII1_HOST_RX_COMPLETE_Q_NUM(chNum); rxCh.retryOnStarvation = 0; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_RGMII1_INFRA_HOST_FD_Q_NUM(chNum); rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up TX channel */ txCh.chNum = PAL_CPPI_PP_RGMII1_INFRA_DMA_CH_NUM(chNum); txCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); } return 0; } #ifdef CONFIG_INTEL_PP_NO_NRGMII1_DESC #define TRUE_IF_RGMII1_EN False #else #define TRUE_IF_RGMII1_EN True #endif qsmonRal_t rgmii1RalQsmon[] = { /* NOTE: This configuration will not work on silicon older than B0 stepping since a silicon bug prevents RAL from working properly with queues shared among multiple DMA channels. */ { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_RGMII1_DDR_RX_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_0, .qsmonThreshold = PAL_CPPI_QSMON_PRIVATE_THRESHOLD, .qsmonChEn = TRUE_IF_RGMII1_EN, .ralQEnable = TRUE_IF_RGMII1_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_1, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = TRUE_IF_RGMII1_EN, .ralQEnable = TRUE_IF_RGMII1_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_2, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = TRUE_IF_RGMII1_EN, .ralQEnable = TRUE_IF_RGMII1_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel. qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = TRUE_IF_RGMII1_EN }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_4 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_5 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_6 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_7 */ // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_RGMII1_DDR_RX_HIGH_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False } }; EXPORT_SYMBOL(rgmii1RalQsmon); static Int32 cppi_init_pp_rgmii1_ral_and_qsmon(PAL_Handle palHandle) { Uint32 chNum; Uint32 ralQenBitmap = 0; qsmonRal_t qsMonRalConfig; for (chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_0; chNum < PAL_CPPI_PP_DMA_GENERIC_RX_CHANNELS_NUM; chNum++) { qsMonRalConfig = rgmii1RalQsmon[chNum]; if (qsMonRalConfig.ralQEnable) ralQenBitmap |= (1 << chNum); if (qsMonRalConfig.qsmonChEn) { if (PAL_cppi4QSMonEnable(palHandle, PAL_CPPI_PP_QSMON_MGR3, qsMonRalConfig.qsmonThread, qsMonRalConfig.fdQueue, qsMonRalConfig.qsmonThreshold, PAL_CPPI_QSMON_DIRECTION_UP)) { CPPI_ERR("PAL_cppi4QSMonEnable failed for PAL_CPPI_PP_QSMON_MGR3 qsmonThread=%d\n", qsMonRalConfig.qsmonThread); return -1; } } } if (PAL_cppi4RalEnable(palHandle, PAL_CPPI_PP_DMA23_RGMII1_RX_TX, ralQenBitmap)) { CPPI_ERR("PAL_cppi4RalEnable failed for dmaNum=%d, ralQenBitmap=%d\n", PAL_CPPI_PP_DMA23_RGMII1_RX_TX, ralQenBitmap); return -1; } return 0; } static Int32 set_pp_sgmii0_rx_dma_channels(PAL_Handle palHandle, Bool enable) { Int32 rc = 0; Cppi4RxChInitCfg rxCh; /* SGMII0_RX_CHs */ rxCh.dmaNum = PAL_CPPI_PP_DMA03_SGMII0_RX; rxCh.sopOffset = PAL_CPPI_PP_START_OF_PACKET_OFFSET; rxCh.retryOnStarvation = 0; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_LOW_Q_NUM; // CH_0 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SGMII0_DDR_RX_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_1 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_2 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_3 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_8 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_9 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SGMII0_DDR_RX_HIGH_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_HI_Q_NUM; rc |= set_rx_channel_status(palHandle, &rxCh, enable); return rc; } static Int32 set_pp_sgmii0_tx_dma_channels(PAL_Handle palHandle, Bool enable) { Cppi4TxChInitCfg txCh; txCh.dmaNum = PAL_CPPI_PP_DMA14_SGMII0_TX; txCh.chNum = PAL_CPPI_PP_DMA14_SGMII0_TX_CH; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; return set_tx_channel_status(palHandle, &txCh, enable); } static Int32 cppi_init_pp_sgmii0_dma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; Uint32 chNum; /* SGMII0_RX_CHs */ if (set_pp_sgmii0_rx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable sgmii0 rx dma channels\n"); return -1; } /* SGMII0_TX_CHs */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_SGMII0_TX_HI_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_SGMII0_TX_LOW_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } if (set_pp_sgmii0_tx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable sgmii0 tx dma channels\n"); return -1; } /* SGMII0 Infrastructure DMA */ for (chNum = 0; chNum < PAL_CPPI_PP_SGMII0_INFRA_DMA_CH_COUNT; chNum++) { /* Input Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_SGMII0_INFRA_INPUT_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } /* Output Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_SGMII0_HOST_RX_COMPLETE_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } /* Set up RX channel */ rxCh.chNum = PAL_CPPI_PP_SGMII0_INFRA_DMA_CH_NUM(chNum); rxCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.sopOffset = 0; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_SGMII0_HOST_RX_COMPLETE_Q_NUM(chNum); rxCh.retryOnStarvation = 0; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_SGMII0_INFRA_HOST_FD_Q_NUM(chNum); rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up TX channel */ txCh.chNum = PAL_CPPI_PP_SGMII0_INFRA_DMA_CH_NUM(chNum); txCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); } return 0; } qsmonRal_t sgmii0RalQsmon[] = { /* NOTE: This configuration will not work on silicon older than B0 stepping since a silicon bug prevents RAL from working properly with queues shared among multiple DMA channels. */ { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SGMII0_DDR_RX_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_0, .qsmonThreshold = PAL_CPPI_QSMON_PRIVATE_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_1, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_2, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel. qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_4 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_5 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_6 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_7 */ // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SGMII0_DDR_RX_HIGH_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False } }; EXPORT_SYMBOL(sgmii0RalQsmon); static Int32 cppi_init_pp_sgmii0_ral_and_qsmon(PAL_Handle palHandle) { Uint32 chNum; Uint32 ralQenBitmap; qsmonRal_t qsMonRalConfig; ralQenBitmap = 0; for (chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_0; chNum < PAL_CPPI_PP_DMA_GENERIC_RX_CHANNELS_NUM; chNum++) { qsMonRalConfig = sgmii0RalQsmon[chNum]; if (qsMonRalConfig.ralQEnable) ralQenBitmap |= (1 << chNum); if (qsMonRalConfig.qsmonChEn) { if (PAL_cppi4QSMonEnable(palHandle, PAL_CPPI_PP_QSMON_MGR4, qsMonRalConfig.qsmonThread, qsMonRalConfig.fdQueue, qsMonRalConfig.qsmonThreshold, PAL_CPPI_QSMON_DIRECTION_UP)) { CPPI_ERR("PAL_cppi4QSMonEnable failed for PAL_CPPI_PP_QSMON_MGR4 qsmonThread=%d\n", qsMonRalConfig.qsmonThread); return -1; } } } if (PAL_cppi4RalEnable(palHandle, PAL_CPPI_PP_DMA03_SGMII0_RX, ralQenBitmap)) { CPPI_ERR("PAL_cppi4RalEnable failed for dmaNum=%d, ralQenBitmap=%d\n", PAL_CPPI_PP_DMA03_SGMII0_RX, ralQenBitmap); return -1; } return 0; } static Int32 set_pp_sgmii1_rx_dma_channels(PAL_Handle palHandle, Bool enable) { Int32 rc = 0; Cppi4RxChInitCfg rxCh; /* SGMII1_RX_CHs */ rxCh.dmaNum = PAL_CPPI_PP_DMA04_SGMII1_RX; rxCh.sopOffset = PAL_CPPI_PP_START_OF_PACKET_OFFSET; rxCh.retryOnStarvation = 0; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_LOW_Q_NUM; // CH_0 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SGMII1_DDR_RX_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_1 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_2 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_3 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_8 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rc |= set_rx_channel_status(palHandle, &rxCh, enable); // CH_9 rxCh.chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SGMII1_DDR_RX_HIGH_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_HI_Q_NUM; rc |= set_rx_channel_status(palHandle, &rxCh, enable); return rc; } static Int32 set_pp_sgmii1_tx_dma_channels(PAL_Handle palHandle, Bool enable) { Cppi4TxChInitCfg txCh; txCh.dmaNum = PAL_CPPI_PP_DMA15_SGMII1_TX; txCh.chNum = PAL_CPPI_PP_DMA15_SGMII1_TX_CH; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; return set_tx_channel_status(palHandle, &txCh, enable); } static Int32 cppi_init_pp_sgmii1_dma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; Uint32 chNum; /* SGMII1_RX_CHs */ if (set_pp_sgmii1_rx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable sgmii1 rx dma channels\n"); return -1; } /* SGMII1_TX_CHs */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_SGMII1_TX_HI_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_SGMII1_TX_LOW_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } if (set_pp_sgmii1_tx_dma_channels(palHandle, True)) { CPPI_ERR("Failed to enable sgmii1 tx dma channels\n"); return -1; } /* SGMII1 Infrastructure DMA */ for (chNum = 0; chNum < PAL_CPPI_PP_SGMII1_INFRA_DMA_CH_COUNT; chNum++) { /* Input Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_SGMII1_INFRA_INPUT_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } /* Output Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_SGMII1_HOST_RX_COMPLETE_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return(-1); } /* Set up RX channel */ rxCh.chNum = PAL_CPPI_PP_SGMII1_INFRA_DMA_CH_NUM(chNum); rxCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.sopOffset = 0; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_SGMII1_HOST_RX_COMPLETE_Q_NUM(chNum); rxCh.retryOnStarvation = 0; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_SGMII1_INFRA_HOST_FD_Q_NUM(chNum); rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up TX channel */ txCh.chNum = PAL_CPPI_PP_SGMII1_INFRA_DMA_CH_NUM(chNum); txCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); } return 0; } qsmonRal_t sgmii1RalQsmon[] = { /* NOTE: This configuration will not work on silicon older than B0 stepping since a silicon bug prevents RAL from working properly with queues shared among multiple DMA channels. */ { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SGMII1_DDR_RX_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_24, .qsmonThreshold = PAL_CPPI_QSMON_PRIVATE_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_25, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_0_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_3_THREAD_26, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_1_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel. qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_4 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_5 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_6 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_7 */ // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_LOW_SHARED_XL_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_HIGH_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SGMII1_DDR_RX_HIGH_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False } }; EXPORT_SYMBOL(sgmii1RalQsmon); static Int32 cppi_init_pp_sgmii1_ral_and_qsmon(PAL_Handle palHandle) { Uint32 chNum; Uint32 ralQenBitmap = 0; qsmonRal_t qsMonRalConfig; for (chNum = PAL_CPPI_PP_DMA_GENERIC_RX_CH_0; chNum < PAL_CPPI_PP_DMA_GENERIC_RX_CHANNELS_NUM; chNum++) { qsMonRalConfig = sgmii1RalQsmon[chNum]; if (qsMonRalConfig.ralQEnable) ralQenBitmap |= (1 << chNum); if (qsMonRalConfig.qsmonChEn) { if (PAL_cppi4QSMonEnable(palHandle, PAL_CPPI_PP_QSMON_MGR3, qsMonRalConfig.qsmonThread, qsMonRalConfig.fdQueue, qsMonRalConfig.qsmonThreshold, PAL_CPPI_QSMON_DIRECTION_UP)) { CPPI_ERR("PAL_cppi4QSMonEnable failed for PAL_CPPI_PP_QSMON_MGR3 qsmonThread=%d\n", qsMonRalConfig.qsmonThread); return -1; } } } if (PAL_cppi4RalEnable(palHandle, PAL_CPPI_PP_DMA04_SGMII1_RX, ralQenBitmap)) { CPPI_ERR("PAL_cppi4RalEnable failed for dmaNum=%d, ralQenBitmap=%d\n", PAL_CPPI_PP_DMA04_SGMII1_RX, ralQenBitmap); return -1; } return 0; } static Int32 cppi_pp_configure_qsmon(PAL_Handle pal_handle, Uint32 manager, qsmonRal_t *qsmon, Bool setCount) { PAL_Result err = 0; if (NULL == qsmon) { CPPI_ERR("qsmon is NULL\n"); return -1; } if (setCount) { if (qsmon->direction == PAL_CPPI_QSMON_DIRECTION_DOWN) { err |= PAL_cppi4QSMonSetQdepthCnt(pal_handle, manager, qsmon->qsmonThread, qsmon->qsmonThreshold); } } else { err |= PAL_cppi4QSMonEnable(pal_handle, manager, qsmon->qsmonThread, qsmon->fdQueue, 0, qsmon->direction); } return err; } Int32 cppi_init_pp_debug_qsmon(PAL_Handle palHandle, Bool setCount) { PAL_Result err = 0; Uint32 manager; Uint32 thread, max_threads; qsmonRal_t *qsmon; for (manager = PAL_CPPI_PP_QSMON_MGR0; manager <= PAL_CPPI_PP_BSMON_MGR; manager++) { switch (manager) { case PAL_CPPI_PP_QSMON_MGR1: qsmon = gQsmon1; max_threads = ARRAY_SIZE(gQsmon1); break; case PAL_CPPI_PP_QSMON_MGR2: qsmon = gQsmon2; max_threads = ARRAY_SIZE(gQsmon2); break; case PAL_CPPI_PP_BSMON_MGR: qsmon = gBsmon; max_threads = ARRAY_SIZE(gBsmon); break; default: continue; break; } for (thread = 0; thread < max_threads; thread++) { if (!qsmon[thread].qsmonChEn) continue; err |= cppi_pp_configure_qsmon(palHandle, manager, &qsmon[thread], setCount); } } if (err) { CPPI_ERR("Unable to configure qsmon\n"); return -1; } return 0; } static Int32 cppi_init_pp_dma_channels(PAL_Handle palHandle) { /*********************************************/ /*********** HOST2PP DMA channels ************/ /*********************************************/ if (cppi_init_pp_host2pp_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_host2pp_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /******************************************/ /*********** MoCA DMA channels ************/ /******************************************/ if (cppi_init_pp_moca_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_moca_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /******************************************/ /*********** ATOM DMA channels ************/ /******************************************/ if (cppi_init_pp_atom_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_atom_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /********************************************/ /*********** RGMII0 DMA channels ************/ /********************************************/ if (cppi_init_pp_rgmii0_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_rgmii0_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /********************************************/ /*********** RGMII1 DMA channels ************/ /********************************************/ if (cppi_init_pp_rgmii1_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_rgmii1_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /********************************************/ /*********** SGMII0 DMA channels ************/ /********************************************/ if (cppi_init_pp_sgmii0_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_sgmii0_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /********************************************/ /*********** SGMII1 DMA channels ************/ /********************************************/ if (cppi_init_pp_sgmii1_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_sgmii1_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } #ifdef CONFIG_NP_APP_DATAPIPE /********************************************/ /********* Data Pipe DMA channels ***********/ /********************************************/ if (cppi_init_pp_data_pipe_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_data_pipe_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } #endif #ifdef CONFIG_WIFI_PROXY /********************************************/ /********* WiFi proxy DMA channels **********/ /********************************************/ if (cppi_init_pp_wifi_rx_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_wifi_rx_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } if (cppi_init_pp_wifi_tx_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_wifi_tx_dma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } if (cppi_init_pp_wifi_proxy_rx_reassembly_infradma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_wifi_proxy_rx_reassembly_infradma_channels [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } #endif return 0; } static Int32 cppi_init_pp_ral_and_qsmon(PAL_Handle palHandle) { /*****************************************/ /*********** MoCA RAL & QSMON ************/ /*****************************************/ if (cppi_init_pp_moca_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_moca_ral_and_qsmon [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /*****************************************/ /*********** ATOM RAL & QSMON ************/ /*****************************************/ if (cppi_init_pp_atom_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_atom_ral_and_qsmon [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /*******************************************/ /*********** RGMII0 RAL & QSMON ************/ /*******************************************/ if (cppi_init_pp_rgmii0_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_rgmii0_ral_and_qsmon [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /*******************************************/ /*********** RGMII1 RAL & QSMON ************/ /*******************************************/ if (cppi_init_pp_rgmii1_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_rgmii1_ral_and_qsmon [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /*******************************************/ /*********** SGMII0 RAL & QSMON ************/ /*******************************************/ if (cppi_init_pp_sgmii0_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_sgmii0_ral_and_qsmon [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /*******************************************/ /*********** SGMII1 RAL & QSMON ************/ /*******************************************/ if (cppi_init_pp_sgmii1_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_sgmii1_ral_and_qsmon [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } return 0; } static int cppi_buffer_pool_count(void) { Uint32 i, ret=0; /* Look into all free decriptors queues */ for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) if (PAL_CPPI41_BMGR_MAX_POOLS > gPpFDqueues[i].bPool) b_pool_count[gPpFDqueues[i].bPool] += gPpFDqueues[i].descCount; /* Verify that the pool sizes are valid */ for (i = 0; i < PAL_CPPI41_BMGR_MAX_POOLS; i++) { CPPI_INFO("CPPI config will request %5u buffers on Buffer pool %i\n", b_pool_count[i], i); if (0 == b_pool_count[i]) continue; if (b_pool_count[i] > max_b_pool_count[i]) { CPPI_ERR("Buffer pool %i can support up to %u buffers but config requests %u\n", i, max_b_pool_count[i], b_pool_count[i]); ret++; } if (b_pool_count[i] & (b_pool_count[i]-1)) CPPI_INFO("Memory wasted, buffer count %u for pool %i is not power of 2\n", b_pool_count[i], i); /* Initialize the thresholds for the buffer pool monitor */ gBsmon[i].qsmonThreshold = b_pool_count[i]; } return ret; } #if (!defined(CONFIG_INTEL_KERNEL_PP_DRIVER_LOCAL) && defined(CONFIG_MRPC_CPPI_CLIENT)) static void init_buffer_pools(struct work_struct *work) { struct delayed_work *dwork = to_delayed_work(work); struct file *f; int ret = 0; if (init_buffer_pools_iterations > INIT_BUFFER_POOLS_MAX_ITER) { CPPI_ERR("done the maximum iterations polling mrpc init for buffer pools init\n"); kfree(dwork); return; } init_buffer_pools_iterations++; CPPI_DBG("Polling MRPC iteration %d\n", init_buffer_pools_iterations); f = filp_open("/sys/devices/platform/cppi_client/status", O_RDONLY, 0); CPPI_DBG("After file open\n"); #ifdef CONFIG_AVM_BUGFIXES /* * several bugs to fix here: * * 1) filp_open() returns ERR_PTR(err) on error, NOT 0. * 2) filep_close is never called. * * 2018-06-11, calle */ if (IS_ERR(f)) // Bugfix for 1) f = NULL; #endif if(f == NULL) { CPPI_DBG("MRPC Client is not ready... rescheduling...\n"); /* Schedule the work */ CPPI_DBG("Start polling MRPC for buffer pools init in %u ms, %lu jiffies\n", 100, msecs_to_jiffies(100)); schedule_delayed_work(dwork, msecs_to_jiffies(100)); } else { CPPI_DBG("MRPC Client is ready... trying to allocate buffer pools..\n"); #ifdef CONFIG_AVM_BUGFIXES filp_close(f, NULL); // Bugfix for 2) #endif ret = cppi_post_init(); if (ret == CPPI_POST_INIT_ERR_BUFF_INIT) { CPPI_DBG("Failed to initiate buffer pools, scheduling a new workqueue..\n"); /* Schedule the work */ CPPI_DBG("Start polling MRPC for buffer pools init in %u ms, %lu jiffies\n", 100, msecs_to_jiffies(100)); schedule_delayed_work(dwork, msecs_to_jiffies(100)); } else { if (ret == CPPI_POST_INIT_OK) CPPI_DBG("Buffer pools allocated successfully, destroying worqueue...\n"); else CPPI_DBG("Error during post init stage, destroying worqueue...\n"); kfree(dwork); } } return; } #endif Int32 avalanche_cppi_get_buffer_count(Uint32 bufPoolID, Uint32* buff_csount) { if (bufPoolID>=PAL_CPPI41_BMGR_MAX_POOLS || buff_csount==NULL) return 1; *buff_csount = b_pool_count[bufPoolID]; return 0; } EXPORT_SYMBOL(avalanche_cppi_get_buffer_count); struct q_count_update { Cppi4Queue q; Uint32 new_cnt; }; #define DEF_Q_UPDATE(m, qId, count) \ {.q.qMgr=m, .q.qNum=qId, .new_cnt=count} struct q_count_update q_count_profile_1[] = { DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, PAL_CPPI_PP_RX_LOW_0_SHARED_DDR_EMB_FD_DESC_COUNT_REDUCED), DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, PAL_CPPI_PP_RX_LOW_1_SHARED_DDR_EMB_FD_DESC_COUNT_REDUCED), DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_MoCA_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_MoCA_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT_REDUCED), #ifndef CONFIG_IPSEC_SUPPORT DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_MoCA_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_MoCA_RX_LOW_PRIVATE_DDR_EMB_FD_DESC_COUNT_REDUCED), #endif DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_WIFI_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_WIFI_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT_REDUCED), DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII0_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RGMII0_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT_REDUCED), DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII0_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RGMII0_RX_LOW_PRIVATE_DDR_EMB_FD_DESC_COUNT_REDUCED), DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII0_DDR_RX_HIGH_EMB_FD_Q_NUM, PAL_CPPI_PP_RGMII0_RX_HIGH_PRIVATE_DDR_EMB_FD_DESC_COUNT_REDUCED), DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII1_PACKET_RAM_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RGMII1_RX_LOW_PRIVATE_PACKET_RAM_EMB_FD_DESC_COUNT_REDUCED), DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII1_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_RGMII1_RX_LOW_PRIVATE_DDR_EMB_FD_DESC_COUNT_REDUCED), DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_RGMII1_DDR_RX_HIGH_EMB_FD_Q_NUM, PAL_CPPI_PP_RGMII1_RX_HIGH_PRIVATE_DDR_EMB_FD_DESC_COUNT_REDUCED), #ifdef CONFIG_WIFI_PROXY DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_WIFI_SHARED_DDR_RX_EMB_FD_Q_NUM, PAL_CPPI_PP_WIFI_FW_RX_EMB_FD_DESC_COUNT_REDUCED), DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_WIFI_FW_RX_REASSEMBLY_HOST_FD_Q_NUM,PAL_CPPI_PP_WIFI_FW_RX_REASSEMBLY_HOST_FD_DESC_COUNT), #endif DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, PAL_CPPI_PP_RX_LOW_XLONG_SHARED_DDR_EMB_FD_DESC_COUNT_REDUCED) }; struct q_count_update q_count_profile_2[] = { DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, PAL_CPPI_PP_RX_LOW_0_SHARED_DDR_EMB_FD_DESC_COUNT_EXTENDED), DEF_Q_UPDATE(PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, PAL_CPPI_PP_RX_LOW_1_SHARED_DDR_EMB_FD_DESC_COUNT_EXTENDED) }; static void inline cppi_mem_profile_init(void) { int i, j, list_size; struct q_count_update *update_list; CPPI_INFO("CPPI memProfile %d\n", memProfile); switch (memProfile) { case 1: // Reduced resources mode update_list = q_count_profile_1; list_size = ARRAY_SIZE(q_count_profile_1); break; case 2: // Extended resources, allocate more buffers/descritors update_list = q_count_profile_2; list_size = ARRAY_SIZE(q_count_profile_2); break; default: // default configuration, there's nothing to do. return; } /* Override QSMON thresholds and the number of free descriptors according to the new configuration */ for (j = 0; j < list_size; j++) for (i = 0; i < ARRAY_SIZE(gQsmon2); i++) if (gQsmon2[i].fdQueue.qNum == update_list[j].q.qNum && gQsmon2[i].fdQueue.qMgr == update_list[j].q.qMgr) { CPPI_DBG("%u.%u qsmonThreshold %d->%d\n", gQsmon2[i].fdQueue.qMgr, gQsmon2[i].fdQueue.qNum, gQsmon2[i].qsmonThreshold, update_list[j].new_cnt); gQsmon2[i].qsmonThreshold = update_list[j].new_cnt; continue; } for (j = 0; j < list_size; j++) for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) if (gPpFDqueues[i].qId == update_list[j].q.qNum && gPpFDqueues[i].qMgr == update_list[j].q.qMgr) { CPPI_DBG("%u.%u descCount %d->%d\n", gPpFDqueues[i].qMgr, gPpFDqueues[i].qId, gPpFDqueues[i].descCount, update_list[j].new_cnt); gPpFDqueues[i].descCount = update_list[j].new_cnt; continue; } return; } /**************************************************************************/ /*! \fn int cppi_enable_pp_srams(void) ************************************************************************** * \brief Enable pp srams (in case the last execution stopped in enhanced * PSM state, PP srams are off and must be power on before cppi * initialization) - during boot time all PP srams should to be turn on. * \return 0 on success else negative number. **************************************************************************/ int cppi_enable_pp_srams(void) { Puma7PmuSram_e i; /* Enable all PP SRAMs. */ for (i = PMU_PP_ST1_SRAM_HIGH_0_ID; i < PMU_PP_ST2_SRAM_LOW_31_ID; i++) { if (PUMA7_SRAM_Ctrl(i, 1)) { CPPI_ERR(KERN_ERR "Failed to enable [%d] memory.\n", i); /* Systen failed to get out from PSM state - reboot! */ BUG_ON(1); return -1; } } printk("PP SRAMs are enable now.\n"); return 0; } int avalanche_cppi_init(void) { struct delayed_work *d_init_buffer_pools_work; PAL_Handle palHandle; unsigned int siliconStepping; #if !(!defined(CONFIG_INTEL_KERNEL_PP_DRIVER_LOCAL) && defined(CONFIG_MRPC_CPPI_CLIENT)) Uint32 ret; #endif cppi_enable_pp_srams(); PAL_osMemSet(&gCppiPpInitCfg, 0, sizeof(gCppiPpInitCfg)); gCppiPpInitCfg.debugToolBind = cppi_pp_proc_init; /************************************************/ /* Make sure the silicon stepping is supported */ /************************************************/ if (SRAM_Get_Boot_Param(SILICON_STEPPING_ID, &siliconStepping)) { CPPI_ERR("Silicon stepping retrieval unsuccessful\n"); BUG_ON(1); return -1; } if (siliconStepping < SILICON_STEPPING_ID_B_0) { CPPI_ERR("A stepping is not supported\n"); BUG_ON(1); return -1; } /************************************************/ /* Init variables limited by the memory profile */ /************************************************/ cppi_mem_profile_init(); /***********************/ /* Init Buffer Manager */ /***********************/ gCppiPpInitCfg.bufMgrBase[PAL_CPPI_PP_BUF_MGR] = (CSL_BufMgr_RegsOvly)PAL_CPPI_PP_BUF_MGR_BASE; if (cppi_buffer_pool_count()) return -1; /***********************/ /* Init Queue Managers */ /***********************/ cppi_init_pp_queue_managers(); /******************************/ /* Init Queue Status Monitors */ /******************************/ cppi_init_pp_queue_status_monitors_managers(); /****************************/ /* Init Descriptors Regions */ /****************************/ if (cppi_init_pp_descriptor_regions()) { CPPI_ERR("cppi_init_pp_descriptor_regions [CPPI41_DOMAIN_PP] FAILED\n"); return 0; } if (cppi_verification()) { CPPI_ERR("cppi_verification [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } /******************************************************************/ /*********** Init DMA addresses and attributes ********************/ /******************************************************************/ cppi_init_pp_dmas(); /***********************/ /* Init PP CPPI Domain */ /***********************/ palHandle = PAL_cppi4Init(&gCppiPpInitCfg, CPPI41_DOMAIN_PP); if(palHandle == NULL) { CPPI_ERR("PAL_cppi4Init of CPPI41_DOMAIN_PP failed!\n"); return 0; } CPPI_INFO("PAL_cppi4Init of CPPI41_DOMAIN_PP initialized successfully\n"); /*****************************************/ /*********** Setup RAL & QSMON ***********/ /*****************************************/ if (cppi_init_pp_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_ral_and_qsmon [CPPI41_DOMAIN_PP] FAILED\n"); return 0; } /************************************************/ /*********** Setup Docsis RAL & QSMON ***********/ /************************************************/ if (cppi_init_pp_docsis_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_docsis_ral_and_qsmon FAILED\n"); return (-1); } /*****************************************/ /************ Debug QSMON PRE ************/ /*****************************************/ if (cppi_init_pp_debug_qsmon(palHandle, False)) { CPPI_ERR("cppi_init_pp_debug_qsmon [CPPI41_DOMAIN_PP] pre FAILED\n"); return -1; } /**************************************************************/ /*********** Setup descriptors according to regions ***********/ /**************************************************************/ if (cppi_init_pp_free_q_descriptors(palHandle)) { CPPI_ERR("cppi_init_pp_free_q_descriptors [CPPI41_DOMAIN_PP] FAILED\n"); return 0; } /*****************************************/ /************ Debug QSMON POST ***********/ /*****************************************/ if (cppi_init_pp_debug_qsmon(palHandle, True)) { CPPI_ERR("cppi_init_pp_debug_qsmon [CPPI41_DOMAIN_PP] post FAILED\n"); return -1; } #if (!defined(CONFIG_INTEL_KERNEL_PP_DRIVER_LOCAL) && defined(CONFIG_MRPC_CPPI_CLIENT)) init_buffer_pools_iterations = 0; CPPI_DBG("Create single threaded work queue for atom buffers allocation\n"); d_init_buffer_pools_work = kmalloc(sizeof(struct delayed_work), GFP_KERNEL); if (!d_init_buffer_pools_work) { pr_err("%s: Error allocating mrpc polling worker\n", __func__); return -1; } CPPI_DBG("[Starting poll MRPC wq for atom buffer pools allocation\n"); /* Init the work */ INIT_DELAYED_WORK(d_init_buffer_pools_work, init_buffer_pools); /* schedule the work */ CPPI_DBG("Start polling MRPC for buffer pools init in %u ms, %lu jiffies", 100, msecs_to_jiffies(100)); schedule_delayed_work(d_init_buffer_pools_work, msecs_to_jiffies(100)); #else ret = cppi_post_init(); if( ret != CPPI_POST_INIT_OK ) { CPPI_ERR("cppi_post_init failed ret(%d)", ret); return -1; } #endif /* CONFIG_MRPC_CPPI_CLIENT */ return 0; } static Int32 cppi_init_pp_docsis_dma_channels(PAL_Handle palHandle) { Cppi4TxChInitCfg txCh; PAL_Cppi4TxChHnd txChHdl; Cppi4RxChInitCfg rxCh; PAL_Cppi4RxChHnd rxChHdl; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; Uint32 dmaNum; Uint32 chNum; /* DOCSIS_RX_CHs */ for (dmaNum = PAL_CPPI_PP_DMA00_OFDM0_RX; dmaNum <= PAL_CPPI_PP_DMA02_SC_QAM_RX; dmaNum++) { rxCh.dmaNum = dmaNum; for (chNum = PAL_CPPI_PP_DMA_DOCSIS_RX_CH_0; chNum <= PAL_CPPI_PP_DMA_DOCSIS_RX_CH_MAP; chNum++) { rxCh.chNum = chNum; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.sopOffset = PAL_CPPI_PP_START_OF_PACKET_OFFSET; rxCh.retryOnStarvation = 0; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_LOW_Q_NUM; switch (chNum) { case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_PRIVATE_PACKET_RAM: // CH 0 rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_DOCSIS_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_PACKET_RAM: // CH 1 rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_0_SHARED_DDR: // CH 2 rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_1_SHARED_DDR: // CH 3 rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_4: case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_5: case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_6: // Channels not used, ignore them continue; break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_7: // TODO: This DMA is needed by docsis rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_XL_DDR: // CH 8 rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_HIGH_PRIVATE_DDR: // CH 9 rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_DOCSIS_DDR_RX_HI_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_SEQUENCER_HI_Q_NUM; break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_MGMT_DDR: // CH 10 rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_QMGR_G2_DOCSIS_RX_MGMT_HOST_FD_Q_NUM; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_HOST_RX_COMPLETE_DOCSIS_MGMT_Q_NUM; tmpQ.qMgr = PAL_CPPI_PP_QMGR_G2; tmpQ.qNum = PAL_CPPI_PP_QMGR_G2_HOST_RX_COMPLETE_DOCSIS_MGMT_Q_NUM; if (NULL == PAL_cppi4QueueOpen(palHandle, tmpQ)) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return (-1); } break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_PLC_EM: // CH 11 rxCh.defDescType = CPPI41_DESC_TYPE_MONOLITHIC; rxCh.u.monolithicPktCfg.fdQueue.qMgr = PAL_CPPI_MAC_US_QMGR_DOCSIS; rxCh.u.monolithicPktCfg.fdQueue.qNum = US_MAC_FD_DLS_MONOLITIC_ID; rxCh.rxCompQueue.qMgr = PAL_CPPI_MAC_US_QMGR_DOCSIS; rxCh.rxCompQueue.qNum = US_MAC_DLS_COMMAND_FROM_EXT_APP_ID; break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_MAP: rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_MAC_US_QMGR_DOCSIS; rxCh.u.embeddedPktCfg.fdQueue.qNum = 276; rxCh.u.embeddedPktCfg.fBufPool[0].bPool = 1; rxCh.u.embeddedPktCfg.fBufPool[0].bMgr = PAL_CPPI_MAC_US_BUF_MGR; break; case PAL_CPPI_PP_DMA_DOCSIS_RX_CH_DS_FW_MPEG_TS_DDR: #if (defined(CONFIG_CABLE_MPEG_VFE) || defined(CONFIG_CABLE_MPEG_VFE_INT_MODE)) rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.sopOffset = 0; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_QMGR_G2_DS_FW_MPEG_TS_FD_INT_MODE_Q_NUM; rxCh.retryOnStarvation = 0; #endif break; } rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } PAL_cppi4EnableRxChannel(rxChHdl, NULL); CPPI_DBG("Open and enable dmaNum=%d, rxChNum=%d\n", rxCh.dmaNum, rxCh.chNum); } } /* TX_CH_MGMT */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_QMGR_G1_US_PREPROCESSING_MGMT_Q_NUM; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return 0; } /* Setup DOCSIS Infrastructure DMA */ for (chNum = 0; chNum < PAL_CPPI_PP_DOCSIS_INFRA_DMA_CH_COUNT; chNum++) { /* Input Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_DOCSIS_INFRA_INPUT_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return 0; } /* Output Queue */ tmpQ.qMgr = PAL_CPPI_PP_QMGR_G1; tmpQ.qNum = PAL_CPPI_PP_DOCSIS_HOST_RX_COMPLETE_Q_NUM(chNum); tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return 0; } /* Set up Rx channel */ rxCh.chNum = PAL_CPPI_PP_DOCSIS_INFRA_DMA_CH_NUM(chNum); rxCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; rxCh.defDescType = CPPI41_DESC_TYPE_HOST; rxCh.sopOffset = 0; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_DOCSIS_HOST_RX_COMPLETE_Q_NUM(chNum); rxCh.retryOnStarvation = 0; rxCh.u.hostPktCfg.fdbQueue[0].qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.hostPktCfg.fdbQueue[0].qNum = PAL_CPPI_PP_DOCSIS_INFRA_HOST_FD_Q_NUM(chNum); rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } txCh.chNum = PAL_CPPI_PP_DOCSIS_INFRA_DMA_CH_NUM(chNum); txCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); } return 0; } qsmonRal_t scQamRalQsmon[] = { /* NOTE: This configuration will not work on silicon older than B0 stepping since a silicon bug prevents RAL from working properly with queues shared among multiple DMA channels. */ { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_PRIVATE_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_DOCSIS_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_6, .qsmonThreshold = PAL_CPPI_QSMON_DOCSIS_ONLY_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_7, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_0_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_8, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_1_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel. qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_4 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_5 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_6 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_7 */ // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_XL_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_HIGH_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_DOCSIS_DDR_RX_HI_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False } }; EXPORT_SYMBOL(scQamRalQsmon); static Int32 cppi_init_pp_sc_qam_ral_and_qsmon(PAL_Handle palHandle) { Uint32 chNum; Uint32 ralQenBitmap = 0; qsmonRal_t qsMonRalConfig; for (chNum = PAL_CPPI_PP_DMA_DOCSIS_RX_CH_0; chNum <= PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_XL_DDR; chNum++) { qsMonRalConfig = scQamRalQsmon[chNum]; if (qsMonRalConfig.ralQEnable) ralQenBitmap |= (1 << chNum); if (qsMonRalConfig.qsmonChEn) { if (PAL_cppi4QSMonEnable(palHandle, PAL_CPPI_PP_QSMON_MGR4, qsMonRalConfig.qsmonThread, qsMonRalConfig.fdQueue, qsMonRalConfig.qsmonThreshold, PAL_CPPI_QSMON_DIRECTION_UP)) { CPPI_ERR("PAL_cppi4QSMonEnable failed for PAL_CPPI_PP_QSMON_MGR4 qsmonThread=%d\n", qsMonRalConfig.qsmonThread); return -1; } } } if (PAL_cppi4RalEnable(palHandle, PAL_CPPI_PP_DMA02_SC_QAM_RX, ralQenBitmap)) { CPPI_ERR("PAL_cppi4RalEnable failed for dmaNum=%d, ralQenBitmap=%d\n", PAL_CPPI_PP_DMA02_SC_QAM_RX, ralQenBitmap); return -1; } return 0; } qsmonRal_t ofdm0RalQsmon[] = { /* NOTE: This configuration will not work on silicon older than B0 stepping since a silicon bug prevents RAL from working properly with queues shared among multiple DMA channels. */ { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_PRIVATE_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_DOCSIS_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_18, .qsmonThreshold = PAL_CPPI_QSMON_DOCSIS_ONLY_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_19, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_0_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_20, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_1_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel. qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_4 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_5 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_6 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_7 */ // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_XL_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_HIGH_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_DOCSIS_DDR_RX_HI_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False } }; EXPORT_SYMBOL(ofdm0RalQsmon); static Int32 cppi_init_pp_ofdm0_ral_and_qsmon(PAL_Handle palHandle) { Uint32 chNum; Uint32 ralQenBitmap; qsmonRal_t qsMonRalConfig; ralQenBitmap = 0; for (chNum = PAL_CPPI_PP_DMA_DOCSIS_RX_CH_0; chNum <= PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_XL_DDR; chNum++) { qsMonRalConfig = ofdm0RalQsmon[chNum]; if (qsMonRalConfig.ralQEnable) ralQenBitmap |= (1 << chNum); if (qsMonRalConfig.qsmonChEn) { if (PAL_cppi4QSMonEnable(palHandle, PAL_CPPI_PP_QSMON_MGR4, qsMonRalConfig.qsmonThread, qsMonRalConfig.fdQueue, qsMonRalConfig.qsmonThreshold, PAL_CPPI_QSMON_DIRECTION_UP)) { CPPI_ERR("PAL_cppi4QSMonEnable failed for PAL_CPPI_PP_QSMON_MGR4 qsmonThread=%d\n", qsMonRalConfig.qsmonThread); return -1; } } } if (PAL_cppi4RalEnable(palHandle, PAL_CPPI_PP_DMA00_OFDM0_RX, ralQenBitmap)) { CPPI_ERR("PAL_cppi4RalEnable failed for dmaNum=%d, ralQenBitmap=%d\n", PAL_CPPI_PP_DMA00_OFDM0_RX, ralQenBitmap); return -1; } return 0; } qsmonRal_t ofdm1RalQsmon[] = { /* NOTE: This configuration will not work on silicon older than B0 stepping since a silicon bug prevents RAL from working properly with queues shared among multiple DMA channels. */ { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_PRIVATE_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_DOCSIS_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_12, .qsmonThreshold = PAL_CPPI_QSMON_DOCSIS_ONLY_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_PACKET_RAM */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_PACKET_RAM_RX_LOW_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_13, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_0_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_0_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, .qsmonThread = PAL_CPPI_PP_QSMON_4_THREAD_14, .qsmonThreshold = PAL_CPPI_QSMON_SHARED_QUEUES_THRESHOLD, .qsmonChEn = True, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_1_SHARED_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_RX_LOW_1_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel. qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = True }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_4 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_5 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_6 */ .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_GENERIC_RX_CH_7 */ // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_XL_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_SHARED_DDR_XLONG_RX_LOW_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False }, { /* PAL_CPPI_PP_DMA_DOCSIS_RX_CH_HIGH_PRIVATE_DDR */ .fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_DOCSIS_DDR_RX_HI_EMB_FD_Q_NUM, .fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2, // Fallback Channel, qsmonThread and qsmonThreshold are not used. .qsmonChEn = False, .ralQEnable = False } }; EXPORT_SYMBOL(ofdm1RalQsmon); static Int32 cppi_init_pp_ofdm1_ral_and_qsmon(PAL_Handle palHandle) { Uint32 chNum; Uint32 ralQenBitmap = 0; qsmonRal_t qsMonRalConfig; for (chNum = PAL_CPPI_PP_DMA_DOCSIS_RX_CH_0; chNum <= PAL_CPPI_PP_DMA_DOCSIS_RX_CH_LOW_SHARED_XL_DDR; chNum++) { qsMonRalConfig = ofdm1RalQsmon[chNum]; if (qsMonRalConfig.ralQEnable) ralQenBitmap |= (1 << chNum); if (qsMonRalConfig.qsmonChEn) { if (PAL_cppi4QSMonEnable(palHandle, PAL_CPPI_PP_QSMON_MGR4, qsMonRalConfig.qsmonThread, qsMonRalConfig.fdQueue, qsMonRalConfig.qsmonThreshold, PAL_CPPI_QSMON_DIRECTION_UP)) { CPPI_ERR("PAL_cppi4QSMonEnable failed for PAL_CPPI_PP_QSMON_MGR4 qsmonThread=%d\n", qsMonRalConfig.qsmonThread); return -1; } } } if (PAL_cppi4RalEnable(palHandle, PAL_CPPI_PP_DMA01_OFDM1_RX, ralQenBitmap)) { CPPI_ERR("PAL_cppi4RalEnable failed for dmaNum=%d, ralQenBitmap=%d\n", PAL_CPPI_PP_DMA01_OFDM1_RX, ralQenBitmap); return -1; } return 0; } static Int32 cppi_init_pp_docsis_ral_and_qsmon(PAL_Handle palHandle) { if (0 != cppi_init_pp_sc_qam_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_sc_qam_ral_and_qsmon [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } if (0 != cppi_init_pp_ofdm0_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_ofdm0_ral_and_qsmon [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } if (0 != cppi_init_pp_ofdm1_ral_and_qsmon(palHandle)) { CPPI_ERR("cppi_init_pp_ofdm1_ral_and_qsmon [CPPI41_DOMAIN_PP] FAILED\n"); return -1; } return 0; } int Puma_DOCSIS_CPPI_Init(void) { PAL_Handle palHandle; Cppi4BufPool tmpBufPool; Uint32 i; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; Uint32 descCount; Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; Uint32 dmaNum; Uint32 chNum; /* ------------------------------------------------------------------------------------- ######## ###### ###### ######## ####### ## ## ### #### ## ## ## ## ## ## ## ## ## ## ## ## ### ### ## ## ## ### ## ## ## ## ## ## ## ## ## #### #### ## ## ## #### ## ## ## ###### ## #### ## ## ## ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ######### ## ## #### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ### ######## ###### ###### ######## ####### ## ## ## ## #### ## ## ------------------------------------------------------------------------------------- */ PAL_osMemSet(&gCppiDsgInitCfg, 0, sizeof(gCppiDsgInitCfg)); #ifdef CONFIG_CPPI_DEBUG_API gCppiDsgInitCfg.debugToolBind = cppi_dsg_proc_init; #endif /******************************/ /******************************/ /* Buffer Manager Information */ /******************************/ /******************************/ gCppiDsgInitCfg.bufMgrBase[PAL_CPPI_OFDM0_BUF_MGR] = (CSL_BufMgr_RegsOvly)PAL_CPPI_OFDM0_BUF_MGR_BASE; gCppiDsgInitCfg.bufMgrBase[PAL_CPPI_OFDM1_BUF_MGR] = (CSL_BufMgr_RegsOvly)PAL_CPPI_OFDM1_BUF_MGR_BASE; gCppiDsgInitCfg.bufMgrBase[PAL_CPPI_SC_QAM0_BUF_MGR] = (CSL_BufMgr_RegsOvly)PAL_CPPI_SC_QAM0_BUF_MGR_BASE; /****************************************************/ /****************************************************/ /* Queue Managers + Descriptors Regions Information */ /****************************************************/ /****************************************************/ /* OFDM0 DSG */ gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].queueMgrRgnBase = (Ptr) PAL_CPPI_OFDM0_QUEUE_MGR_REGS_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].descMemRgnBase = (Ptr) PAL_CPPI_OFDM0_QUEUE_MGR_DESC_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].queueMgmtRgnBase = (Ptr) PAL_CPPI_OFDM0_QUEUE_MGR_QUEUES_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].queueStatusRgnBase = (Ptr) PAL_CPPI_OFDM0_QUEUE_MGR_Q_STATS_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].queueProxyRgnBase = NULL; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].totalQNum = PAL_CPPI_DSG_QMGR_TOTAL_Q_COUNT; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].LinkingRAM0Base = PAL_CPPI_DSG_QUEUE_MGR_LINKING_RAM_INTERNAL_ADDRESS; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].LinkingRAM0Size = PAL_CPPI_OFDM0_QUEUE_MGR_LINKING_RAM_SIZE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].base = (Ptr)PAL_CPPI_DSG_DESC_RAM_INTERNAL_ADDRESS; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].szDesc = PAL_CPPI_DS_DSG_FD_EMB_DESC_SIZE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].numDesc = PAL_CPPI_OFDM0_FD_EMB_DESC_COUNT; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM0_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].isOnChip = 1; /* OFDM1 DSG */ gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].queueMgrRgnBase = (Ptr) PAL_CPPI_OFDM1_QUEUE_MGR_REGS_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].descMemRgnBase = (Ptr) PAL_CPPI_OFDM1_QUEUE_MGR_DESC_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].queueMgmtRgnBase = (Ptr) PAL_CPPI_OFDM1_QUEUE_MGR_QUEUES_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].queueStatusRgnBase = (Ptr) PAL_CPPI_OFDM1_QUEUE_MGR_Q_STATS_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].queueProxyRgnBase = NULL; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].totalQNum = PAL_CPPI_DSG_QMGR_TOTAL_Q_COUNT; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].LinkingRAM0Base = PAL_CPPI_DSG_QUEUE_MGR_LINKING_RAM_INTERNAL_ADDRESS; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].LinkingRAM0Size = PAL_CPPI_OFDM1_QUEUE_MGR_LINKING_RAM_SIZE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].base = (Ptr)PAL_CPPI_DSG_DESC_RAM_INTERNAL_ADDRESS; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].szDesc = PAL_CPPI_DS_DSG_FD_EMB_DESC_SIZE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].numDesc = PAL_CPPI_OFDM1_FD_EMB_DESC_COUNT; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_OFDM1_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].isOnChip = 1; /* SC-QAMs DSG */ gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].queueMgrRgnBase = (Ptr) PAL_CPPI_SC_QAM0_QUEUE_MGR_REGS_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].descMemRgnBase = (Ptr) PAL_CPPI_SC_QAM0_QUEUE_MGR_DESC_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].queueMgmtRgnBase = (Ptr) PAL_CPPI_SC_QAM0_QUEUE_MGR_QUEUES_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].queueStatusRgnBase = (Ptr) PAL_CPPI_SC_QAM0_QUEUE_MGR_Q_STATS_BASE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].queueProxyRgnBase = NULL; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].totalQNum = PAL_CPPI_DSG_QMGR_TOTAL_Q_COUNT; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].LinkingRAM0Base = PAL_CPPI_DSG_QUEUE_MGR_LINKING_RAM_INTERNAL_ADDRESS; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].LinkingRAM0Size = PAL_CPPI_SC_QAM0_QUEUE_MGR_LINKING_RAM_SIZE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].base = (Ptr)PAL_CPPI_DSG_DESC_RAM_INTERNAL_ADDRESS; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].szDesc = PAL_CPPI_DS_DSG_FD_EMB_DESC_SIZE; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].numDesc = PAL_CPPI_SC_QAM0_FD_EMB_DESC_COUNT; gCppiDsgInitCfg.queueMgrInfo[PAL_CPPI_SC_QAM0_QUEUE_MGR].descRegion[PAL_CPPI_DSG_FD_EMB_DESC_REGION].isOnChip = 1; /********/ /********/ /* DMAs */ /********/ /********/ gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM0_RX_DMA].globalCtrlBase = (Ptr)PAL_CPPI_OFDM0_RX_DMA_GLOBAL_CTRL_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM0_RX_DMA].chCtrlStatusBase = (Ptr)PAL_CPPI_OFDM0_RX_DMA_CH_CFG_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM0_RX_DMA].schedCtrlBase = (Ptr)PAL_CPPI_OFDM0_RX_DMA_SCHEDULER_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM0_RX_DMA].tdFQueue.qMgr = PAL_CPPI_OFDM0_QUEUE_MGR; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM0_RX_DMA].tdFQueue.qNum = PAL_CPPI_DSG_QMGR_TEARDOWN_Q_NUM; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM0_TX_DMA].globalCtrlBase = (Ptr)PAL_CPPI_OFDM0_TX_DMA_GLOBAL_CTRL_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM0_TX_DMA].chCtrlStatusBase = (Ptr)PAL_CPPI_OFDM0_TX_DMA_CH_CFG_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM0_TX_DMA].schedCtrlBase = (Ptr)PAL_CPPI_OFDM0_TX_DMA_SCHEDULER_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM0_TX_DMA].tdFQueue.qMgr = PAL_CPPI_OFDM0_QUEUE_MGR; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM0_TX_DMA].tdFQueue.qNum = PAL_CPPI_DSG_QMGR_TEARDOWN_Q_NUM; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM1_RX_DMA].globalCtrlBase = (Ptr)PAL_CPPI_OFDM1_RX_DMA_GLOBAL_CTRL_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM1_RX_DMA].chCtrlStatusBase = (Ptr)PAL_CPPI_OFDM1_RX_DMA_CH_CFG_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM1_RX_DMA].schedCtrlBase = (Ptr)PAL_CPPI_OFDM1_RX_DMA_SCHEDULER_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM1_RX_DMA].tdFQueue.qMgr = PAL_CPPI_OFDM1_QUEUE_MGR; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM1_RX_DMA].tdFQueue.qNum = PAL_CPPI_DSG_QMGR_TEARDOWN_Q_NUM; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM1_TX_DMA].globalCtrlBase = (Ptr)PAL_CPPI_OFDM1_TX_DMA_GLOBAL_CTRL_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM1_TX_DMA].chCtrlStatusBase = (Ptr)PAL_CPPI_OFDM1_TX_DMA_CH_CFG_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM1_TX_DMA].schedCtrlBase = (Ptr)PAL_CPPI_OFDM1_TX_DMA_SCHEDULER_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM1_TX_DMA].tdFQueue.qMgr = PAL_CPPI_OFDM1_QUEUE_MGR; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_OFDM1_TX_DMA].tdFQueue.qNum = PAL_CPPI_DSG_QMGR_TEARDOWN_Q_NUM; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_SC_QAM0_RX_DMA].globalCtrlBase = (Ptr)PAL_CPPI_SC_QAM0_RX_DMA_GLOBAL_CTRL_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_SC_QAM0_RX_DMA].chCtrlStatusBase = (Ptr)PAL_CPPI_SC_QAM0_RX_DMA_CH_CFG_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_SC_QAM0_RX_DMA].schedCtrlBase = (Ptr)PAL_CPPI_SC_QAM0_RX_DMA_SCHEDULER_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_SC_QAM0_RX_DMA].tdFQueue.qMgr = PAL_CPPI_SC_QAM0_QUEUE_MGR; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_SC_QAM0_RX_DMA].tdFQueue.qNum = PAL_CPPI_DSG_QMGR_TEARDOWN_Q_NUM; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_SC_QAM0_TX_DMA].globalCtrlBase = (Ptr)PAL_CPPI_SC_QAM0_TX_DMA_GLOBAL_CTRL_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_SC_QAM0_TX_DMA].chCtrlStatusBase = (Ptr)PAL_CPPI_SC_QAM0_TX_DMA_CH_CFG_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_SC_QAM0_TX_DMA].schedCtrlBase = (Ptr)PAL_CPPI_SC_QAM0_TX_DMA_SCHEDULER_BASE; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_SC_QAM0_TX_DMA].tdFQueue.qMgr = PAL_CPPI_SC_QAM0_QUEUE_MGR; gCppiDsgInitCfg.dmaBlock[PAL_CPPI_SC_QAM0_TX_DMA].tdFQueue.qNum = PAL_CPPI_DSG_QMGR_TEARDOWN_Q_NUM; palHandle = PAL_cppi4Init(&gCppiDsgInitCfg, (Ptr)CPPI41_DOMAIN_DSG); if(palHandle == NULL) { CPPI_ERR("PAL_cppi4Init of CPPI41_DOMAIN_DSG failed!\n"); return 0; } CPPI_INFO("PAL_cppi4Init of CPPI41_DOMAIN_DSG initialized successfully\n"); /*************************************************************************/ /*********** Init DSG buffer pools used in the system ********************/ /*************************************************************************/ /* OFDM0 DSG Buffer Pool init */ tmpBufPool.bPool = PAL_CPPI_OFDM0_BUFFER_POOL00; tmpBufPool.bMgr = PAL_CPPI_OFDM0_BUF_MGR; if ((PAL_cppi4BufPoolDirectInit(palHandle, tmpBufPool, PAL_CPPI_DS_DSG_BUFFER_POOL00_REF_CNT, PAL_CPPI_DS_DSG_BUFFER_POOL00_BUF_SIZE, PAL_CPPI_OFDM0_BUFFER_POOL00_BUF_COUNT, (Ptr)PAL_CPPI_OFDM0_BUFFER_RAM_INTERNAL_ADDRESS)) == NULL) { CPPI_ERR("PAL_cppi4BufPoolDirectInit for pool %d [CPPI41_DOMAIN_DSG] FAILED\n", tmpBufPool.bPool); return -1; } /* OFDM1 DSG Buffer Pool init */ tmpBufPool.bPool = PAL_CPPI_OFDM1_BUFFER_POOL00; tmpBufPool.bMgr = PAL_CPPI_OFDM1_BUF_MGR; if ((PAL_cppi4BufPoolDirectInit(palHandle, tmpBufPool, PAL_CPPI_DS_DSG_BUFFER_POOL00_REF_CNT, PAL_CPPI_DS_DSG_BUFFER_POOL00_BUF_SIZE, PAL_CPPI_OFDM1_BUFFER_POOL00_BUF_COUNT, (Ptr)PAL_CPPI_OFDM1_BUFFER_RAM_INTERNAL_ADDRESS)) == NULL) { CPPI_ERR("PAL_cppi4BufPoolDirectInit for pool %d [CPPI41_DOMAIN_DSG] FAILED\n", tmpBufPool.bPool); return -1; } /* SC-QAM DSG Buffer Pool init */ tmpBufPool.bPool = PAL_CPPI_SC_QAM0_BUFFER_POOL00; tmpBufPool.bMgr = PAL_CPPI_SC_QAM0_BUF_MGR; if ((PAL_cppi4BufPoolDirectInit(palHandle, tmpBufPool, PAL_CPPI_DS_DSG_BUFFER_POOL00_REF_CNT, PAL_CPPI_DS_DSG_BUFFER_POOL00_BUF_SIZE, PAL_CPPI_SC_QAM0_BUFFER_POOL00_BUF_COUNT, (Ptr)PAL_CPPI_SC_QAM0_BUFFER_RAM_INTERNAL_ADDRESS)) == NULL) { CPPI_ERR("PAL_cppi4BufPoolDirectInit for pool %d [CPPI41_DOMAIN_DSG] FAILED\n", tmpBufPool.bPool); return -1; } /****************************************************/ /*********** Setup DSG descriptors ******************/ /****************************************************/ for (i = 0; i < ARRAY_SIZE(gDsgFDqueues); i++) /* Go over all free decriptors queues list */ { DsgCppiDescType_t* currDesc = NULL; switch (gDsgFDqueues[i].qMgr) { case PAL_CPPI_OFDM0_QUEUE_MGR: currDesc = (DsgCppiDescType_t *)PAL_CPPI_OFDM0_DESC_RAM_BASE; break; case PAL_CPPI_OFDM1_QUEUE_MGR: currDesc = (DsgCppiDescType_t *)PAL_CPPI_OFDM1_DESC_RAM_BASE; break; case PAL_CPPI_SC_QAM0_QUEUE_MGR: currDesc = (DsgCppiDescType_t *)PAL_CPPI_SC_QAM0_DESC_RAM_BASE; break; default: CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d index %d FAILED\n",gDsgFDqueues[i].qMgr,i); return -1; } tmpQ.qMgr = gDsgFDqueues[i].qMgr; tmpQ.qNum = gDsgFDqueues[i].qId; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_DSG] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return 0; } memset((void *)currDesc, 0, gDsgFDqueues[i].descSize * gDsgFDqueues[i].descCount); for (descCount = 0; descCount < gDsgFDqueues[i].descCount; descCount++) { currDesc->hw.descInfo = CPPI41_EM_DESCINFO_DTYPE_EMBEDDED | (PAL_CPPI_DSG_PSI_SIZE << CPPI41_EM_DESCINFO_PSWSIZE_SHIFT); currDesc->hw.tagInfo = 0; currDesc->hw.pktInfo = (1 << CPPI41_EM_PKTINFO_RETPOLICY_SHIFT) | (1 << CPPI41_EM_PKTINFO_ONCHIP_SHIFT) | (0 << CPPI41_EM_PKTINFO_RETQMGR_SHIFT) | (tmpQ.qNum << CPPI41_EM_PKTINFO_RETQ_SHIFT); currDesc->psi[0] = DS_EMBEDDED_DESC_BPI_CMD_TEMPLATE; currDesc->psi[1] = DS_EMBEDDED_DESC_CRC_CMD_TEMPLATE; currDesc->psi[2] = DS_EMBEDDED_DESC_PHS_CMD_TEMPLATE; currDesc->psi[3] = DS_EMBEDDED_DESC_RX_FIFO_0_CMD_TEMPLATE; currDesc->psi[4] = DS_EMBEDDED_DESC_RX_FIFO_1_CMD_TEMPLATE; PAL_CPPI4_CACHE_WRITEBACK(currDesc, gDsgFDqueues[i].descSize); PAL_cppi4QueuePush(tmpQHnd, (Ptr)DSG_INTERNAL_OFFSET((Uint32)currDesc), PAL_CPPI4_DESCSIZE_2_QMGRSIZE(gDsgFDqueues[i].descSize), 0); currDesc = (DsgCppiDescType_t*)((Uint32)currDesc + gDsgFDqueues[i].descSize); } } /*******************************************************/ /*********** Setup DSG RX DMA channels *****************/ /*******************************************************/ for (dmaNum = PAL_CPPI_OFDM0_RX_DMA; dmaNum <= PAL_CPPI_SC_QAM0_RX_DMA; dmaNum++) { tmpBufPool.bMgr = 0; // DSG has to see it as 0 always. for (chNum = 0; chNum < PAL_CPPI_DSG_NUM_TOTAL_CHAN; chNum++) { rxCh.chNum = chNum; rxCh.dmaNum = dmaNum; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.sopOffset = 0; rxCh.rxCompQueue.qMgr = PAL_CPPI_DMA_NUM_TO_QMGR_NUM(dmaNum); rxCh.rxCompQueue.qNum = PAL_CPPI_DSG_QMGR_Q_0; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_DMA_NUM_TO_QMGR_NUM(dmaNum); rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_DSG_QMGR_FD_EMB_Q_NUM; rxCh.u.embeddedPktCfg.numBufSlot = (EMSLOTCNT - 1); rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxCh.u.embeddedPktCfg.fBufPool[0] = tmpBufPool; rxCh.u.embeddedPktCfg.fBufPool[1] = tmpBufPool; rxCh.u.embeddedPktCfg.fBufPool[2] = tmpBufPool; rxCh.u.embeddedPktCfg.fBufPool[3] = tmpBufPool; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } PAL_cppi4EnableRxChannel(rxChHdl, NULL); CPPI_DBG("Open and enable dmaNum=%d, rxChNum=%d\n", dmaNum, rxCh.chNum); } } /*******************************************************/ /*********** Setup DSG TX DMA channels *****************/ /*******************************************************/ for (dmaNum = PAL_CPPI_OFDM0_TX_DMA; dmaNum <= PAL_CPPI_SC_QAM0_TX_DMA; dmaNum++) { txCh.chNum = 0; txCh.dmaNum = dmaNum; txCh.tdQueue.qMgr = PAL_CPPI_DMA_NUM_TO_QMGR_NUM(dmaNum); txCh.tdQueue.qNum = PAL_CPPI_DSG_QMGR_TEARDOWN_Q_NUM; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } PAL_cppi4EnableTxChannel(txChHdl, NULL); CPPI_DBG("Open and enable dmaNum=%d, txChNum=%d\n", dmaNum, txCh.chNum); } /* ---------------------------------------------------------------------------- ## ## ###### ######## ####### ## ## ### #### ## ## ## ## ## ## ## ## ## ## ### ### ## ## ## ### ## ## ## ## ## ## ## ## #### #### ## ## ## #### ## ## ## ###### ## ## ## ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ######### ## ## #### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ### ####### ###### ######## ####### ## ## ## ## #### ## ## ---------------------------------------------------------------------------- The DOCSIS US Domain related initializatios are in docsis_cppi_puma7 module. */ /* ---------------------------------------------------------------------------- ######## ######## ######## ####### ## ## ### #### ## ## ## ## ## ## ## ## ## ## ### ### ## ## ## ### ## ## ## ## ## ## ## ## ## #### #### ## ## ## #### ## ######## ######## ## ## ## ## ## ### ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ######### ## ## #### ## ## ## ## ## ## ## ## ## ## ## ## ### ## ## ######## ####### ## ## ## ## #### ## ## ---------------------------------------------------------------------------- */ palHandle = PAL_cppi4Init(NULL, CPPI41_DOMAIN_PP); /* No need to initialize buffer pools and free queues since they are shared and were already initialized */ if (cppi_init_pp_docsis_dma_channels(palHandle)) { CPPI_ERR("cppi_init_pp_docsis_dma_channels FAILED\n"); return (-1); } return 0; } int get_dma_state(struct Puma7_cppi_dma_block_state dma_state[PAL_CPPI41_NUM_DMA_BLOCK]) { PAL_Handle palHandle = PAL_cppi4Init(&gCppiPpInitCfg, CPPI41_DOMAIN_PP); PAL_CPPI_PP_DMA_BLOCKS_e dma_block; u32 channels_bitmap; if(!palHandle) { CPPI_ERR("PAL_cppi4Init of CPPI41_DOMAIN_PP failed!\n"); return -1; } /* Get channels status for each DMA block. */ for (dma_block = 0; dma_block < PAL_CPPI41_NUM_DMA_BLOCK; dma_block++) { if (PAL_cppi4GetDmaState(palHandle, dma_block, &channels_bitmap) != PAL_SOK) return -1; dma_state[dma_block].channels_bitmap = channels_bitmap; } return 0; } EXPORT_SYMBOL(get_dma_state); void set_dma_status(PAL_CPPI_PP_DMA_BLOCKS_e dma_number, Bool enable) { PAL_Handle palHandle = PAL_cppi4Init(&gCppiPpInitCfg, CPPI41_DOMAIN_PP); if(!palHandle) { CPPI_ERR("PAL_cppi4Init of CPPI41_DOMAIN_PP failed!\n"); return; } switch (dma_number) { case PAL_CPPI_PP_DMA03_SGMII0_RX: set_pp_sgmii0_rx_dma_channels(palHandle, enable); break; case PAL_CPPI_PP_DMA04_SGMII1_RX: set_pp_sgmii1_rx_dma_channels(palHandle, enable); break; case PAL_CPPI_PP_DMA05_RGMII0_RX: set_pp_rgmii0_rx_dma_channels_status(palHandle, enable); break; case PAL_CPPI_PP_DMA06_MoCA_RX_TX: set_pp_moca_rx_dma_channels(palHandle, enable); set_pp_moca_tx_dma_channels(palHandle, enable); break; case PAL_CPPI_PP_DMA07_ATOM_RX_TX: set_pp_atom_rx_dma_channels(palHandle, enable); set_pp_atom_tx_dma_channels(palHandle, enable); break; case PAL_CPPI_PP_DMA08_RX_TX_INFRA_WIFI_PROXY_RX_TX: case PAL_CPPI_PP_DMA09_INFRA_RX_TX: case PAL_CPPI_PP_DMA10_INFRA_RX_TX: case PAL_CPPI_PP_DMA11_INFRA_RX_TX: CPPI_INFO("DMA %d is not used, can't enable/disable\n", dma_number); break; case PAL_CPPI_PP_DMA14_SGMII0_TX: set_pp_sgmii0_tx_dma_channels(palHandle, enable); break; case PAL_CPPI_PP_DMA15_SGMII1_TX: set_pp_sgmii1_tx_dma_channels(palHandle, enable); break; case PAL_CPPI_PP_DMA16_RGMII0_TX: set_pp_rgmii0_tx_dma_channels(palHandle, enable); break; case PAL_CPPI_PP_DMA23_RGMII1_RX_TX: set_pp_rgmii1_rx_dma_channels(palHandle, enable); set_pp_rgmii1_tx_dma_channels(palHandle, enable); break; case PAL_CPPI_PP_DMA00_OFDM0_RX: case PAL_CPPI_PP_DMA01_OFDM1_RX: case PAL_CPPI_PP_DMA02_SC_QAM_RX: case PAL_CPPI_PP_DMA12_OFDM0_TX_QAM_0_3_TX: case PAL_CPPI_PP_DMA13_OFDM1_TX_QAM_4_7_TX: case PAL_CPPI_PP_DMA21_US_COP_RX: case PAL_CPPI_PP_DMA22_US_COP_TX: CPPI_INFO("DMA %d is not used, can't enable/disable\n", dma_number); break; default: CPPI_ERR("{ %u } is illegal DMA number\n", dma_number); } } EXPORT_SYMBOL(set_dma_status); #ifdef CONFIG_INTEL_KERNEL_VOICE_SUPPORT int Puma_VoiceDSP_CPPI_Init(void) { PAL_Handle palHandle; Uint32 i; Cppi4Queue tmpQ; PAL_Cppi4QueueHnd tmpQHnd; Ptr currDescRegionPtr; Uint32 descCount; Cppi4BufPool tmpBufPool; Cppi4TxChInitCfg txCh; Cppi4RxChInitCfg rxCh; PAL_Cppi4TxChHnd txChHdl; PAL_Cppi4RxChHnd rxChHdl; currDescRegionPtr = NULL; palHandle = PAL_cppi4Init(NULL, CPPI41_DOMAIN_PP); if(palHandle == NULL) { CPPI_ERR("PAL_cppi4Init FAILED\n"); return -1; } /**********************************************/ /******** Setup VOICE DSP descriptors *********/ /**********************************************/ for (i = 0; i < ARRAY_SIZE(gPpFDqueues); i++) /* Go over all free decriptors queues list */ { if (gPpFDqueues[i].descRegion == PAL_CPPI_PP_VOICE_GLOBAL_DESC_REGION) { if (PAL_cppi4IsDescRegionAllocated(palHandle, gPpFDqueues[i].qMgr, gPpFDqueues[i].descRegion) == False) { /* This is the first queue within this region - allocate all the region now */ currDescRegionPtr = PAL_cppi4AllocDescRegion(palHandle, gPpFDqueues[i].qMgr, gPpFDqueues[i].descRegion); if (currDescRegionPtr == NULL) { CPPI_ERR("Descriptor region %d allocation FAILED\n", gPpFDqueues[i].descRegion); return -1; } currDescRegionPtr = (Ptr)avalanche_no_OperSys_memory_phys_to_virt((uintptr_t)currDescRegionPtr); descCount = gCppiPpInitCfg.queueMgrInfo[gPpFDqueues[i].qMgr].descRegion[gPpFDqueues[i].descRegion].numDesc; PAL_osMemSet(currDescRegionPtr, 0, descCount * gPpFDqueues[i].descSize); CPPI_DBG("Descriptor region %d allocation, base address = %p, descCount = %d\n", gPpFDqueues[i].descRegion, currDescRegionPtr, descCount); #ifdef CONFIG_AVM_CPPI_DEBUG { FDqueue_t *fdq = &gPpFDqueues[i]; uintptr_t uip = ((uintptr_t*)currDescRegionPtr)[fdq->descRegion]; Ptr start = (Ptr)uip; Ptr end = start + descCount * fdq->descSize; pr_info("CPPI: Descriptor region %2d: %p-%p %5lu\n", fdq->descRegion, start, end, (unsigned long)descCount); } #endif } tmpQ.qMgr = gPpFDqueues[i].qMgr; tmpQ.qNum = gPpFDqueues[i].qId; tmpQHnd = PAL_cppi4QueueOpen(palHandle, tmpQ); if (tmpQHnd == NULL) { CPPI_ERR("PAL_cppi4QueueOpen for qMgr %d, qNum %d [CPPI41_DOMAIN_PP] FAILED\n", tmpQ.qMgr, tmpQ.qNum); return -1; } if (currDescRegionPtr == NULL) { CPPI_ERR("Descriptor region %d allocation FAILED currDescRegionPtr = NULL \n", gPpFDqueues[i].descRegion); return -1; } for (descCount = 0; descCount < gPpFDqueues[i].descCount; descCount++) { Cppi4EmbdDescPp* currDesc = (Cppi4EmbdDescPp*)currDescRegionPtr; currDesc->descInfo = CPPI41_EM_DESCINFO_DTYPE_EMBEDDED | CPPI41_EM_DESCINFO_SLOTCNT_PP; currDesc->tagInfo = (PAL_CPPI_PP_VOICE_DSP_C55_SOURCE_PORT << CPPI41_EM_TAGINFO_SRCPORT_SHIFT) | 0x3fff; currDesc->pktInfo = (PAL_CPPI4_HOSTDESC_PKT_TYPE_ETH << CPPI41_EM_PKTINFO_PKTTYPE_SHIFT) | CPPI41_EM_PKTINFO_RETPOLICY_RETURN | (tmpQ.qMgr << CPPI41_EM_PKTINFO_RETQMGR_SHIFT) | (tmpQ.qNum << CPPI41_EM_PKTINFO_RETQ_SHIFT); PAL_CPPI4_CACHE_WRITEBACK(currDesc, gPpFDqueues[i].descSize); PAL_cppi4QueuePush(tmpQHnd, (Ptr)avalanche_no_OperSys_memory_virt_to_phys((Uint32)currDesc), PAL_CPPI4_DESCSIZE_2_QMGRSIZE(gPpFDqueues[i].descSize), 0); currDescRegionPtr = (Ptr)((Uint32)currDescRegionPtr + gPpFDqueues[i].descSize); } } } /*****************************************************/ /*********** Init VOICE DSP buffer pool **************/ /*****************************************************/ { Uint32* poolPhysAddr; if (avalanche_alloc_no_OperSys_memory(eNO_OperSys_VoiceNI, b_pool_count[PAL_CPPI_PP_VOICE_DSP_BUFFER_POOL] * PAL_CPPI_PP_VOICE_DSP_BUFFER_SIZE, (unsigned int *)&poolPhysAddr)) { CPPI_ERR("avalanche_alloc_no_OperSys_memory for buffer pool FAILED\n"); return -1; } memset((void *)avalanche_no_OperSys_memory_phys_to_virt((u32)poolPhysAddr), 0, b_pool_count[PAL_CPPI_PP_VOICE_DSP_BUFFER_POOL] * PAL_CPPI_PP_VOICE_DSP_BUFFER_SIZE); tmpBufPool.bMgr = PAL_CPPI_PP_BUF_MGR; tmpBufPool.bPool = PAL_CPPI_PP_VOICE_DSP_BUFFER_POOL; if (NULL == PAL_cppi4BufPoolDirectInit(palHandle, tmpBufPool,PAL_CPPI_PP_VOICE_DSP_BUFFER_REF_CNT, PAL_CPPI_PP_VOICE_DSP_BUFFER_SIZE, b_pool_count[PAL_CPPI_PP_VOICE_DSP_BUFFER_POOL], (void*)poolPhysAddr)) { CPPI_ERR("PAL_cppi4BufPoolDirectInit for pool %d FAILED\n", tmpBufPool.bPool); return -1; } } /****************************/ /* Setup VOICE DMA Channels */ /****************************/ /* Set up Rx channel */ rxCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; rxCh.chNum = PAL_CPPI_PP_DMA10_VOICE_DSP_INFRA_RX_CH; rxCh.defDescType = CPPI41_DESC_TYPE_EMBEDDED; rxCh.sopOffset = 0; rxCh.rxCompQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.rxCompQueue.qNum = PAL_CPPI_PP_QMGR_G2_VOICE_DSP_TX_QNUM; rxCh.u.embeddedPktCfg.fdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; rxCh.u.embeddedPktCfg.fdQueue.qNum = PAL_CPPI_PP_QMGR_G2_VOICE_INFRA_RX_EMB_FD_Q_NUM; if (get_bPool_info(&rxCh.u.embeddedPktCfg.fdQueue, &rxCh.u.embeddedPktCfg.fBufPool[0])) return -1; rxCh.u.embeddedPktCfg.numBufSlot = EMSLOTCNT_PP - 1; rxCh.u.embeddedPktCfg.sopSlotNum = 0; rxChHdl = PAL_cppi4RxChOpen(palHandle, &rxCh, NULL); if (!rxChHdl) { CPPI_ERR("PAL_cppi4RxChOpen failed for dmaNum=%d, txChNum=%d\n", rxCh.dmaNum, rxCh.chNum); return -1; } /* Set up Tx channel */ txCh.dmaNum = PAL_CPPI_PP_DMA10_INFRA_RX_TX; txCh.chNum = PAL_CPPI_PP_DMA10_VOICE_DSP_INFRA_TX_CH; txCh.tdQueue.qMgr = PAL_CPPI_PP_QMGR_G2; txCh.tdQueue.qNum = PAL_CPPI_PP_QMGR_G2_TEARDOWN_FD_Q_NUM; txChHdl = PAL_cppi4TxChOpen(palHandle, &txCh, NULL); if (!txChHdl) { CPPI_ERR("PAL_cppi4TxChOpen failed for dmaNum=%d, txChNum=%d\n", txCh.dmaNum, txCh.chNum); return -1; } /* Enable Tx-Rx channels */ PAL_cppi4EnableRxChannel(rxChHdl, NULL); PAL_cppi4EnableTxChannel(txChHdl, NULL); return 0; } #endif core_param(memProfile, memProfile, int, 0644); EXPORT_SYMBOL(Puma_DOCSIS_CPPI_Init); #ifdef CONFIG_INTEL_KERNEL_VOICE_SUPPORT EXPORT_SYMBOL(Puma_VoiceDSP_CPPI_Init); #endif