/* * * gpio_northwest_registers.h * Description: * SPI utility header. * * * GPL LICENSE SUMMARY * * Copyright(c) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. * The full GNU General Public License is included in this distribution * in the file called LICENSE.GPL. * * Contact Information: * Intel Corporation * 2200 Mission College Blvd. * Santa Clara, CA 97052 */ #ifndef GPIO_NW_REG #define GPIO_NW_REG /***************************************************************** */ /*! UART */ /***************************************************************** */ /*BBU*/ #define GPIO_NORTHWEST_REGISTERS_BBU_UART_CTS_B_PAD_CFG0_MSGREGADDR 0x4C58 #define GPIO_NORTHWEST_REGISTERS_BBU_UART_CTS_B_PAD_CFG1_MSGREGADDR 0x4C5C #define GPIO_NORTHWEST_REGISTERS_BBU_UART_RTS_B_PAD_CFG0_MSGREGADDR 0x4C50 #define GPIO_NORTHWEST_REGISTERS_BBU_UART_RTS_B_PAD_CFG1_MSGREGADDR 0x4C54 #define GPIO_NORTHWEST_REGISTERS_BBU_UART_RX_PAD_CFG0_MSGREGADDR 0x4C40 #define GPIO_NORTHWEST_REGISTERS_BBU_UART_RX_PAD_CFG1_MSGREGADDR 0x4C44 #define GPIO_NORTHWEST_REGISTERS_BBU_UART_TX_PAD_CFG0_MSGREGADDR 0x4C30 #define GPIO_NORTHWEST_REGISTERS_BBU_UART_TX_PAD_CFG1_MSGREGADDR 0x4C34 /***************************************************************** */ /*! I2C */ /***************************************************************** */ /*I2C0*/ #define GPIO_NORTHWEST_REGISTERS_I2C0_SCL_PAD_CFG0_MSGREGADDR 0x4850 #define GPIO_NORTHWEST_REGISTERS_I2C0_SCL_PAD_CFG1_MSGREGADDR 0x4854 #define GPIO_NORTHWEST_REGISTERS_I2C0_SDA_PAD_CFG0_MSGREGADDR 0x4858 #define GPIO_NORTHWEST_REGISTERS_I2C0_SDA_PAD_CFG1_MSGREGADDR 0x485C /*I2C1*/ #define GPIO_NORTHWEST_REGISTERS_I2C1_SDA_PAD_CFG0_MSGREGADDR 0x4800 #define GPIO_NORTHWEST_REGISTERS_I2C1_SDA_PAD_CFG1_MSGREGADDR 0x4804 #define GPIO_NORTHWEST_REGISTERS_I2C1_SCL_PAD_CFG0_MSGREGADDR 0x4808 #define GPIO_NORTHWEST_REGISTERS_I2C1_SCL_PAD_CFG1_MSGREGADDR 0x480C /***************************************************************** */ /*! SPI */ /***************************************************************** */ /*RF FE*/ #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_CLK_PAD_CFG0_MSGREGADDR 0x4438 #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_CLK_PAD_CFG1_MSGREGADDR 0x443C #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_CS0_PAD_CFG0_MSGREGADDR 0x4468 #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_CS0_PAD_CFG1_MSGREGADDR 0x446C #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_CS1_PAD_CFG0_MSGREGADDR 0x4450 #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_CS1_PAD_CFG1_MSGREGADDR 0x4454 #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_MISO_PAD_CFG0_MSGREGADDR 0x4448 #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_MISO_PAD_CFG1_MSGREGADDR 0x444C #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_MOSI_PAD_CFG0_MSGREGADDR 0x4478 #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_MOSI_PAD_CFG1_MSGREGADDR 0x447C #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_INT_PAD_CFG0_MSGREGADDR 0x4420 #define GPIO_NORTHWEST_REGISTERS_RF_FE_SPI_INT_PAD_CFG1_MSGREGADDR 0x4424 /*EPGA*/ #define GPIO_NORTHWEST_REGISTERS_EPGA_CLK_PAD_CFG0_MSGREGADDR 0x4818 #define GPIO_NORTHWEST_REGISTERS_EPGA_CLK_PAD_CFG1_MSGREGADDR 0x481C #define GPIO_NORTHWEST_REGISTERS_EPGA_PWDN_N_PAD_CFG0_MSGREGADDR 0x4828 #define GPIO_NORTHWEST_REGISTERS_EPGA_PWDN_N_PAD_CFG1_MSGREGADDR 0x482C #define GPIO_NORTHWEST_REGISTERS_EPGA_WE_N_PAD_CFG0_MSGREGADDR 0x4848 #define GPIO_NORTHWEST_REGISTERS_EPGA_WE_N_PAD_CFG1_MSGREGADDR 0x484C #define GPIO_NORTHWEST_REGISTERS_EPGA_DATA_PAD_CFG0_MSGREGADDR 0x4838 #define GPIO_NORTHWEST_REGISTERS_EPGA_DATA_PAD_CFG1_MSGREGADDR 0x483C /***************************************************************** */ /*! BBU */ /***************************************************************** */ #define GPIO_NORTHWEST_REGISTERS_BATTERY_PWM_PAD_CFG0_MSGREGADDR 0x4C10 #define GPIO_NORTHWEST_REGISTERS_BATTERY_PWM_PAD_CFG1_MSGREGADDR 0x4C14 #define GPIO_NORTHWEST_REGISTERS_BBU_ENABLE_1_PAD_CFG0_MSGREGADDR 0x4C48 #define GPIO_NORTHWEST_REGISTERS_BBU_ENABLE_1_PAD_CFG1_MSGREGADDR 0x4C4C #define GPIO_NORTHWEST_REGISTERS_BBU_ENABLE_2_PAD_CFG0_MSGREGADDR 0x4C28 #define GPIO_NORTHWEST_REGISTERS_BBU_ENABLE_2_PAD_CFG1_MSGREGADDR 0x4C2C #define GPIO_NORTHWEST_REGISTERS_ONE_WIRE_EPROM1_PAD_CFG0_MSGREGADDR 0x4C20 #define GPIO_NORTHWEST_REGISTERS_ONE_WIRE_EPROM1_PAD_CFG1_MSGREGADDR 0x4C24 #define GPIO_NORTHWEST_REGISTERS_ONE_WIRE_EPROM2_PAD_CFG0_MSGREGADDR 0x4C08 #define GPIO_NORTHWEST_REGISTERS_ONE_WIRE_EPROM2_PAD_CFG1_MSGREGADDR 0x4C0C /***************************************************************** */ /*! SGMII */ /***************************************************************** */ /*1*/ #define GPIO_NORTHWEST_REGISTERS_MPEG_RESET_PAD_CFG0_MSGREGADDR 0x4440 #define GPIO_NORTHWEST_REGISTERS_MPEG_RESET_PAD_CFG1_MSGREGADDR 0x4444 /***************************************************************** */ /*! NET PGIOs */ /***************************************************************** */ /*GPIO 0*/ #define GPIO_NORTHWEST_REGISTERS_RF_FE_SWITCH0_PAD_CFG0_MSGREGADDR 0x4460 #define GPIO_NORTHWEST_REGISTERS_RF_FE_SWITCH0_PAD_CFG1_MSGREGADDR 0x4464 /*GPIO 1*/ #define GPIO_NORTHWEST_REGISTERS_RF_FE_SWITCH1_PAD_CFG0_MSGREGADDR 0x4430 #define GPIO_NORTHWEST_REGISTERS_RF_FE_SWITCH1_PAD_CFG1_MSGREGADDR 0x4434 /*GPIO 2*/ #define GPIO_NORTHWEST_REGISTERS_MOCA_GPIO_PAD_CFG0_MSGREGADDR 0x4458 #define GPIO_NORTHWEST_REGISTERS_MOCA_GPIO_PAD_CFG1_MSGREGADDR 0x445C /*GPIO 3*/ #define GPIO_NORTHWEST_REGISTERS_MPEG_RESET_PAD_CFG0_MSGREGADDR 0x4440 #define GPIO_NORTHWEST_REGISTERS_MPEG_RESET_PAD_CFG1_MSGREGADDR 0x4444 /*GPIO 4*/ #define GPIO_NORTHWEST_REGISTERS_RF_FE_RESET_PAD_CFG0_MSGREGADDR 0x4418 #define GPIO_NORTHWEST_REGISTERS_RF_FE_RESET_PAD_CFG1_MSGREGADDR 0x441C /*GPIO 5*/ #define GPIO_NORTHWEST_REGISTERS_MOCA_RESET_PAD_CFG0_MSGREGADDR 0x4480 #define GPIO_NORTHWEST_REGISTERS_MOCA_RESET_PAD_CFG1_MSGREGADDR 0x4484 /*GPIO 6*/ #define GPIO_NORTHWEST_REGISTERS_MOCA_INT_PAD_CFG0_MSGREGADDR 0x4470 #define GPIO_NORTHWEST_REGISTERS_MOCA_INT_PAD_CFG1_MSGREGADDR 0x4474 #define GPIO_NORTHWEST_REGISTERS_LED_14_PAD_CFG0_MSGREGADDR 0x4840 #define GPIO_NORTHWEST_REGISTERS_LED_14_PAD_CFG1_MSGREGADDR 0x4844 /*GPIO 7*/ #define GPIO_NORTHWEST_REGISTERS_MPEG_INT_PAD_CFG0_MSGREGADDR 0x4428 #define GPIO_NORTHWEST_REGISTERS_MPEG_INT_PAD_CFG1_MSGREGADDR 0x442C #endif