/* * * gpio_southeast_registers.h * Description: * SPI utility header. * * * GPL LICENSE SUMMARY * * Copyright(c) 2015 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. * The full GNU General Public License is included in this distribution * in the file called LICENSE.GPL. * * Contact Information: * Intel Corporation * 2200 Mission College Blvd. * Santa Clara, CA 97052 */ #ifndef GPIO_SE_REG #define GPIO_SE_REG #define PUAM7_TS_MAX_NUMBER 7 /***************************************************************** */ /*! MPEG */ /***************************************************************** */ /*TS0*/ #define GPIO_SOUTHEAST_REGISTERS_TS0_CLK_PAD_CFG0_MSGREGADDR 0x5000 #define GPIO_SOUTHEAST_REGISTERS_TS0_CLK_PAD_CFG1_MSGREGADDR 0x5004 #define GPIO_SOUTHEAST_REGISTERS_TS0_SYNC_PAD_CFG0_MSGREGADDR 0x5010 #define GPIO_SOUTHEAST_REGISTERS_TS0_SYNC_PAD_CFG1_MSGREGADDR 0x5014 #define GPIO_SOUTHEAST_REGISTERS_TS0_DAV_PAD_CFG0_MSGREGADDR 0x5028 #define GPIO_SOUTHEAST_REGISTERS_TS0_DAV_PAD_CFG1_MSGREGADDR 0x502C #define GPIO_SOUTHEAST_REGISTERS_TS0_DATA_PAD_CFG0_MSGREGADDR 0x5030 #define GPIO_SOUTHEAST_REGISTERS_TS0_DATA_PAD_CFG1_MSGREGADDR 0x5034 /*TS1*/ #define GPIO_SOUTHEAST_REGISTERS_TS1_CLK_PAD_CFG0_MSGREGADDR 0x5040 #define GPIO_SOUTHEAST_REGISTERS_TS1_CLK_PAD_CFG1_MSGREGADDR 0x5044 #define GPIO_SOUTHEAST_REGISTERS_TS1_SYNC_PAD_CFG0_MSGREGADDR 0x5058 #define GPIO_SOUTHEAST_REGISTERS_TS1_SYNC_PAD_CFG1_MSGREGADDR 0x505C #define GPIO_SOUTHEAST_REGISTERS_TS1_DAV_PAD_CFG0_MSGREGADDR 0x5070 #define GPIO_SOUTHEAST_REGISTERS_TS1_DAV_PAD_CFG1_MSGREGADDR 0x5074 #define GPIO_SOUTHEAST_REGISTERS_TS1_DATA_PAD_CFG0_MSGREGADDR 0x5080 #define GPIO_SOUTHEAST_REGISTERS_TS1_DATA_PAD_CFG1_MSGREGADDR 0x5084 /*TS2*/ #define GPIO_SOUTHEAST_REGISTERS_TS2_CLK_PAD_CFG0_MSGREGADDR 0x5060 #define GPIO_SOUTHEAST_REGISTERS_TS2_CLK_PAD_CFG1_MSGREGADDR 0x5064 #define GPIO_SOUTHEAST_REGISTERS_TS2_DATA_PAD_CFG0_MSGREGADDR 0x5048 #define GPIO_SOUTHEAST_REGISTERS_TS2_DATA_PAD_CFG1_MSGREGADDR 0x504C #define GPIO_SOUTHEAST_REGISTERS_TS2_DAV_PAD_CFG0_MSGREGADDR 0x5068 #define GPIO_SOUTHEAST_REGISTERS_TS2_DAV_PAD_CFG1_MSGREGADDR 0x506C #define GPIO_SOUTHEAST_REGISTERS_TS2_SYNC_PAD_CFG0_MSGREGADDR 0x5078 #define GPIO_SOUTHEAST_REGISTERS_TS2_SYNC_PAD_CFG1_MSGREGADDR 0x507C /*TS3*/ #define GPIO_SOUTHEAST_REGISTERS_TS3_CLK_PAD_CFG0_MSGREGADDR 0x5008 #define GPIO_SOUTHEAST_REGISTERS_TS3_CLK_PAD_CFG1_MSGREGADDR 0x500C #define GPIO_SOUTHEAST_REGISTERS_TS3_DAV_PAD_CFG0_MSGREGADDR 0x5018 #define GPIO_SOUTHEAST_REGISTERS_TS3_DAV_PAD_CFG1_MSGREGADDR 0x501C #define GPIO_SOUTHEAST_REGISTERS_TS3_SYNC_PAD_CFG0_MSGREGADDR 0x5020 #define GPIO_SOUTHEAST_REGISTERS_TS3_SYNC_PAD_CFG1_MSGREGADDR 0x5024 #define GPIO_SOUTHEAST_REGISTERS_TS3_DATA_PAD_CFG0_MSGREGADDR 0x5038 #define GPIO_SOUTHEAST_REGISTERS_TS3_DATA_PAD_CFG1_MSGREGADDR 0x503C /*TS4*/ #define GPIO_SOUTHEAST_REGISTERS_TS4_SYNC_CCARD_MISTRT_PAD_CFG0_MSGREGADDR 0x5400 #define GPIO_SOUTHEAST_REGISTERS_TS4_SYNC_CCARD_MISTRT_PAD_CFG1_MSGREGADDR 0x5404 #define GPIO_SOUTHEAST_REGISTERS_TS4_DAV_CCARD_MDI_0_PAD_CFG0_MSGREGADDR 0x5410 #define GPIO_SOUTHEAST_REGISTERS_TS4_DAV_CCARD_MDI_0_PAD_CFG1_MSGREGADDR 0x5414 #define GPIO_SOUTHEAST_REGISTERS_TS4_CLK_CCARD_MICLK_PAD_CFG0_MSGREGADDR 0x5428 #define GPIO_SOUTHEAST_REGISTERS_TS4_CLK_CCARD_MICLK_PAD_CFG1_MSGREGADDR 0x542C #define GPIO_SOUTHEAST_REGISTERS_TS4_DATA_CCARD_MDO_0_PAD_CFG0_MSGREGADDR 0x5440 #define GPIO_SOUTHEAST_REGISTERS_TS4_DATA_CCARD_MDO_0_PAD_CFG1_MSGREGADDR 0x5444 /*TS5*/ #define GPIO_SOUTHEAST_REGISTERS_TS5_SYNC_CCARD_MOSTRT_PAD_CFG0_MSGREGADDR 0x5430 #define GPIO_SOUTHEAST_REGISTERS_TS5_SYNC_CCARD_MOSTRT_PAD_CFG1_MSGREGADDR 0x5434 #define GPIO_SOUTHEAST_REGISTERS_TS5_DAV_CCARD_MDI_1_PAD_CFG0_MSGREGADDR 0x5460 #define GPIO_SOUTHEAST_REGISTERS_TS5_DAV_CCARD_MDI_1_PAD_CFG1_MSGREGADDR 0x5464 #define GPIO_SOUTHEAST_REGISTERS_TS5_CLK_CCARD_MOCLK_PAD_CFG0_MSGREGADDR 0x5470 #define GPIO_SOUTHEAST_REGISTERS_TS5_CLK_CCARD_MOCLK_PAD_CFG1_MSGREGADDR 0x5474 #define GPIO_SOUTHEAST_REGISTERS_TS5_DATA_CCARD_MDO_1_PAD_CFG0_MSGREGADDR 0x5480 #define GPIO_SOUTHEAST_REGISTERS_TS5_DATA_CCARD_MDO_1_PAD_CFG1_MSGREGADDR 0x5484 /*TS6*/ #define GPIO_SOUTHEAST_REGISTERS_TS6_DATA_CCARD_MDO_3_PAD_CFG0_MSGREGADDR 0x5408 #define GPIO_SOUTHEAST_REGISTERS_TS6_DATA_CCARD_MDO_3_PAD_CFG1_MSGREGADDR 0x540C #define GPIO_SOUTHEAST_REGISTERS_TS6_CLK_CCARD_MDI_2_PAD_CFG0_MSGREGADDR 0x5418 #define GPIO_SOUTHEAST_REGISTERS_TS6_CLK_CCARD_MDI_2_PAD_CFG1_MSGREGADDR 0x541C #define GPIO_SOUTHEAST_REGISTERS_TS6_SYNC_CCARD_MDO_2_PAD_CFG0_MSGREGADDR 0x5448 #define GPIO_SOUTHEAST_REGISTERS_TS6_SYNC_CCARD_MDO_2_PAD_CFG1_MSGREGADDR 0x544C #define GPIO_SOUTHEAST_REGISTERS_TS6_DAV_CCARD_MDI_3_PAD_CFG0_MSGREGADDR 0x5478 #define GPIO_SOUTHEAST_REGISTERS_TS6_DAV_CCARD_MDI_3_PAD_CFG1_MSGREGADDR 0x547C /*TS7*/ #define GPIO_SOUTHEAST_REGISTERS_TS7_DAV_CCARD_MDI_5_PAD_CFG0_MSGREGADDR 0x5420 #define GPIO_SOUTHEAST_REGISTERS_TS7_DAV_CCARD_MDI_5_PAD_CFG1_MSGREGADDR 0x5424 #define GPIO_SOUTHEAST_REGISTERS_TS7_CLK_CCARD_MDI_4_PAD_CFG0_MSGREGADDR 0x5438 #define GPIO_SOUTHEAST_REGISTERS_TS7_CLK_CCARD_MDI_4_PAD_CFG1_MSGREGADDR 0x543C #define GPIO_SOUTHEAST_REGISTERS_TS7_DATA_CCARD_MDO_5_PAD_CFG0_MSGREGADDR 0x5450 #define GPIO_SOUTHEAST_REGISTERS_TS7_DATA_CCARD_MDO_5_PAD_CFG1_MSGREGADDR 0x5454 #define GPIO_SOUTHEAST_REGISTERS_TS7_SYNC_CCARD_MDO_4_PAD_CFG0_MSGREGADDR 0x5468 #define GPIO_SOUTHEAST_REGISTERS_TS7_SYNC_CCARD_MDO_4_PAD_CFG1_MSGREGADDR 0x546C /***************************************************************** */ /*! UART */ /***************************************************************** */ /*Docsis*/ #define GPIO_SOUTHEAST_REGISTERS_DOCSIS_UART_RXD_PAD_CFG0_MSGREGADDR 0x4800 #define GPIO_SOUTHEAST_REGISTERS_DOCSIS_UART_RXD_PAD_CFG1_MSGREGADDR 0x4804 #define GPIO_SOUTHEAST_REGISTERS_DOCSIS_UART_TXD_PAD_CFG0_MSGREGADDR 0x4808 #define GPIO_SOUTHEAST_REGISTERS_DOCSIS_UART_TXD_PAD_CFG1_MSGREGADDR 0x480C /*DECT*/ #define GPIO_SOUTHEAST_REGISTERS_DECT_UART_CTS_B_DECT_SPI_CLK_PAD_CFG0_MSGREGADDR 0x4C20 #define GPIO_SOUTHEAST_REGISTERS_DECT_UART_CTS_B_DECT_SPI_CLK_PAD_CFG1_MSGREGADDR 0x4C24 #define GPIO_SOUTHEAST_REGISTERS_DECT_UART_RTS_B_DECT_SPI_CS_PAD_CFG0_MSGREGADDR 0x4C08 #define GPIO_SOUTHEAST_REGISTERS_DECT_UART_RTS_B_DECT_SPI_CS_PAD_CFG1_MSGREGADDR 0x4C0C #define GPIO_SOUTHEAST_REGISTERS_DECT_UART_RX_DECT_SPI_MISO_PAD_CFG0_MSGREGADDR 0x4C38 #define GPIO_SOUTHEAST_REGISTERS_DECT_UART_RX_DECT_SPI_MISO_PAD_CFG1_MSGREGADDR 0x4C3C #define GPIO_SOUTHEAST_REGISTERS_DECT_UART_TX_DECT_SPI_MOSI_PAD_CFG0_MSGREGADDR 0x4C50 #define GPIO_SOUTHEAST_REGISTERS_DECT_UART_TX_DECT_SPI_MOSI_PAD_CFG1_MSGREGADDR 0x4C54 /***************************************************************** */ /*! TDM */ /***************************************************************** */ /*TDM0 + 1*/ #define GPIO_SOUTHEAST_REGISTERS_TDM_CLK_PAD_CFG0_MSGREGADDR 0x4C18 #define GPIO_SOUTHEAST_REGISTERS_TDM_CLK_PAD_CFG1_MSGREGADDR 0x4C1C #define GPIO_SOUTHEAST_REGISTERS_TDM_FS_PAD_CFG0_MSGREGADDR 0x4C30 #define GPIO_SOUTHEAST_REGISTERS_TDM_FS_PAD_CFG1_MSGREGADDR 0x4C34 #define GPIO_SOUTHEAST_REGISTERS_TDM_TX_PAD_CFG0_MSGREGADDR 0x4C48 #define GPIO_SOUTHEAST_REGISTERS_TDM_TX_PAD_CFG1_MSGREGADDR 0x4C4C #define GPIO_SOUTHEAST_REGISTERS_TDM_RX_PAD_CFG0_MSGREGADDR 0x4C60 #define GPIO_SOUTHEAST_REGISTERS_TDM_RX_PAD_CFG1_MSGREGADDR 0x4C64 /***************************************************************** */ /*! NET PGIOs */ /***************************************************************** */ /*GPIO 6*/ #define GPIO_SOUTHEAST_REGISTERS_PCIE_CLKREQ2B_PAD_CFG0_MSGREGADDR 0x4448 #define GPIO_SOUTHEAST_REGISTERS_PCIE_CLKREQ2B_PAD_CFG1_MSGREGADDR 0x444C /*GPIO 8*/ #define GPIO_SOUTHEAST_REGISTERS_EXT_IRQ_0_PAD_CFG0_MSGREGADDR 0x4810 #define GPIO_SOUTHEAST_REGISTERS_EXT_IRQ_0_PAD_CFG1_MSGREGADDR 0x4814 /*GPIO 9*/ #define GPIO_SOUTHEAST_REGISTERS_EXT_IRQ_1_PAD_CFG0_MSGREGADDR 0x4820 #define GPIO_SOUTHEAST_REGISTERS_EXT_IRQ_1_PAD_CFG1_MSGREGADDR 0x4824 /*GPIO 10*/ #define GPIO_SOUTHEAST_REGISTERS_PCIE_CLKREQ3B_PAD_CFG0_MSGREGADDR 0x4428 #define GPIO_SOUTHEAST_REGISTERS_PCIE_CLKREQ3B_PAD_CFG1_MSGREGADDR 0x442C #define GPIO_SOUTHEAST_REGISTERS_PCIE_CLKREQ3B_PAD_CFG0_MSGREGADDR 0x4428 #define GPIO_SOUTHEAST_REGISTERS_PCIE_CLKREQ3B_PAD_CFG1_MSGREGADDR 0x442C #endif