/*
 *
 * gpio_west_registers.h
 * Description:
 * SPI utility header.
 *
 *
 * GPL LICENSE SUMMARY
 *
 *  Copyright(c) 2015 Intel Corporation.
 *
 *  This program is free software; you can redistribute it and/or modify 
 *  it under the terms of version 2 of the GNU General Public License as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope that it will be useful, but 
 *  WITHOUT ANY WARRANTY; without even the implied warranty of 
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU 
 *  General Public License for more details.
 *
 *
 *  You should have received a copy of the GNU General Public License 
 *  along with this program; if not, write to the Free Software 
 *  Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *  The full GNU General Public License is included in this distribution 
 *  in the file called LICENSE.GPL.
 *
 *  Contact Information:
 *  Intel Corporation
 *  2200 Mission College Blvd.
 *  Santa Clara, CA  97052
 */

#ifndef GPIO_W_REG
#define GPIO_W_REG
#define PUAM7_TS_MAX_NUMBER 7

/***************************************************************** */
/*!                    I2C                                         */
/***************************************************************** */
/*I2C6*/
#define GPIO_WEST_REGISTERS_I2C3_SCL_PAD_CFG0_MSGREGADDR 0x4438
#define GPIO_WEST_REGISTERS_I2C3_SCL_PAD_CFG1_MSGREGADDR 0x443C
#define GPIO_WEST_REGISTERS_I2C3_SDA_PAD_CFG0_MSGREGADDR 0x4458
#define GPIO_WEST_REGISTERS_I2C3_SDA_PAD_CFG1_MSGREGADDR 0x445C
/***************************************************************** */
/*!                    CODEC                                       */
/***************************************************************** */
/*CODEC 1*/
#define GPIO_SOUTHEAST_REGISTERS_CODEC_CLK_PAD_CFG0_MSGREGADDR 0x4C28
#define GPIO_SOUTHEAST_REGISTERS_CODEC_CLK_PAD_CFG1_MSGREGADDR 0x4C2C
#define GPIO_SOUTHEAST_REGISTERS_CODEC_CS0_N_PAD_CFG0_MSGREGADDR 0x4C00
#define GPIO_SOUTHEAST_REGISTERS_CODEC_CS0_N_PAD_CFG1_MSGREGADDR 0x4C04
#define GPIO_SOUTHEAST_REGISTERS_CODEC_CS1_N_PAD_CFG0_MSGREGADDR 0x4C10
#define GPIO_SOUTHEAST_REGISTERS_CODEC_CS1_N_PAD_CFG1_MSGREGADDR 0x4C14
#define GPIO_SOUTHEAST_REGISTERS_CODEC_DATA_IN_PAD_CFG0_MSGREGADDR 0x4C70
#define GPIO_SOUTHEAST_REGISTERS_CODEC_DATA_IN_PAD_CFG1_MSGREGADDR 0x4C74
#define GPIO_SOUTHEAST_REGISTERS_CODEC_DATA_OUT_PAD_CFG0_MSGREGADDR 0x4C58
#define GPIO_SOUTHEAST_REGISTERS_CODEC_DATA_OUT_PAD_CFG1_MSGREGADDR 0x4C5C
#define GPIO_SOUTHEAST_REGISTERS_CODEC_INT_PAD_CFG0_MSGREGADDR 0x4C40
#define GPIO_SOUTHEAST_REGISTERS_CODEC_INT_PAD_CFG1_MSGREGADDR 0x4C44
#define GPIO_SOUTHEAST_REGISTERS_CODEC_RESET0_PAD_CFG0_MSGREGADDR 0x4C80
#define GPIO_SOUTHEAST_REGISTERS_CODEC_RESET0_PAD_CFG1_MSGREGADDR 0x4C84
#define GPIO_SOUTHEAST_REGISTERS_CODEC_RESET1_PAD_CFG0_MSGREGADDR 0x4C78
#define GPIO_SOUTHEAST_REGISTERS_CODEC_RESET1_PAD_CFG1_MSGREGADDR 0x4C7C
/***************************************************************** */
/*!                    GBE                                         */
/***************************************************************** */
/*GBE 0*/
#define GPIO_WEST_REGISTERS_GBE_0_TXDATA_3_PAD_CFG0_MSGREGADDR 0x4C00
#define GPIO_WEST_REGISTERS_GBE_0_TXDATA_3_PAD_CFG1_MSGREGADDR 0x4C04
#define GPIO_WEST_REGISTERS_GBE_0_TXDATA_2_PAD_CFG0_MSGREGADDR 0x4C08
#define GPIO_WEST_REGISTERS_GBE_0_TXDATA_2_PAD_CFG1_MSGREGADDR 0x4C0C
#define GPIO_WEST_REGISTERS_GBE_0_TXDATA_1_PAD_CFG0_MSGREGADDR 0x4C10
#define GPIO_WEST_REGISTERS_GBE_0_TXDATA_1_PAD_CFG1_MSGREGADDR 0x4C14
#define GPIO_WEST_REGISTERS_GBE_0_TXCLK_PAD_CFG0_MSGREGADDR 0x4C18
#define GPIO_WEST_REGISTERS_GBE_0_TXCLK_PAD_CFG1_MSGREGADDR 0x4C1C
#define GPIO_WEST_REGISTERS_GBE_0_TXCTL_PAD_CFG0_MSGREGADDR 0x4C20
#define GPIO_WEST_REGISTERS_GBE_0_TXCTL_PAD_CFG1_MSGREGADDR 0x4C24
#define GPIO_WEST_REGISTERS_GBE_0_TXDATA_0_PAD_CFG0_MSGREGADDR 0x4C28
#define GPIO_WEST_REGISTERS_GBE_0_TXDATA_0_PAD_CFG1_MSGREGADDR 0x4C2C
#define GPIO_WEST_REGISTERS_GBE_0_RXCLK_PAD_CFG0_MSGREGADDR 0x4C30
#define GPIO_WEST_REGISTERS_GBE_0_RXCLK_PAD_CFG1_MSGREGADDR 0x4C34
#define GPIO_WEST_REGISTERS_GBE_0_RXCTL_PAD_CFG0_MSGREGADDR 0x4C38
#define GPIO_WEST_REGISTERS_GBE_0_RXCTL_PAD_CFG1_MSGREGADDR 0x4C3C
#define GPIO_WEST_REGISTERS_GBE_0_RXDATA_0_PAD_CFG0_MSGREGADDR 0x4C40
#define GPIO_WEST_REGISTERS_GBE_0_RXDATA_0_PAD_CFG1_MSGREGADDR 0x4C44
#define GPIO_WEST_REGISTERS_GBE_0_RXDATA_3_PAD_CFG0_MSGREGADDR 0x4C48
#define GPIO_WEST_REGISTERS_GBE_0_RXDATA_3_PAD_CFG1_MSGREGADDR 0x4C4C
#define GPIO_WEST_REGISTERS_GBE_0_RXDATA_2_PAD_CFG0_MSGREGADDR 0x4C50
#define GPIO_WEST_REGISTERS_GBE_0_RXDATA_2_PAD_CFG1_MSGREGADDR 0x4C54
#define GPIO_WEST_REGISTERS_GBE_0_RXDATA_1_PAD_CFG0_MSGREGADDR 0x4C58
#define GPIO_WEST_REGISTERS_GBE_0_RXDATA_1_PAD_CFG1_MSGREGADDR 0x4C5C
#define GPIO_WEST_REGISTERS_GBE_0_MDC_PAD_CFG0_MSGREGADDR 0x4C60
#define GPIO_WEST_REGISTERS_GBE_0_MDC_PAD_CFG1_MSGREGADDR 0x4C64
#define GPIO_WEST_REGISTERS_GBE_0_MDIO_PAD_CFG0_MSGREGADDR 0x4C68
#define GPIO_WEST_REGISTERS_GBE_0_MDIO_PAD_CFG1_MSGREGADDR 0x4C6C
#define GPIO_WEST_REGISTERS_GBE_0_REFCLK_PAD_CFG0_MSGREGADDR 0x4C70
#define GPIO_WEST_REGISTERS_GBE_0_REFCLK_PAD_CFG1_MSGREGADDR 0x4C74
#define GPIO_WEST_REGISTERS_GBE_0_INT_PAD_CFG0_MSGREGADDR 0x4C78
#define GPIO_WEST_REGISTERS_GBE_0_INT_PAD_CFG1_MSGREGADDR 0x4C7C
#define GPIO_WEST_REGISTERS_GBE_0_RESET_PAD_CFG0_MSGREGADDR 0x4C80
#define GPIO_WEST_REGISTERS_GBE_0_RESET_PAD_CFG1_MSGREGADDR 0x4C84
/*GBE 1*/
#define GPIO_WEST_REGISTERS_GBE_1_TXDATA_3_PAD_CFG0_MSGREGADDR 0x4800
#define GPIO_WEST_REGISTERS_GBE_1_TXDATA_3_PAD_CFG1_MSGREGADDR 0x4804
#define GPIO_WEST_REGISTERS_GBE_1_TXDATA_2_PAD_CFG0_MSGREGADDR 0x4808
#define GPIO_WEST_REGISTERS_GBE_1_TXDATA_2_PAD_CFG1_MSGREGADDR 0x480C
#define GPIO_WEST_REGISTERS_GBE_1_TXDATA_1_PAD_CFG0_MSGREGADDR 0x4810
#define GPIO_WEST_REGISTERS_GBE_1_TXDATA_1_PAD_CFG1_MSGREGADDR 0x4814
#define GPIO_WEST_REGISTERS_GBE_1_TXCLK_PAD_CFG0_MSGREGADDR 0x4818
#define GPIO_WEST_REGISTERS_GBE_1_TXCLK_PAD_CFG1_MSGREGADDR 0x481C
#define GPIO_WEST_REGISTERS_GBE_1_TXCTL_PAD_CFG0_MSGREGADDR 0x4820
#define GPIO_WEST_REGISTERS_GBE_1_TXCTL_PAD_CFG1_MSGREGADDR 0x4824
#define GPIO_WEST_REGISTERS_GBE_1_TXDATA_0_PAD_CFG0_MSGREGADDR 0x4828
#define GPIO_WEST_REGISTERS_GBE_1_TXDATA_0_PAD_CFG1_MSGREGADDR 0x482C
#define GPIO_WEST_REGISTERS_GBE_1_RXCLK_PAD_CFG0_MSGREGADDR 0x4830
#define GPIO_WEST_REGISTERS_GBE_1_RXCLK_PAD_CFG1_MSGREGADDR 0x4834
#define GPIO_WEST_REGISTERS_GBE_1_RXCTL_PAD_CFG0_MSGREGADDR 0x4838
#define GPIO_WEST_REGISTERS_GBE_1_RXCTL_PAD_CFG1_MSGREGADDR 0x483C
#define GPIO_WEST_REGISTERS_GBE_1_RXDATA_0_PAD_CFG0_MSGREGADDR 0x4840
#define GPIO_WEST_REGISTERS_GBE_1_RXDATA_0_PAD_CFG1_MSGREGADDR 0x4844
#define GPIO_WEST_REGISTERS_GBE_1_RXDATA_3_PAD_CFG0_MSGREGADDR 0x4848
#define GPIO_WEST_REGISTERS_GBE_1_RXDATA_3_PAD_CFG1_MSGREGADDR 0x484C
#define GPIO_WEST_REGISTERS_GBE_1_RXDATA_2_PAD_CFG0_MSGREGADDR 0x4850
#define GPIO_WEST_REGISTERS_GBE_1_RXDATA_2_PAD_CFG1_MSGREGADDR 0x4854
#define GPIO_WEST_REGISTERS_GBE_1_RXDATA_1_PAD_CFG0_MSGREGADDR 0x4858
#define GPIO_WEST_REGISTERS_GBE_1_RXDATA_1_PAD_CFG1_MSGREGADDR 0x485C
#define GPIO_WEST_REGISTERS_GBE_1_MDC_PAD_CFG0_MSGREGADDR 0x4860
#define GPIO_WEST_REGISTERS_GBE_1_MDC_PAD_CFG1_MSGREGADDR 0x4864
#define GPIO_WEST_REGISTERS_GBE_1_MDIO_PAD_CFG0_MSGREGADDR 0x4868
#define GPIO_WEST_REGISTERS_GBE_1_MDIO_PAD_CFG1_MSGREGADDR 0x486C
#define GPIO_WEST_REGISTERS_GBE_1_REFCLK_PAD_CFG0_MSGREGADDR 0x4870
#define GPIO_WEST_REGISTERS_GBE_1_REFCLK_PAD_CFG1_MSGREGADDR 0x4874
#define GPIO_WEST_REGISTERS_GBE_1_INT_PAD_CFG0_MSGREGADDR 0x4878
#define GPIO_WEST_REGISTERS_GBE_1_INT_PAD_CFG1_MSGREGADDR 0x487C
#define GPIO_WEST_REGISTERS_GBE_1_RESET_PAD_CFG0_MSGREGADDR 0x4880
#define GPIO_WEST_REGISTERS_GBE_1_RESET_PAD_CFG1_MSGREGADDR 0x4884
/***************************************************************** */
/*!                    SGMII                                       */
/***************************************************************** */
/*0*/
#define GPIO_WEST_REGISTERS_SATA_DEVSLP0_PAD_CFG0_MSGREGADDR 0x4440
#define GPIO_WEST_REGISTERS_SATA_DEVSLP0_PAD_CFG1_MSGREGADDR 0x4444
/***************************************************************** */
/*!                    NET PGIOs                                   */
/***************************************************************** */
/*GPIO 18*/
#define GPIO_WEST_REGISTERS_GBE_0_RESET_PAD_CFG0_MSGREGADDR 0x4C80
#define GPIO_WEST_REGISTERS_GBE_0_RESET_PAD_CFG1_MSGREGADDR 0x4C84
/*gpio19*/
#define GPIO_WEST_REGISTERS_GBE_1_RESET_PAD_CFG0_MSGREGADDR 0x4880
#define GPIO_WEST_REGISTERS_GBE_1_RESET_PAD_CFG1_MSGREGADDR 0x4884

#endif