--- zzzz-none-000/linux-5.15.111/arch/arm/mm/Kconfig	2023-05-11 14:00:40.000000000 +0000
+++ puma7-arm-6670-761/linux-5.15.111/arch/arm/mm/Kconfig	2024-02-07 09:27:16.000000000 +0000
@@ -1,4 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
+# Includes Intel Corporation's changes/modifications dated: 2014, 2018.
+# Changed/modified portions - Copyright © 2014-2018, Intel Corporation.
 comment "Processor Type"
 
 # Select CPU types depending on the architecture selected.  This selects
@@ -134,6 +136,8 @@
 # ARM926T
 config CPU_ARM926T
 	bool
+	depends on !ARCH_AVALANCHE && (ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_MX2 || ARCH_DAVINCI)
+	default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_MX2 || ARCH_DAVINCI 
 	select CPU_32v5
 	select CPU_ABRT_EV5TJ
 	select CPU_CACHE_VIVT
@@ -376,6 +380,7 @@
 # ARMv6
 config CPU_V6
 	bool
+	depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_AVALANCHE
 	select CPU_32v6
 	select CPU_ABRT_EV6
 	select CPU_CACHE_V6
@@ -390,6 +395,7 @@
 # ARMv6k
 config CPU_V6K
 	bool
+	depends on CPU_V6
 	select CPU_32v6
 	select CPU_32v6K
 	select CPU_ABRT_EV6
@@ -467,13 +473,13 @@
 
 config CPU_32v5
 	bool
+		depends on !ARCH_AVALANCHE
 	select CPU_USE_DOMAINS if MMU
 	select NEED_KUSER_HELPERS
 	select TLS_REG_EMUL if SMP || !MMU
 
 config CPU_32v6
 	bool
-	select TLS_REG_EMUL if !CPU_32v6K && !MMU
 
 config CPU_32v6K
 	bool
@@ -750,7 +756,6 @@
 config CPU_ENDIAN_BE8
 	bool
 	depends on CPU_BIG_ENDIAN
-	default CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
 	help
 	  Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
 
@@ -774,7 +779,7 @@
 
 config CPU_ICACHE_DISABLE
 	bool "Disable I-Cache (I-bit)"
-	depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
+	depends on (CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
 	help
 	  Say Y here to disable the processor instruction cache. Unless
 	  you have a reason not to or are unsure, say N.
@@ -989,6 +994,7 @@
 	default MIGHT_HAVE_CACHE_L2X0
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC
+	select CACHE_L2X0_BIG_ENDIAN if ARCH_AVALANCHE
 	help
 	  This option enables the L2x0 PrimeCell.
 
@@ -999,6 +1005,11 @@
 	  This option enables support for the performance monitoring features
 	  of the L220 and PL310 outer cache controllers.
 
+config CACHE_L2X0_BIG_ENDIAN
+	bool "Set L2X0 driver to BIG endian" if CACHE_L2X0
+	help
+	  Set L2X0 driver to BIG endian
+
 if CACHE_L2X0
 
 config PL310_ERRATA_588369