/* * * avalanche_intd.h * Description: * interrupt distributor header file * * This file is provided under a dual BSD/GPLv2 license. When using or redistributing this file, you may do so under either license. GPL LICENSE SUMMARY Copyright(c) 2015 Intel Corporation. This program is free software; you can redistribute it and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. The full GNU General Public License is included in this distribution in the file called LICENSE.GPL. Contact Information: Intel Corporation 2200 Mission College Blvd. Santa Clara, CA 97052 BSD LICENSE Copyright(c) 2008-2015 Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /****************/ /** Includes **/ /****************/ #include #include #include #include #include #include #include /***************/ /** Defines **/ /***************/ #define INTD_MAX_ENABLE_REGS ( 32 ) #define INTD_MAX_STATUS_REGS ( 32 ) #define INTD_MAX_POLARITY_REGS ( 32 ) #define INTD_MAX_TYPE_REGS ( 32 ) #define INTD_MAX_COUNT_REGS ( 64 ) #define INTD_MAX_PACER_REGS ( 50 ) #define INTD_MAX_VECT_VAL ( 255 ) #define INTD_MAX_INTERRUPT_COUNT ( 255 ) #define INTD_SET_BIT_0 ( 0x00000001 ) #define INTD_CLEAR_BIT_0 ( 0xFFFFFFFE ) /*Avalanche Interrupt Distributor registers */ /*This IO region is in Packet Processor1 region Avalanche Interrupt Distributor registers */ /** * Interrupts Distributor 1 (INTD1) base address, has 16 ip * interrupts to 12 system interrupts. */ #define ATOM_INTD1_BASE (0xF3C23000) /** * INTD0 interrupt0's line in the system interrupt controller * (INTC). */ #define ATOM_INTD_BASE (0xF3C22000) /* uncomment to enable debug prints */ //#define PAL_CPPI4_DBG #ifdef PAL_CPPI4_DBG /* Debug print, also print function name and line number */ # define DPRINTK(fmt, args...) printk("%s(%d): " fmt "\n", __FUNCTION__ , __LINE__, ## args) #else # define DPRINTK(fmt, args...) #endif /* Error print, also print function name and line number */ #define EPRINTK(fmt, args...) printk(KERN_ERR "****** %s(%d): " fmt " ******\n", __FUNCTION__ , __LINE__, ## args) /***************/ /** Globals **/ /***************/ avalanche_idist_regs_t *intd_regs; avalanche_idist_regs_t *intd1_regs; SOC_HOST_INFO host_info = { .host_num = 0, .max_ip_ints_mapped = (AVALANCHE_IDIST_IP_INT_NUM + AVALANCHE_IDIST1_IP_INT_NUM), }; /********************************/ /** functions Implementation **/ /********************************/ static int __init avalanche_intd_init(void) { /* NETSS mmio structure */ netss_dev_info_t cppiMemIO_pp1; intd_regs = NULL; intd1_regs = NULL; if(!netss_device_get_info(NETSS_DEV_PACKET_PROCESSOR1, &cppiMemIO_pp1)) { DPRINTK("DBG: Physical Address of NETSS_PP_DPIPROXY=%p \n", (cppiMemIO_pp1.base )); /*initilize AVALANCHE controller register memory map INTD addresses */ intd_regs = (avalanche_idist_regs_t *)ioremap_nocache( (cppiMemIO_pp1.base + (ATOM_INTD_BASE & 0x00FFFFFF)), sizeof(avalanche_idist_regs_t)); if(!intd_regs) { EPRINTK("ERROR: could not mapped AVALANCHE_INTD_BASE region in \n"); return 1; } DPRINTK("DBG: Physical Address of AVALANCHE_INTD_BASE=%p Virtual address of AVALANCHE_INTD_BASE=%p\n", (cppiMemIO_pp1.base + (ATOM_INTD_BASE & 0x00FFFFFF)), intd_regs); /*initilize AVALANCHE INTD1 controller register memory map addresses */ intd1_regs = (avalanche_idist_regs_t *)ioremap_nocache( (cppiMemIO_pp1.base + (ATOM_INTD1_BASE & 0x00FFFFFF)), sizeof(avalanche_idist_regs_t)); if(!intd1_regs) { EPRINTK("ERROR: could not mapped AVALANCHE_INTD1_BASE region in \n"); return 1; } DPRINTK("DBG: Physical Address of AVALANCHE_INTD1_BASE=%p Virtual address of AVALANCHE_INTD1_BASE=%p\n", (cppiMemIO_pp1.base + (ATOM_INTD1_BASE & 0x00FFFFFF)), intd1_regs); } else { EPRINTK(" netss_get_subdevice_mmio_info() error for PP2 \n"); } /* reading revision registers of INTD and INTD1 */ DPRINTK("AVALANCHE_INTD Interrupt distributor revision : %x", be32_to_cpu(intd_regs->idrevr)); DPRINTK("AVALANCHE_INTD1 Interrupt distributor revision : %x", be32_to_cpu(intd1_regs->idrevr)); return 0; } static void __exit avalanche_intd_cleanup(void) { /* cleanup AVALANCHE INTD addresses */ if(intd_regs != NULL ) { iounmap(intd_regs); intd_regs = NULL; } /*cleanup AVALANCHE INTD1 addresses */ if(intd1_regs != NULL ) { iounmap(intd1_regs); intd1_regs= NULL; } } int avalanche_intd_get_interrupt_count( unsigned int host_num, unsigned int ip_int_num ) { DPRINTK("start"); if( (host_num == host_info.host_num) && (ip_int_num < INTD_MAX_COUNT_REGS )&& (ip_int_num < host_info.max_ip_ints_mapped )) { unsigned int counter_reg_indx = ip_int_num; counter_reg_indx -= (AVALANCHE_IDIST_IP_INT_NUM <= ip_int_num) ? AVALANCHE_IDIST_IP_INT_NUM : 0; if (AVALANCHE_IDIST_IP_INT_NUM <= ip_int_num) { return be32_to_cpu(intd1_regs->idcounterr[counter_reg_indx]); } return be32_to_cpu(intd_regs->idcounterr[counter_reg_indx]); } DPRINTK("end"); return (-1); } EXPORT_SYMBOL(avalanche_intd_get_interrupt_count); int avalanche_intd_set_interrupt_count(unsigned int host_num, unsigned int ip_int_num, unsigned int count_val) { if ((host_num == host_info.host_num) && (ip_int_num < INTD_MAX_COUNT_REGS) && (ip_int_num < host_info.max_ip_ints_mapped) && (count_val < INTD_MAX_INTERRUPT_COUNT)) { unsigned int counter_reg_indx = ip_int_num; counter_reg_indx -= (AVALANCHE_IDIST_IP_INT_NUM <= ip_int_num) ? AVALANCHE_IDIST_IP_INT_NUM : 0; if (AVALANCHE_IDIST_IP_INT_NUM < ip_int_num) { intd1_regs->idcounterr[counter_reg_indx] = cpu_to_be32(count_val); } else { intd_regs->idcounterr[counter_reg_indx] = cpu_to_be32(count_val); } return 0; } return (-1); } EXPORT_SYMBOL(avalanche_intd_set_interrupt_count); int avalanche_intd_write_eoi(unsigned int vect_val) { if (vect_val <= INTD_MAX_VECT_VAL) { if (AVALANCHE_IDIST_SYS_INT_NUM <= vect_val) { intd1_regs->ideoir = cpu_to_be32(vect_val - AVALANCHE_IDIST_SYS_INT_NUM); } else { intd_regs->ideoir = cpu_to_be32(vect_val); } return 0; } return (-1); } EXPORT_SYMBOL(avalanche_intd_write_eoi); module_init(avalanche_intd_init); module_exit(avalanche_intd_cleanup);