/* * Intel PCH/PCU SPI flash driver. * * Copyright (C) 2015-2016, Intel Corporation * Author: Mika Westerberg * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include #include #include #include #include #include #include #include #include #include #include "intel-spi.h" /* Offsets are from @ispi->base */ #define BFPREG 0x00 #define HSFSTS_CTL 0x04 #define HSFSTS_CTL_FSMIE BIT(31) #define HSFSTS_CTL_FDBC_SHIFT 24 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT) #define HSFSTS_CTL_FCYCLE_SHIFT 17 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT) /* HW sequencer opcodes */ #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT) #define HSFSTS_CTL_FGO BIT(16) #define HSFSTS_CTL_FLOCKDN BIT(15) #define HSFSTS_CTL_FDV BIT(14) #define HSFSTS_CTL_SCIP BIT(5) #define HSFSTS_CTL_AEL BIT(2) #define HSFSTS_CTL_FCERR BIT(1) #define HSFSTS_CTL_FDONE BIT(0) #define FADDR 0x08 #define DLOCK 0x0c #define FDATA(n) (0x10 + ((n) * 4)) #define FRACC 0x50 #define FREG(n) (0x54 + ((n) * 4)) #define FREG_BASE_MASK 0x3fff #define FREG_LIMIT_SHIFT 16 #define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT) #define PR(n) (0x74 + ((n) * 4)) #define PR_WRITE_ENABLE BIT(31) #define PR_LIMIT_SHIFT 16 #define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT) #define PR_READ_ENABLE BIT(15) #define PR_BASE_MASK 0x3fff #define PR_ADDR_SHIFT 12 #define PR_NUMBER 5 /* Offsets are from @ispi->sregs */ #define SSFSTS_CTL 0x00 #define SSFSTS_CTL_FSMIE BIT(23) #define SSFSTS_CTL_DS BIT(22) #define SSFSTS_CTL_DBC_SHIFT 16 #define SSFSTS_CTL_SPOP BIT(11) #define SSFSTS_CTL_ACS BIT(10) #define SSFSTS_CTL_SCGO BIT(9) #define SSFSTS_CTL_COP_SHIFT 12 #define SSFSTS_CTL_AEL BIT(4) #define SSFSTS_CTL_FCERR BIT(3) #define SSFSTS_CTL_FDONE BIT(2) #define SSFSTS_CTL_SCIP BIT(0) #define PREOP_OPTYPE 0x04 #define OPMENU0 0x08 #define OPMENU1 0x0c /* CPU specifics */ #define SSFSTS_CTL_BYT 0x90 #define BCR_BYT 0xfc #define BCR_BYT_WPD BIT(0) #define SSFSTS_CTL_LPT 0x90 #define GBL_SMI_EN 0x1 /** * @dev: Device pointer * @base: Beginning of MMIO space * @sregs: Start of software sequencer registers * @opcodes: Opcodes that are supported. This gets programmed by BIOS * before it locks down the controller. */ struct intel_spi { struct device *dev; const struct intel_spi_boardinfo *info; struct spi_nor nor; struct mtd_info mtd; void __iomem *base; void __iomem *sregs; bool hwonly; bool readonly; u8 opcodes[8]; u8 preopcodes[2]; }; /** * @base: Beginning of the protected region, bits 26:12 are extracted from the PR(n) register, bits 11:0 are assumed to be 0x000. * @limit: Limit of the protected region, bits 26:12 are extracted from the PR(n) register, bits 11:0 are assumed to be 0xFFF. * @reg: Address of the PR(n) register. */ struct protected_region { u32 base; u32 limit; void __iomem *reg; }; static struct protected_region pr[PR_NUMBER]; /* * SMI_EN port number, used to disable SMI to make sure the SPI driver does not * get interrupted by SMI handlers that could access the SPI as well. */ static u32 smi_en_port; static const char *intel_spi_partition_names[] = { "Descriptor", "BIOS", "ME", "GbE", "Platform Data", }; static void dump_regs(struct intel_spi *ispi) { #ifdef DEBUG u32 value; int i; dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG)); value = readl(ispi->base + HSFSTS_CTL); dev_info(ispi->dev, "HSFSTS_CTL=0x%08x\n", value); if (value & HSFSTS_CTL_FLOCKDN) dev_dbg(ispi->dev, "-> Locked\n"); dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR)); dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK)); for (i = 0; i < 16; i++) dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n", i, readl(ispi->base + FDATA(i))); dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC)); for (i = 0; i < 5; i++) dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i, readl(ispi->base + FREG(i))); for (i = 0; i < 5; i++) dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i, readl(ispi->base + PR(i))); dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", readl(ispi->sregs + SSFSTS_CTL)); dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n", readl(ispi->sregs + PREOP_OPTYPE)); dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", readl(ispi->sregs + OPMENU0)); dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", readl(ispi->sregs + OPMENU1)); if (ispi->info->type == INTEL_SPI_BYT) dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BCR_BYT)); dev_dbg(ispi->dev, "Protected regions:\n"); for (i = 0; i < 5; i++) { u32 base, limit; value = readl(ispi->base + PR(i)); if (!(value & (PR_WRITE_ENABLE | PR_READ_ENABLE))) continue; limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT; base = value & PR_BASE_MASK; dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n", i, base << 12, (limit << 12) | 0xfff, value & PR_WRITE_ENABLE ? 'W' : '.', value & PR_READ_ENABLE ? 'R' : '.'); } dev_dbg(ispi->dev, "Flash regions:\n"); for (i = 0; i < 5; i++) { u32 region, base, limit; region = readl(ispi->base + FREG(i)); base = region & FREG_BASE_MASK; limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT; if (base > limit || (i > 0 && limit == 0)) dev_dbg(ispi->dev, " %02d disabled\n", i); else dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n", i, base << 12, (limit << 12) | 0xfff); } if (ispi->readonly) dev_dbg(ispi->dev, "The flash chip is readonly\n"); #endif } /* Reads max 64 bytes from the device fifo */ static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size) { size_t bytes; int i = 0; if (size > 64) return -EINVAL; while (size > 0) { bytes = min_t(size_t, size, 4); if(buf == NULL || ispi->base == NULL) { return -EINVAL; } memcpy_fromio(buf, ispi->base + FDATA(i++), bytes); size -= bytes; buf += bytes; } return 0; } /* Writes max 64 bytes to the device fifo */ static int intel_spi_write_block(struct intel_spi *ispi, const void *buf, size_t size) { size_t bytes; int i = 0; if (size > 64) return -EINVAL; while (size > 0) { bytes = min_t(size_t, size, 4); memcpy_toio(ispi->base + FDATA(i++), buf, bytes); size -= bytes; buf += bytes; } return 0; } static int intel_spi_wait_busy(struct intel_spi *ispi) { unsigned long timeout = jiffies + msecs_to_jiffies(100); u32 hwstat, swstat; while (!time_after(jiffies, timeout)) { /* Both sequencers must be idle */ hwstat = readl(ispi->base + HSFSTS_CTL); swstat = readl(ispi->base + SSFSTS_CTL); if (!(hwstat & HSFSTS_CTL_SCIP) && !(swstat & SSFSTS_CTL_SCIP)) break; cond_resched(); } return timeout <= 0 ? -ETIMEDOUT : 0; } /* Get the SMI_EN port number in order be able to disable/enable SMIs. */ static void get_smi_en_port(struct intel_spi *ispi) { struct pci_dev *pcu_dev = NULL; u32 pcu_base_addr_cfg; u32 acpi_base_addr; u32 SmiEnVal; /* Invalidate the SMI_EN port number in case something fails */ smi_en_port = 0; /* Find the PCU */ pcu_dev = pci_get_device(0x8086, 0x2B9C, NULL); if (!pcu_dev) { dev_err(ispi->dev, "PCU device not found\n"); return; } /* * The bits 15:7 of the ACPI base address are at offset 0x40 * from PCI config space. */ pci_read_config_dword(pcu_dev, 0x40, &pcu_base_addr_cfg); acpi_base_addr = pcu_base_addr_cfg & 0x0000FF80; if (!acpi_base_addr) { dev_err(ispi->dev, "I/O space for ACPI uninitialized\n"); return; } /* SMI_EN is at offset 0x30 from ABASE */ smi_en_port = acpi_base_addr + 0x30; /* If SMIs are disabled leave them like that. */ SmiEnVal = inl(smi_en_port); if (0 == (SmiEnVal & 0xFFFFFFFE)) { dev_info(ispi->dev, "SMIs already disabled\n"); smi_en_port = 0; } } /* * Disables the generation of SMIs. * Returns the status of the gbl_smi_en bit before it was disabled. */ static inline u32 disable_smi(void) { u32 SmiEnVal; u32 gbl_smi_en_val = 0; if (smi_en_port) { SmiEnVal = inl(smi_en_port); gbl_smi_en_val = SmiEnVal & GBL_SMI_EN; /* Clear bit 0 (gbl_smi_en) */ SmiEnVal &= 0xFFFFFFFE; outl(SmiEnVal, smi_en_port); } return gbl_smi_en_val; } /* * Restores the status of the gbl_smi_en bit to its original value * before being disabled by disable_smi() function. */ static inline void restore_smi(u32 gbl_smi_en_val) { u32 SmiEnVal; if (smi_en_port) { SmiEnVal = inl(smi_en_port); SmiEnVal |= gbl_smi_en_val & GBL_SMI_EN; outl(SmiEnVal, smi_en_port); } } /* * Disables write protection of the region that contains 'offset'. * No action is performed if 'offset' is not contained in any protected region. */ static inline void intel_spi_unprotect(u32 offset) { u32 val; int i; for (i = 0; i < PR_NUMBER; i++) { if (offset >= pr[i].base && offset <= pr[i].limit) { val = readl(pr[i].reg); val &= (u32)~PR_WRITE_ENABLE; writel(val, pr[i].reg); break; } } } /* * Enables write protection of the region that contains 'offset'. * No action is performed if 'offset' is not contained in any protected region. */ static inline void intel_spi_protect(u32 offset) { u32 val; int i; for (i = 0; i < PR_NUMBER; i++) { if (offset >= pr[i].base && offset <= pr[i].limit) { val = readl(pr[i].reg); val |= (u32)PR_WRITE_ENABLE; writel(val, pr[i].reg); break; } } } static int intel_spi_init(struct intel_spi *ispi) { u32 opmenu0, opmenu1, val; int i; switch (ispi->info->type) { case INTEL_SPI_BYT: ispi->sregs = ispi->base + SSFSTS_CTL_BYT; /* Disable write protection */ val = readl(ispi->base + BCR_BYT); if (!(val & BCR_BYT_WPD)) { val |= BCR_BYT_WPD; writel(val, ispi->base + BCR_BYT); val = readl(ispi->base + BCR_BYT); } ispi->readonly = !(val & BCR_BYT_WPD); break; case INTEL_SPI_LPT: ispi->sregs = ispi->base + SSFSTS_CTL_LPT; break; default: return -EINVAL; } /* Disable #SMI generation */ val = readl(ispi->base + HSFSTS_CTL); val &= ~HSFSTS_CTL_FSMIE; writel(val, ispi->base + HSFSTS_CTL); val = readl(ispi->sregs + SSFSTS_CTL); val &= ~SSFSTS_CTL_FSMIE; writel(val, ispi->sregs + SSFSTS_CTL); /* * BIOS programs allowed opcodes and then locks down the register. * So read back what opcodes it decided to support. That's the set * we are supporting as well. */ opmenu0 = readl(ispi->sregs + OPMENU0); opmenu1 = readl(ispi->sregs + OPMENU1); for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) { ispi->opcodes[i] = opmenu0 >> i * 8; ispi->opcodes[i + 4] = opmenu1 >> i * 8; } val = readl(ispi->sregs + PREOP_OPTYPE); ispi->preopcodes[0] = val; ispi->preopcodes[1] = val >> 8; /* Detect if there is any write protected region. */ for (i = 0; i < PR_NUMBER; i++) { val = readl(ispi->base + PR(i)); if (val & PR_WRITE_ENABLE) { pr[i].limit = ((val & PR_LIMIT_MASK) >> (PR_LIMIT_SHIFT-PR_ADDR_SHIFT))|0xFFF; pr[i].base = (val & PR_BASE_MASK)<base + PR(i); } else { /* Invalidate this entry */ pr[i].limit = 0; pr[i].base = (u32)~0; } } get_smi_en_port(ispi); dump_regs(ispi); return 0; } static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode) { int i; for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) if (ispi->opcodes[i] == opcode) return i; return -EINVAL; } static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, u8 *buf, int len) { u32 val, status; int ret; val = readl(ispi->base + HSFSTS_CTL); val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK); switch (opcode) { case SPINOR_OP_RDID: val |= HSFSTS_CTL_FCYCLE_RDID; break; case SPINOR_OP_WRSR: val |= HSFSTS_CTL_FCYCLE_WRSR; break; case SPINOR_OP_RDSR: val |= HSFSTS_CTL_FCYCLE_RDSR; break; default: return -EINVAL; } val |= len << HSFSTS_CTL_FDBC_SHIFT; val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val |= HSFSTS_CTL_FGO; writel(val, ispi->base + HSFSTS_CTL); ret = intel_spi_wait_busy(ispi); if (ret) return ret; status = readl(ispi->base + HSFSTS_CTL); if (status & HSFSTS_CTL_FCERR) return -EIO; else if (status & HSFSTS_CTL_AEL) return -EACCES; return 0; } static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, u8 * buf, int len, bool write_enable) { u32 val, status; int ret; ret = intel_spi_opcode_index(ispi, opcode); if (ret < 0) return ret; val = SSFSTS_CTL_DS | len << SSFSTS_CTL_DBC_SHIFT; val |= ret << SSFSTS_CTL_COP_SHIFT; val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE; if (write_enable) { if (ispi->preopcodes[1] == SPINOR_OP_WREN) val |= SSFSTS_CTL_SPOP; val |= SSFSTS_CTL_ACS; } val |= SSFSTS_CTL_SCGO; writel(val, ispi->sregs + SSFSTS_CTL); ret = intel_spi_wait_busy(ispi); if (ret) return ret; status = readl(ispi->base + SSFSTS_CTL); if (status & SSFSTS_CTL_FCERR) return -EIO; else if (status & SSFSTS_CTL_AEL) return -EACCES; return 0; } static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) { struct intel_spi *ispi = nor->priv; int ret; /* Address of the first chip */ writel(0, ispi->base + FADDR); ret = intel_spi_sw_cycle(ispi, opcode, buf, len, false); if (ret) ret = intel_spi_hw_cycle(ispi, opcode, buf, len); if (ret) return ret; return intel_spi_read_block(ispi, buf, len); } static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) { struct intel_spi *ispi = nor->priv; int ret; /* * This is handled with atomic operation and preop code in Intel * controler so skip it here now. */ if (opcode == SPINOR_OP_WREN) return 0; writel(0, ispi->base + FADDR); /* Write the value beforehand */ ret = intel_spi_write_block(ispi, buf, len); if (ret) return ret; ret = intel_spi_sw_cycle(ispi, opcode, buf, len, 0); if (ret) ret = intel_spi_hw_cycle(ispi, opcode, buf, len); return ret; } static int intel_spi_read(struct spi_nor *nor, loff_t from, size_t len, u_char *read_buf) { struct intel_spi *ispi = nor->priv; size_t block_size, len_read = 0; u32 val, status, gbl_smi_en_val; ssize_t ret = 0; gbl_smi_en_val = disable_smi(); while (len > 0) { /* AVM/TKL: do not read across sector boundaries */ block_size = min_t(size_t, 64, nor->mtd.erasesize - (from & (nor->mtd.erasesize - 1))); block_size = min_t(size_t, len, block_size); writel(from, ispi->base + FADDR); val = readl(ispi->base + HSFSTS_CTL); val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val &= ~HSFSTS_CTL_FDBC_MASK; val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; val &= ~HSFSTS_CTL_FCYCLE_MASK; val |= HSFSTS_CTL_FCYCLE_READ; val |= HSFSTS_CTL_FGO; writel(val, ispi->base + HSFSTS_CTL); ret = intel_spi_wait_busy(ispi); if (ret) break; status = readl(ispi->base + HSFSTS_CTL); if (status & HSFSTS_CTL_FCERR) ret = -EIO; else if (status & HSFSTS_CTL_AEL) ret = -EACCES; if (ret < 0) { dev_err(ispi->dev, "error: from: 0x%llx size: 0x%x status: %#x\n", from, block_size, status); break; } ret = intel_spi_read_block(ispi, read_buf, block_size); if (ret) break; len_read += block_size; //length of buffer read len -= block_size; from += block_size; read_buf += block_size; } restore_smi(gbl_smi_en_val); if(ret < 0) return ret; else return len_read; } static int intel_spi_write(struct spi_nor *nor, loff_t to, size_t len, const u_char *write_buf) { struct intel_spi *ispi = nor->priv; size_t block_size, len_wrote = 0; u32 val, status, gbl_smi_en_val; int ret; gbl_smi_en_val = disable_smi(); intel_spi_unprotect(to); while (len > 0) { /* AVM/TKL: do not write across sector boundaries */ block_size = min_t(size_t, 64, nor->mtd.erasesize - (to & (nor->mtd.erasesize - 1))); block_size = min_t(size_t, len, block_size); writel(to, ispi->base + FADDR); val = readl(ispi->base + HSFSTS_CTL); val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val &= ~HSFSTS_CTL_FDBC_MASK; val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; val &= ~HSFSTS_CTL_FCYCLE_MASK; val |= HSFSTS_CTL_FCYCLE_WRITE; /* Write enable */ if (ispi->preopcodes[1] == SPINOR_OP_WREN) val |= SSFSTS_CTL_SPOP; val |= SSFSTS_CTL_ACS; writel(val, ispi->base + HSFSTS_CTL); ret = intel_spi_write_block(ispi, write_buf, block_size); if (ret) { dev_err(ispi->dev, "failed to write block\n"); break; } /* Start the write now */ val = readl(ispi->base + HSFSTS_CTL); writel(val | HSFSTS_CTL_FGO, ispi->base + HSFSTS_CTL); ret = intel_spi_wait_busy(ispi); if (ret) { dev_err(ispi->dev, "timeout\n"); break; } status = readl(ispi->base + HSFSTS_CTL); if (status & (HSFSTS_CTL_FCERR | HSFSTS_CTL_AEL)) { /* There is not much we can do but to report an error */ dev_err(ispi->dev, "error: %llx: %#x\n", to, status); } len_wrote += block_size; //length of buffer written len -= block_size; to += block_size; write_buf += block_size; } intel_spi_protect(to); restore_smi(gbl_smi_en_val); if(ret<0) return ret; else return len_wrote; } static int intel_spi_erase(struct spi_nor *nor, loff_t offs) { struct intel_spi *ispi = nor->priv; u32 val, status = 0, gbl_smi_en_val; int ret; gbl_smi_en_val = disable_smi(); intel_spi_unprotect(offs); writel(offs, ispi->base + FADDR); val = readl(ispi->base + HSFSTS_CTL); val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; val &= ~HSFSTS_CTL_FDBC_MASK; val &= ~HSFSTS_CTL_FCYCLE_MASK; val |= HSFSTS_CTL_FCYCLE_ERASE; val |= HSFSTS_CTL_FGO; writel(val, ispi->base + HSFSTS_CTL); ret = intel_spi_wait_busy(ispi); if (0 == ret) status = readl(ispi->base + HSFSTS_CTL); if (status & HSFSTS_CTL_FCERR) ret = -EIO; else if (status & HSFSTS_CTL_AEL) ret = -EACCES; intel_spi_protect(offs); restore_smi(gbl_smi_en_val); return ret; } static int intel_spi_fill_partitions(const struct intel_spi *ispi, struct mtd_partition *parts, size_t nparts) { u32 region, base, limit; int i, n; for (i = 0, n = 0; i < nparts; i++) { region = readl(ispi->base + FREG(i)); base = region & FREG_BASE_MASK; limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT; if (base > limit || (i > 0 && limit == 0)) continue; parts[n].name = intel_spi_partition_names[i]; parts[n].offset = base << 12; parts[n].size = ((limit << 12) | 0xfff) - parts[n].offset + 1; if (ispi->readonly) parts[n].mask_flags = MTD_WRITEABLE; n++; } return n; } struct intel_spi *intel_spi_probe(struct device *dev, struct resource *mem, const struct intel_spi_boardinfo *info) { struct mtd_partition parts[ARRAY_SIZE(intel_spi_partition_names)]; struct intel_spi *ispi; int ret, nparts; if (!info || !mem) return ERR_PTR(-EINVAL); ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL); if (!ispi) return ERR_PTR(-ENOMEM); ispi->base = devm_ioremap_resource(dev, mem); if (IS_ERR(ispi->base)) return ispi->base; ispi->info = info; ispi->readonly = info->readonly; ispi->dev = dev; ret = intel_spi_init(ispi); if (ret) return ERR_PTR(ret); ispi->nor.dev = ispi->dev; ispi->nor.priv = ispi; ispi->nor.mtd.priv = &ispi->nor; ispi->nor.read_reg = intel_spi_read_reg; ispi->nor.write_reg = intel_spi_write_reg; ispi->nor.read = intel_spi_read; ispi->nor.write = intel_spi_write; ispi->nor.erase = intel_spi_erase; ret = spi_nor_scan(&ispi->nor, NULL, SPI_NOR_NORMAL); if (ret) { dev_info(dev, "failed to locate the chip\n"); return ERR_PTR(ret); } memset(parts, 0, sizeof(parts)); nparts = intel_spi_fill_partitions(ispi, parts, ARRAY_SIZE(parts)); ret = mtd_device_parse_register(&ispi->nor.mtd, NULL, NULL, parts, nparts); if (ret) return ERR_PTR(ret); return ispi; } EXPORT_SYMBOL_GPL(intel_spi_probe); int intel_spi_remove(struct intel_spi *ispi) { return mtd_device_unregister(&ispi->nor.mtd); } EXPORT_SYMBOL_GPL(intel_spi_remove); MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver"); MODULE_AUTHOR("Mika Westerberg "); MODULE_LICENSE("GPL v2");