/* ========================================================================= * The Synopsys DWC ETHER QOS Software Driver and documentation (hereinafter * "Software") is an unsupported proprietary work of Synopsys, Inc. unless * otherwise expressly agreed to in writing between Synopsys and you. * * The Software IS NOT an item of Licensed Software or Licensed Product under * any End User Software License Agreement or Agreement for Licensed Product * with Synopsys or any supplement thereto. Permission is hereby granted, * free of charge, to any person obtaining a copy of this software annotated * with this license and the Software, to deal in the Software without * restriction, including without limitation the rights to use, copy, modify, * merge, publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, subject * to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * DAMAGE. * ========================================================================= */ #ifndef __DWC_ETH_QOS__YHEADER__ #define __DWC_ETH_QOS__YHEADER__ /* OS Specific declarations and definitions */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) #define DWC_ETH_QOS_ENABLE_VLAN_TAG #endif /* for PPT */ #include #include #include #include /* Macro definitions*/ #define MAC_VER_4_00 0x40 #define MAC_VER_4_10 0x41 #ifdef CONFIG_PTPSUPPORT_OBJ #define DWC_ETH_QOS_CONFIG_PTP #endif #ifdef CONFIG_DEBUGFS_OBJ #define DWC_ETH_QOS_CONFIG_DEBUGFS #endif /* NOTE: Uncomment below line for TX and RX DESCRIPTOR DUMP in KERNEL LOG */ //#define DWC_ETH_QOS_ENABLE_RX_DESC_DUMP /* Uncomment below macro definitions for testing corresponding IP features in driver */ //#define DWC_ETH_QOS_QUEUE_SELECT_ALGO //#define DWC_ETH_QOS_CERTIFICATION_PKTBURSTCNT //#define DWC_ETH_QOS_CERTIFICATION_PKTBURSTCNT_HALFDUPLEX #define DWC_ETH_QOS_TXPOLLING_MODE_ENABLE /* Enable polling GBE ISR status registers */ //#define GBE_POLLING /* Enable GBE debug logic */ //#define GBE_DEBUG #ifdef DWC_ETH_QOS_CONFIG_PTP #undef DWC_ETH_QOS_TXPOLLING_MODE_ENABLE #endif /* Uncomment below macro to enable Double VLAN support. */ //#define DWC_ETH_QOS_ENABLE_DVLAN /* Uncomment below macro to test EEE feature Tx path with * no EEE supported PHY card * */ //#define DWC_ETH_QOS_CUSTOMIZED_EEE_TEST #ifdef DWC_ETH_QOS_CUSTOMIZED_EEE_TEST #undef DWC_ETH_QOS_TXPOLLING_MODE_ENABLE #endif #ifdef DWC_ETH_QOS_CERTIFICATION_PKTBURSTCNT_HALFDUPLEX #define DWC_ETH_QOS_CERTIFICATION_PKTBURSTCNT #endif #ifdef DWC_ETH_QOS_CERTIFICATION_PKTBURSTCNT #undef DWC_ETH_QOS_TXPOLLING_MODE_ENABLE #endif /* NOTE: Uncomment below line for function trace log messages in KERNEL LOG */ //#define YDEBUG //#define YDEBUG_PG //#define YDEBUG_MDIO //#define YDEBUG_PTP //#define YDEBUG_FILTER //#define YDEBUG_EEE #define Y_TRUE 1 #define Y_FALSE 0 #define Y_SUCCESS 0 #define Y_FAILURE 1 #define Y_INV_WR 1 #define Y_INV_RD 2 #define Y_INV_ARG 3 #define Y_MAX_THRD_XEEDED 4 #define ONE_SEC_TO_NS (1000000000) /* The following macros map error macros to POSIX errno values */ #define ERR_READ_TIMEOUT ETIME #define ERR_WRITE_TIMEOUT ETIME #define ERR_FIFO_READ_FAILURE EIO #define ERR_FIFO_WRITE_FAILURE EIO #define ERR_READ_OVRFLW ENOBUFS #define ERR_READ_UNDRFLW ENODATA #define ERR_WRITE_OVRFLW ENOBUFS #define ERR_WRITE_UNDRFLW ENODATA #define MASK (0x1ULL << 0 | \ 0x13c7ULL << 32) #define MAC_MASK (0x10ULL << 0) #define TX_DESC_CNT 1024 #define RX_DESC_CNT 1024 #define MIN_RX_DESC_CNT 16 #define TX_BUF_SIZE 1536 #define RX_BUF_SIZE 1568 #define DWC_ETH_QOS_MAX_LRO_DESC 16 #define DWC_ETH_QOS_MAX_LRO_AGGR 32 #define MIN_PACKET_SIZE 64 /* #ifdef DWC_ETH_QOS_ENABLE_VLAN_TAG #define MAX_PACKET_SIZE VLAN_ETH_FRAME_LEN #else #define MAX_PACKET_SIZE 1514 #endif */ /* RX header size for split header */ #define DWC_ETH_QOS_HDR_SIZE_64B 64 /* 64 bytes */ #define DWC_ETH_QOS_HDR_SIZE_128B 128 /* 128 bytes */ #define DWC_ETH_QOS_HDR_SIZE_256B 256 /* 256 bytes */ #define DWC_ETH_QOS_HDR_SIZE_512B 512 /* 512 bytes */ #define DWC_ETH_QOS_HDR_SIZE_1024B 1024 /* 1024 bytes */ #define DWC_ETH_QOS_MAX_HDR_SIZE DWC_ETH_QOS_HDR_SIZE_256B #define MAX_MULTICAST_LIST 14 #define RX_DESC_DATA_LENGTH_LBIT 0 #define RX_DESC_DATA_LENGTH 0x7fff #define DWC_ETH_QOS_TX_FLAGS_IP_PKT 0x00000001 #define DWC_ETH_QOS_TX_FLAGS_TCP_PKT 0x00000002 #define DEV_NAME "DWC_ETH_QOS" #define DEV_ADDRESS 0xffffffff #define DEV_REG_MMAP_SIZE 0x14e8 #define VENDOR_ID 0x8086 #define DEVICE_ID 0x2BE8 #define PCI_BAR_NO 0 #define COMPLETE_BAR 0 /* MII/GMII register offset */ #define DWC_ETH_QOS_AUTO_NEGO_NP 0x0007 #define DWC_ETH_QOS_PHY_CTL 0x0010 #define DWC_ETH_QOS_PHY_STS 0x0011 /* Default MTL queue operation mode values */ #define DWC_ETH_QOS_Q_DISABLED 0x0 #define DWC_ETH_QOS_Q_AVB 0x1 #define DWC_ETH_QOS_Q_DCB 0x2 #define DWC_ETH_QOS_Q_GENERIC 0x3 /* Driver power status macros */ #define DWC_ETH_QOS_POWER_ON (0) #define DWC_ETH_QOS_MAGIC_WAKEUP (1 << 0) #define DWC_ETH_QOS_REMOTE_WAKEUP (1 << 1) #define DWC_ETH_QOS_NETIP_WAKEUP (1 << 2) #define DWC_ETH_QOS_NETIP_PWRDWN (1 << 3) // Intermediate state to indicate // the device is going to StandBy mode #define DWC_ETH_QOS_NETIP_PWRUP (1 << 4) // Intermediate state to indicate // the device is exiting the StandBy mode #define DWC_ETH_QOS_NETIP_SPLHDR_REQ (1 << 5) // Indicate a split header change was // received while device was in StandBy mode #define DWC_ETH_QOS_NETIP_MTU_REQ (1 << 6) // Indicate a mtu change request was // received while device was in StandBy mode #define DWC_ETH_QOS_NETIP_MAC_ADDR_REQ (1 << 7) // Indicate a MAC address change request was // received while device was in StandBy mode #define DWC_ETH_QOS_MAC_ADDR_LEN 6 #define DWC_ETH_QOS_ETH_FRAME_LEN (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) #define FIFO_SIZE_B(x) (x) #define FIFO_SIZE_KB(x) (x*1024) #define DWC_ETH_QOS_MAX_DATA_PER_TX_BUF (1 << 13) /* 8 KB Maximum data per buffer pointer(in Bytes) */ #define DWC_ETH_QOS_MAX_DATA_PER_TXD (DWC_ETH_QOS_MAX_DATA_PER_TX_BUF * 2) /* Maxmimum data per descriptor(in Bytes) */ #define DWC_ETH_QOS_MAX_SUPPORTED_MTU 16380 #define DWC_ETH_QOS_MAX_GPSL 9000 /* Default maximum Gaint Packet Size Limit */ #define DWC_ETH_QOS_MIN_SUPPORTED_MTU (ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) #define DWC_ETH_QOS_RDESC3_OWN 0x80000000 #define DWC_ETH_QOS_RDESC3_FD 0x20000000 #define DWC_ETH_QOS_RDESC3_LD 0x10000000 #define DWC_ETH_QOS_RDESC3_RS2V 0x08000000 #define DWC_ETH_QOS_RDESC3_RS1V 0x04000000 #define DWC_ETH_QOS_RDESC3_RS0V 0x02000000 #define DWC_ETH_QOS_RDESC3_LT 0x00070000 #define DWC_ETH_QOS_RDESC3_ES 0x00008000 #define DWC_ETH_QOS_RDESC3_PL 0x00007FFF #define DWC_ETH_QOS_RDESC2_HL 0x000003FF #define DWC_ETH_QOS_RDESC1_PT 0x00000007 /* Payload type */ #define DWC_ETH_QOS_RDESC1_PT_TCP 0x00000002 /* Payload type = TCP */ /* Maximum size of pkt that is copied to a new buffer on receive */ #define DWC_ETH_QOS_COPYBREAK_DEFAULT 256 #define DWC_ETH_QOS_SYSCLOCK 62500000 /* System clock is 62.5MHz */ #define DWC_ETH_QOS_SYSTIMEPERIOD 16 /* System time period is 16ns */ #define DWC_ETH_QOS_TX_QUEUE_CNT (pdata->tx_queue_cnt) #define DWC_ETH_QOS_RX_QUEUE_CNT (pdata->rx_queue_cnt) #define DWC_ETH_QOS_QUEUE_CNT min(DWC_ETH_QOS_TX_QUEUE_CNT, DWC_ETH_QOS_RX_QUEUE_CNT) /* Helper macros for TX descriptor handling */ #define GET_TX_QUEUE_PTR(qInx) (&(pdata->tx_queue[(qInx)])) #define GET_TX_DESC_PTR(qInx, dInx) (pdata->tx_queue[(qInx)].tx_desc_data.tx_desc_ptrs[(dInx)]) #define GET_TX_DESC_DMA_ADDR(qInx, dInx) (pdata->tx_queue[(qInx)].tx_desc_data.tx_desc_dma_addrs[(dInx)]) #define GET_TX_WRAPPER_DESC(qInx) (&(pdata->tx_queue[(qInx)].tx_desc_data)) #define GET_TX_BUF_PTR(qInx, dInx) (pdata->tx_queue[(qInx)].tx_desc_data.tx_buf_ptrs[(dInx)]) #define INCR_TX_DESC_INDEX(inx, offset) do {\ (inx) += (offset);\ if ((inx) >= TX_DESC_CNT)\ (inx) = ((inx) - TX_DESC_CNT);\ } while (0) #define DECR_TX_DESC_INDEX(inx) do {\ (inx)--;\ if ((inx) < 0)\ (inx) = (TX_DESC_CNT + (inx));\ } while (0) #define INCR_TX_LOCAL_INDEX(inx, offset)\ (((inx) + (offset)) >= TX_DESC_CNT ?\ ((inx) + (offset) - TX_DESC_CNT) : ((inx) + (offset))) #define GET_CURRENT_XFER_DESC_CNT(qInx) (pdata->tx_queue[(qInx)].tx_desc_data.packet_count) #define GET_CURRENT_XFER_LAST_DESC_INDEX(qInx, start_index, offset)\ (GET_CURRENT_XFER_DESC_CNT((qInx)) == 0) ? (TX_DESC_CNT - 1) :\ ((GET_CURRENT_XFER_DESC_CNT((qInx)) == 1) ? (INCR_TX_LOCAL_INDEX((start_index), (offset))) :\ INCR_TX_LOCAL_INDEX((start_index), (GET_CURRENT_XFER_DESC_CNT((qInx)) + (offset) - 1))) #define GET_TX_TOT_LEN(buffer, start_index, packet_count, total_len) do {\ int i, pkt_idx = (start_index);\ for(i = 0; i < (packet_count); i++) {\ (total_len) += ((buffer)[pkt_idx].len + (buffer)[pkt_idx].len2);\ pkt_idx = INCR_TX_LOCAL_INDEX(pkt_idx, 1);\ } \ } while (0) /* Helper macros for RX descriptor handling */ #define GET_RX_QUEUE_PTR(qInx) (&(pdata->rx_queue[(qInx)])) #define GET_RX_DESC_PTR(qInx, dInx) (pdata->rx_queue[(qInx)].rx_desc_data.rx_desc_ptrs[(dInx)]) #define GET_RX_DESC_DMA_ADDR(qInx, dInx) (pdata->rx_queue[(qInx)].rx_desc_data.rx_desc_dma_addrs[(dInx)]) #define GET_RX_WRAPPER_DESC(qInx) (&(pdata->rx_queue[(qInx)].rx_desc_data)) #define GET_RX_BUF_PTR(qInx, dInx) (pdata->rx_queue[(qInx)].rx_desc_data.rx_buf_ptrs[(dInx)]) #define INCR_RX_DESC_INDEX(inx, offset) do {\ (inx) += (offset);\ if ((inx) >= RX_DESC_CNT)\ (inx) = ((inx) - RX_DESC_CNT);\ } while (0) #define DECR_RX_DESC_INDEX(inx) do {\ (inx)--;\ if ((inx) < 0)\ (inx) = (RX_DESC_CNT + (inx));\ } while (0) #define INCR_RX_LOCAL_INDEX(inx, offset)\ (((inx) + (offset)) >= RX_DESC_CNT ?\ ((inx) + (offset) - RX_DESC_CNT) : ((inx) + (offset))) #define GET_CURRENT_RCVD_DESC_CNT(qInx) (pdata->rx_queue[(qInx)].rx_desc_data.pkt_received) #define GET_CURRENT_RCVD_LAST_DESC_INDEX(start_index, offset) (RX_DESC_CNT - 1) #define GET_TX_DESC_IDX(qInx, desc) (((desc) - GET_TX_DESC_DMA_ADDR((qInx), 0))/(sizeof(tx_descriptor_t))) #define GET_RX_DESC_IDX(qInx, desc) (((desc) - GET_RX_DESC_DMA_ADDR((qInx), 0))/(sizeof(rx_descriptor_t))) /* Helper macro for handling coalesce parameters via ethtool */ /* Obtained by trial and error */ #define DWC_ETH_QOS_OPTIMAL_DMA_RIWT_USEC 124 /* Max delay before RX interrupt after a pkt is received Max * delay in usecs is 1020 for 62.5MHz device clock */ #define DWC_ETH_QOS_MAX_DMA_RIWT 0xff /* Max no of pkts to be received before an RX interrupt */ #define DWC_ETH_QOS_RX_MAX_FRAMES 16 #define DMA_SBUS_AXI_PBL_MASK 0xFE /* Helper macros for handling receive error */ #define DWC_ETH_QOS_RX_LENGTH_ERR 0x00000001 #define DWC_ETH_QOS_RX_BUF_OVERFLOW_ERR 0x00000002 #define DWC_ETH_QOS_RX_CRC_ERR 0x00000004 #define DWC_ETH_QOS_RX_FRAME_ERR 0x00000008 #define DWC_ETH_QOS_RX_FIFO_OVERFLOW_ERR 0x00000010 #define DWC_ETH_QOS_RX_MISSED_PKT_ERR 0x00000020 #define DWC_ETH_QOS_RX_CHECKSUM_DONE 0x00000001 #define DWC_ETH_QOS_RX_VLAN_PKT 0x00000002 /* MAC Time stamp contorl reg bit fields */ #define MAC_TCR_TSENA 0x00000001 /* Enable timestamp */ #define MAC_TCR_TSCFUPDT 0x00000002 /* Enable Fine Timestamp Update */ #define MAC_TCR_TSENALL 0x00000100 /* Enable timestamping for all packets */ #define MAC_TCR_TSCTRLSSR 0x00000200 /* Enable Timestamp Digitla Contorl (1ns accuracy )*/ #define MAC_TCR_TSVER2ENA 0x00000400 /* Enable PTP packet processing for Version 2 Formate */ #define MAC_TCR_TSIPENA 0x00000800 /* Enable processing of PTP over Ethernet Packets */ #define MAC_TCR_TSIPV6ENA 0x00001000 /* Enable processing of PTP Packets sent over IPv6-UDP Packets */ #define MAC_TCR_TSIPV4ENA 0x00002000 /* Enable processing of PTP Packets sent over IPv4-UDP Packets */ #define MAC_TCR_TSEVENTENA 0x00004000 /* Enable Timestamp Snapshot for Event Messages */ #define MAC_TCR_TSMASTERENA 0x00008000 /* Enable snapshot for Message Relevent to Master */ #define MAC_TCR_SNAPTYPSEL_1 0x00010000 /* select PTP packets for taking snapshots */ #define MAC_TCR_SNAPTYPSEL_2 0x00020000 #define MAC_TCR_SNAPTYPSEL_3 0x00030000 #define MAC_TCR_AV8021ASMEN 0x10000000 /* Enable AV 802.1AS Mode */ /* PTP Offloading control register bits (MAC_PTO_control)*/ #define MAC_PTOCR_PTOEN 0x00000001 /* PTP offload Enable */ #define MAC_PTOCR_ASYNCEN 0x00000002 /* Automatic PTP Sync message enable */ #define MAC_PTOCR_APDREQEN 0x00000004 /* Automatic PTP Pdelay_Req message enable */ /* Hash Table Reg count */ #define DWC_ETH_QOS_HTR_CNT (pdata->max_hash_table_size/32) /* For handling VLAN filtering */ #define DWC_ETH_QOS_VLAN_PERFECT_FILTERING 0 #define DWC_ETH_QOS_VLAN_HASH_FILTERING 1 /* For handling differnet PHY interfaces */ #define DWC_ETH_QOS_GMII_MII 0x0 #define DWC_ETH_QOS_RGMII 0x1 #define DWC_ETH_QOS_SGMII 0x2 #define DWC_ETH_QOS_TBI 0x3 #define DWC_ETH_QOS_RMII 0x4 #define DWC_ETH_QOS_RTBI 0x5 #define DWC_ETH_QOS_SMII 0x6 #define DWC_ETH_QOS_RevMII 0x7 /* for EEE */ #define DWC_ETH_QOS_DEFAULT_LPI_LS_TIMER 0x3E8 /* 1000 in decimal */ #define DWC_ETH_QOS_DEFAULT_LPI_TWT_TIMER 0x0 #define DWC_ETH_QOS_DEFAULT_LPI_TIMER 1000 /* LPI Tx local expiration time in msec */ #define DWC_ETH_QOS_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x)) typedef struct { uint32_t RDES0; uint32_t RDES1; uint32_t RDES2; uint32_t RDES3; } rx_descriptor_t; typedef struct { uint32_t TDES0; uint32_t TDES1; uint32_t TDES2; uint32_t TDES3; } tx_descriptor_t; typedef struct { uint32_t pkt_attributes; uint16_t vlan_tag; } rx_pkt_features_t; typedef struct { uint32_t pkt_attributes; uint32_t hdr_len; uint32_t pay_len; uint32_t pkt_type; uint32_t tcp_hdr_len; uint16_t vlan_tag; uint16_t mss; } tx_pkt_features_t; typedef enum { eDWC_ETH_QOS_256 = 0x0, eDWC_ETH_QOS_512 = 0x1, eDWC_ETH_QOS_1k = 0x3, eDWC_ETH_QOS_2k = 0x7, eDWC_ETH_QOS_4k = 0xf, eDWC_ETH_QOS_8k = 0x1f, eDWC_ETH_QOS_16k = 0x3f, eDWC_ETH_QOS_32k = 0x7f } eDWC_ETH_QOS_mtl_fifo_size; typedef enum { eGBE_GMAC5_TO_PHY, eGBE_GMAC5_TO_GMAC4 } e_GBE_mux_config; /* do forward declaration of private data structure */ struct DWC_ETH_QOS_prv_data; struct DWC_ETH_QOS_tx_wrapper_descriptor; typedef struct { uint32_t mac_ier; uint32_t dma_ier; // TODO: Add descriptors configuration to save time in Tx and Rx operations } hw_config_t; typedef struct { int(*tx_complete) (tx_descriptor_t *); int(*tx_window_error) (tx_descriptor_t *); int(*tx_aborted_error) (tx_descriptor_t *); int(*tx_carrier_lost_error) (tx_descriptor_t *); int(*tx_fifo_underrun) (tx_descriptor_t *); int(*tx_get_collision_count) (tx_descriptor_t *); int(*tx_handle_aborted_error) (tx_descriptor_t *); int(*tx_update_fifo_threshold) (tx_descriptor_t *); /*tx threshold config */ int(*tx_config_threshold) (uint32_t); int(*set_promiscuous_mode) (void); int(*set_all_multicast_mode) (void); int(*set_multicast_list_mode) (void); int(*set_unicast_mode) (void); int(*enable_rx_csum) (void); int(*disable_rx_csum) (void); int(*get_rx_csum_status) (void); int(*read_phy_regs) (int, int, int*); int(*write_phy_regs) (int, int, int); int(*set_full_duplex) (void); int(*set_half_duplex) (void); int(*set_speed) (struct DWC_ETH_QOS_prv_data *, uint32_t speed); /* for PMT */ int(*start_dma_rx) (uint32_t); int(*stop_dma_rx) (uint32_t); int(*start_dma_tx) (uint32_t); int(*stop_dma_tx) (uint32_t); int(*start_mac_tx_rx) (void); int(*stop_mac_tx_rx) (void); int(*init) (struct DWC_ETH_QOS_prv_data *); int(*sw_reset) (void); void (*pre_xmit) (struct DWC_ETH_QOS_prv_data *, uint32_t qInx); void (*dev_read) (struct DWC_ETH_QOS_prv_data *, uint32_t qInx); void (*tx_desc_init) (struct DWC_ETH_QOS_prv_data *, uint32_t qInx); void (*rx_desc_init) (struct DWC_ETH_QOS_prv_data *, uint32_t qInx); void (*rx_desc_reset) (uint32_t, struct DWC_ETH_QOS_prv_data *, uint32_t, uint32_t qInx); int(*tx_desc_reset) (uint32_t, struct DWC_ETH_QOS_prv_data *, uint32_t qInx); /* last tx segmnet reports the tx status */ int(*get_tx_desc_ls) (tx_descriptor_t *); int(*get_tx_desc_ctxt) (tx_descriptor_t *); void (*update_rx_tail_ptr) (unsigned int qInx, unsigned int dma_addr); /* for FLOW ctrl */ int(*enable_rx_flow_ctrl) (void); int(*disable_rx_flow_ctrl) (void); int(*enable_tx_flow_ctrl) (uint32_t); int(*disable_tx_flow_ctrl) (uint32_t); /* for PMT operations */ int(*enable_magic_pmt) (void); int(*disable_magic_pmt) (void); int(*enable_remote_pmt) (void); int(*disable_remote_pmt) (void); int(*configure_rwk_filter) (uint32_t *, uint32_t); /* for RX watchdog timer */ int(*config_rx_watchdog) (uint32_t, uint32_t riwt); /* for RX and TX threshold config */ int(*config_rx_threshold) (uint32_t ch_no, uint32_t val); int(*config_tx_threshold) (uint32_t ch_no, uint32_t val); /* for RX and TX Store and Forward Mode config */ int(*config_rsf_mode) (uint32_t ch_no, uint32_t val); int(*config_tsf_mode) (uint32_t ch_no, uint32_t val); /* for TX DMA Operate on Second Frame config */ int(*config_osf_mode) (uint32_t ch_no, uint32_t val); /* for INCR/INCRX config */ int(*config_incr_incrx_mode) (uint32_t val); /* for AXI PBL config */ int(*config_axi_pbl_val) (uint32_t val); /* for AXI WORL config */ int(*config_axi_worl_val) (uint32_t val); /* for AXI RORL config */ int(*config_axi_rorl_val) (uint32_t val); /* for RX and TX PBL config */ int(*config_rx_pbl_val) (uint32_t ch_no, uint32_t val); int(*get_rx_pbl_val) (uint32_t ch_no); int(*config_tx_pbl_val) (uint32_t ch_no, uint32_t val); int(*get_tx_pbl_val) (uint32_t ch_no); int(*config_pblx8) (uint32_t ch_no, uint32_t val); /* for TX vlan control */ void(*enable_vlan_reg_control) (struct DWC_ETH_QOS_tx_wrapper_descriptor *desc_data); void(*enable_vlan_desc_control) (struct DWC_ETH_QOS_prv_data *pdata); /* for sa(source address) insert/replace */ void(*configure_sa_via_reg) (uint32_t); /* for handling rx interrupts */ void(*disable_rx_interrupt)(uint32_t, hw_config_t *); void(*enable_rx_interrupt)(uint32_t, hw_config_t *); /* for handling tx interrupts */ void(*disable_tx_interrupt)(uint32_t, hw_config_t *); void(*enable_tx_interrupt)(uint32_t, hw_config_t *); /* for handling MMC */ int(*disable_mmc_interrupts)(void); int(*config_mmc_counters)(void); /* for handling split header */ int(*config_split_header_mode)(uint32_t qInx, uint16_t sph_en); int(*config_header_size)(uint16_t header_size); /* for handling DCB and AVB */ int(*set_dcb_algorithm)(uint8_t dcb_algorithm); int(*set_dcb_queue_weight)(uint32_t qInx, uint32_t q_weight); int(*set_tx_queue_operating_mode)(uint32_t qInx, uint32_t q_mode); int(*set_avb_algorithm)(uint32_t qInx, uint8_t avb_algorithm); int(*config_credit_control)(uint32_t qInx, uint32_t cc); int(*config_send_slope)(uint32_t qInx, uint32_t send_slope); int(*config_idle_slope)(uint32_t qInx, uint32_t idle_slope); int(*config_high_credit)(uint32_t qInx, uint32_t hi_credit); int(*config_low_credit)(uint32_t qInx, uint32_t lo_credit); int(*config_slot_num_check)(uint32_t qInx, uint8_t slot_check); int(*config_advance_slot_num_check)(uint32_t qInx, uint8_t adv_slot_check); /* for hw time stamping */ int(*config_hw_time_stamping)(uint32_t); int(*config_sub_second_increment)(unsigned long ptp_clock); int(*init_systime)(uint32_t, uint32_t); int(*config_addend)(uint32_t); int(*adjust_systime)(uint32_t, uint32_t, int, bool); uint64_t(*get_systime)(void); uint32_t(*get_tx_tstamp_status)(tx_descriptor_t *txdesc); uint64_t(*get_tx_tstamp)(tx_descriptor_t *txdesc); uint32_t(*get_tx_tstamp_status_via_reg)(void); uint64_t(*get_tx_tstamp_via_reg)(void); uint32_t(*rx_tstamp_available)(rx_descriptor_t *rxdesc); uint32_t(*get_rx_tstamp_status)(rx_descriptor_t *rxdesc); uint64_t(*get_rx_tstamp)(rx_descriptor_t *rxdesc); int(*drop_tx_status_enabled)(void); /* for l2, l3 and l4 layer filtering */ int(*config_l2_da_perfect_inverse_match)(int perfect_inverse_match); int(*update_mac_addr)(int idx, uint8_t addr[]); int(*update_hash_table_reg)(int idx, uint32_t data); int(*config_mac_pkt_filter_reg)(uint8_t, uint8_t, uint8_t, uint8_t, uint8_t); int(*config_l3_l4_filter_enable)(int); int(*config_l3_filters)(int filter_no, int enb_dis, int ipv4_ipv6_match, int src_dst_addr_match, int perfect_inverse_match); int(*update_ip4_addr0)(int filter_no, uint8_t addr[]); int(*update_ip4_addr1)(int filter_no, uint8_t addr[]); int(*update_ip6_addr)(int filter_no, uint16_t addr[]); int(*config_l4_filters)(int filter_no, int enb_dis, int tcp_udp_match, int src_dst_port_match, int perfect_inverse_match); int(*update_l4_sa_port_no)(int filter_no, uint16_t port_no); int(*update_l4_da_port_no)(int filter_no, uint16_t port_no); /* for VLAN filtering */ int(*get_vlan_hash_table_reg)(void); int(*update_vlan_hash_table_reg)(uint16_t data); int(*update_vlan_id)(uint16_t vid); int(*config_vlan_filtering)(int filter_enb_dis, int perfect_hash_filtering, int perfect_inverse_match); int(*config_mac_for_vlan_pkt)(void); uint32_t(*get_vlan_tag_comparison)(void); /* for differnet PHY interconnect */ int(*control_an)(bool enable, bool restart); int(*get_an_adv_pause_param)(void); int(*get_an_adv_duplex_param)(void); int(*get_lp_an_adv_pause_param)(void); int(*get_lp_an_adv_duplex_param)(void); /* for EEE */ int(*set_eee_mode)(void); int(*reset_eee_mode)(void); int(*set_eee_pls)(int phy_link); int(*set_eee_timer)(int lpi_lst, int lpi_twt); uint32_t(*get_lpi_status)(void); int(*set_lpi_tx_automate)(void); /* for ARP */ int(*config_arp_offload)(int enb_dis); int(*update_arp_offload_ip_addr)(uint8_t addr[], uint32_t version); /* for MAC loopback */ int(*config_mac_loopback_mode)(uint32_t); /* for MAC Double VLAN Processing config */ int(*config_tx_vlan)(uint32_t op_type, uint32_t vlan_tag, bool inner_tag); int(*config_svlan)(uint32_t); void(*config_dvlan)(bool enb_dis); void(*config_rx_outer_vlan_stripping)(uint32_t); void(*config_rx_inner_vlan_stripping)(uint32_t); /* for PFC */ void (*config_pfc)(int enb_dis); /* for PTP offloading */ void(*config_ptpoffload_engine)(uint32_t, uint32_t); } hw_interface_t; /* wrapper buffer structure to hold transmit pkt details */ struct DWC_ETH_QOS_tx_buffer { dma_addr_t dma; /* dma address of skb */ struct sk_buff *skb; /* virtual address of skb */ unsigned short len; /* length of first skb */ unsigned char buf1_mapped_as_page; dma_addr_t dma2; /* dam address of second skb */ unsigned short len2; /* length of second skb */ unsigned char buf2_mapped_as_page; }; struct DWC_ETH_QOS_tx_wrapper_descriptor { char *desc_name; /* ID of descriptor */ void *tx_desc_ptrs[TX_DESC_CNT]; dma_addr_t tx_desc_dma_addrs[TX_DESC_CNT]; struct DWC_ETH_QOS_tx_buffer *tx_buf_ptrs[TX_DESC_CNT]; unsigned char contigous_mem; int cur_tx; /* always gives index of desc which has to be used for current xfer */ int dirty_tx; /* always gives index of desc which has to be checked for xfer complete */ unsigned int free_desc_cnt; /* always gives total number of available free desc count for driver */ unsigned int tx_pkt_queued; /* always gives total number of packets queued for transmission */ unsigned int queue_stopped; int packet_count; uint32_t tx_threshold_val; /* contain bit value for TX threshold */ uint32_t tsf_on; /* set to 1 if TSF is enabled else set to 0 */ uint32_t osf_on; /* set to 1 if OSF is enabled else set to 0 */ uint32_t tx_pbl; /* for tx vlan delete/insert/replace */ uint32_t tx_vlan_tag_via_reg; uint32_t tx_vlan_tag_ctrl; uint16_t vlan_tag_id; uint32_t vlan_tag_present; /* for VLAN context descriptor operation */ uint32_t context_setup; /* for TSO */ uint32_t default_mss; }; struct DWC_ETH_QOS_tx_queue { /* Tx descriptors */ struct DWC_ETH_QOS_tx_wrapper_descriptor tx_desc_data; int q_op_mode; }; /* wrapper buffer structure to hold received pkt details */ struct DWC_ETH_QOS_rx_buffer { dma_addr_t dma; /* dma address of skb */ struct sk_buff *skb; /* virtual address of skb */ unsigned short len; /* length of received packet */ struct page *page; /* page address */ unsigned char mapped_as_page; bool good_pkt; /* set to 1 if it is good packet else set to 0 */ unsigned int inte; /* set to non-zero if INTE is set for corresponding desc */ dma_addr_t dma2; /* dma address of second skb */ struct page *page2; /* page address of second buffer */ unsigned short len2; /* length of received packet-second buffer */ unsigned short rx_hdr_size; /* header buff size in case of split header */ }; struct DWC_ETH_QOS_rx_wrapper_descriptor { char *desc_name; /* ID of descriptor */ void *rx_desc_ptrs[RX_DESC_CNT]; dma_addr_t rx_desc_dma_addrs[RX_DESC_CNT]; struct DWC_ETH_QOS_rx_buffer *rx_buf_ptrs[RX_DESC_CNT]; unsigned char contigous_mem; int cur_rx; /* always gives index of desc which needs to be checked for packet availabilty */ int dirty_rx; unsigned int pkt_received; /* always gives total number of packets received from device in one RX interrupt */ unsigned int skb_realloc_idx; unsigned int skb_realloc_threshold; /* for rx coalesce schem */ int use_riwt; /* set to 1 if RX watchdog timer should be used for RX interrupt mitigation */ uint32_t rx_riwt; uint32_t rx_coal_frames; /* Max no of pkts to be received before an RX interrupt */ uint32_t rx_threshold_val; /* contain bit vlaue for RX threshold */ uint32_t rsf_on; /* set to 1 if RSF is enabled else set to 0 */ uint32_t rx_pbl; struct sk_buff *skb_top; /* points to first skb in the chain in case of jumbo pkts */ /* for rx vlan stripping */ uint32_t rx_inner_vlan_strip; uint32_t rx_outer_vlan_strip; }; struct DWC_ETH_QOS_rx_queue { /* Rx descriptors */ struct DWC_ETH_QOS_rx_wrapper_descriptor rx_desc_data; struct DWC_ETH_QOS_prv_data *pdata; }; struct desc_if_struct { int(*alloc_queue_struct) (struct DWC_ETH_QOS_prv_data *); void(*free_queue_struct) (struct DWC_ETH_QOS_prv_data *); int(*alloc_buff_and_desc) (struct DWC_ETH_QOS_prv_data *); void (*realloc_skb) (struct DWC_ETH_QOS_prv_data *, uint32_t); void (*unmap_rx_skb) (struct DWC_ETH_QOS_prv_data *, struct DWC_ETH_QOS_rx_buffer *); void (*unmap_tx_skb) (struct DWC_ETH_QOS_prv_data *, struct DWC_ETH_QOS_tx_buffer *); unsigned int (*map_tx_skb) (struct net_device *, struct sk_buff *); void (*tx_free_mem) (struct DWC_ETH_QOS_prv_data *); void (*rx_free_mem) (struct DWC_ETH_QOS_prv_data *); void (*wrapper_tx_desc_init) (struct DWC_ETH_QOS_prv_data *); void (*wrapper_tx_desc_init_single_q) (struct DWC_ETH_QOS_prv_data *, uint32_t); void (*wrapper_rx_desc_init) (struct DWC_ETH_QOS_prv_data *); void (*wrapper_rx_desc_init_single_q) (struct DWC_ETH_QOS_prv_data *, uint32_t); void (*rx_skb_free_mem) (struct DWC_ETH_QOS_prv_data *, uint32_t); void (*rx_skb_free_mem_single_q) (struct DWC_ETH_QOS_prv_data *, uint32_t); void (*tx_skb_free_mem) (struct DWC_ETH_QOS_prv_data *, uint32_t); void (*tx_skb_free_mem_single_q) (struct DWC_ETH_QOS_prv_data *, uint32_t); int (*handle_tso) (struct net_device *dev, struct sk_buff *skb); }; /* * This structure contains different flags and each flags will indicates * different hardware features. */ struct DWC_ETH_QOS_hw_features { /* HW Feature Register0 */ unsigned int mii_sel; /* 10/100 Mbps support */ unsigned int gmii_sel; /* 1000 Mbps support */ unsigned int hd_sel; /* Half-duplex support */ unsigned int pcs_sel; /* PCS registers(TBI, SGMII or RTBI PHY interface) */ unsigned int vlan_hash_en; /* VLAN Hash filter selected */ unsigned int sma_sel; /* SMA(MDIO) Interface */ unsigned int rwk_sel; /* PMT remote wake-up packet */ unsigned int mgk_sel; /* PMT magic packet */ unsigned int mmc_sel; /* RMON module */ unsigned int arp_offld_en; /* ARP Offload features is selected */ unsigned int ts_sel; /* IEEE 1588-2008 Adavanced timestamp */ unsigned int eee_sel; /* Energy Efficient Ethernet is enabled */ unsigned int tx_coe_sel; /* Tx Checksum Offload is enabled */ unsigned int rx_coe_sel; /* Rx Checksum Offload is enabled */ unsigned int mac_addr16_sel; /* MAC Addresses 1-16 are selected */ unsigned int mac_addr32_sel; /* MAC Addresses 32-63 are selected */ unsigned int mac_addr64_sel; /* MAC Addresses 64-127 are selected */ unsigned int tsstssel; /* Timestamp System Time Source */ unsigned int speed_sel; /* Speed Select */ unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ unsigned int act_phy_sel; /* Active PHY Selected */ /* HW Feature Register1 */ unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ unsigned int adv_ts_hword; /* Advance timestamping High Word selected */ unsigned int dcb_en; /* DCB Feature Enable */ unsigned int sph_en; /* Split Header Feature Enable */ unsigned int tso_en; /* TCP Segmentation Offload Enable */ unsigned int dma_debug_gen; /* DMA debug registers are enabled */ unsigned int av_sel; /* AV Feature Enabled */ unsigned int lp_mode_en; /* Low Power Mode Enabled */ unsigned int hash_tbl_sz; /* Hash Table Size */ unsigned int l3l4_filter_num; /* Total number of L3-L4 Filters */ /* HW Feature Register2 */ unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ unsigned int pps_out_num; /* Number of PPS outputs */ unsigned int aux_snap_num; /* Number of Auxillary snapshot inputs */ }; /* structure to hold MMC values */ struct DWC_ETH_QOS_mmc_counters { /* MMC TX counters */ unsigned long mmc_tx_octetcount_gb; unsigned long mmc_tx_framecount_gb; unsigned long mmc_tx_broadcastframe_g; unsigned long mmc_tx_multicastframe_g; unsigned long mmc_tx_64_octets_gb; unsigned long mmc_tx_65_to_127_octets_gb; unsigned long mmc_tx_128_to_255_octets_gb; unsigned long mmc_tx_256_to_511_octets_gb; unsigned long mmc_tx_512_to_1023_octets_gb; unsigned long mmc_tx_1024_to_max_octets_gb; unsigned long mmc_tx_unicast_gb; unsigned long mmc_tx_multicast_gb; unsigned long mmc_tx_broadcast_gb; unsigned long mmc_tx_underflow_error; unsigned long mmc_tx_singlecol_g; unsigned long mmc_tx_multicol_g; unsigned long mmc_tx_deferred; unsigned long mmc_tx_latecol; unsigned long mmc_tx_exesscol; unsigned long mmc_tx_carrier_error; unsigned long mmc_tx_octetcount_g; unsigned long mmc_tx_framecount_g; unsigned long mmc_tx_excessdef; unsigned long mmc_tx_pause_frame; unsigned long mmc_tx_vlan_frame_g; unsigned long mmc_tx_osize_frame_g; /* MMC RX counters */ unsigned long mmc_rx_framecount_gb; unsigned long mmc_rx_octetcount_gb; unsigned long mmc_rx_octetcount_g; unsigned long mmc_rx_broadcastframe_g; unsigned long mmc_rx_multicastframe_g; unsigned long mmc_rx_crc_errror; unsigned long mmc_rx_align_error; unsigned long mmc_rx_run_error; unsigned long mmc_rx_jabber_error; unsigned long mmc_rx_undersize_g; unsigned long mmc_rx_oversize_g; unsigned long mmc_rx_64_octets_gb; unsigned long mmc_rx_65_to_127_octets_gb; unsigned long mmc_rx_128_to_255_octets_gb; unsigned long mmc_rx_256_to_511_octets_gb; unsigned long mmc_rx_512_to_1023_octets_gb; unsigned long mmc_rx_1024_to_max_octets_gb; unsigned long mmc_rx_unicast_g; unsigned long mmc_rx_length_error; unsigned long mmc_rx_outofrangetype; unsigned long mmc_rx_pause_frames; unsigned long mmc_rx_fifo_overflow; unsigned long mmc_rx_vlan_frames_gb; unsigned long mmc_rx_watchdog_error; unsigned long mmc_rx_receive_error; unsigned long mmc_rx_ctrl_frames_g; /* IPC */ unsigned long mmc_rx_ipc_intr_mask; unsigned long mmc_rx_ipc_intr; /* IPv4 */ unsigned long mmc_rx_ipv4_gd; unsigned long mmc_rx_ipv4_hderr; unsigned long mmc_rx_ipv4_nopay; unsigned long mmc_rx_ipv4_frag; unsigned long mmc_rx_ipv4_udsbl; /* IPV6 */ unsigned long mmc_rx_ipv6_gd_octets; unsigned long mmc_rx_ipv6_hderr_octets; unsigned long mmc_rx_ipv6_nopay_octets; /* Protocols */ unsigned long mmc_rx_udp_gd; unsigned long mmc_rx_udp_err; unsigned long mmc_rx_tcp_gd; unsigned long mmc_rx_tcp_err; unsigned long mmc_rx_icmp_gd; unsigned long mmc_rx_icmp_err; /* IPv4 */ unsigned long mmc_rx_ipv4_gd_octets; unsigned long mmc_rx_ipv4_hderr_octets; unsigned long mmc_rx_ipv4_nopay_octets; unsigned long mmc_rx_ipv4_frag_octets; unsigned long mmc_rx_ipv4_udsbl_octets; /* IPV6 */ unsigned long mmc_rx_ipv6_gd; unsigned long mmc_rx_ipv6_hderr; unsigned long mmc_rx_ipv6_nopay; /* Protocols */ unsigned long mmc_rx_udp_gd_octets; unsigned long mmc_rx_udp_err_octets; unsigned long mmc_rx_tcp_gd_octets; unsigned long mmc_rx_tcp_err_octets; unsigned long mmc_rx_icmp_gd_octets; unsigned long mmc_rx_icmp_err_octets; }; struct DWC_ETH_QOS_extra_stats { uint32_t q_re_alloc_rx_buf_failed[8]; /* Tx/Rx IRQ error info */ uint32_t tx_process_stopped_irq_n[8]; uint32_t rx_process_stopped_irq_n[8]; uint32_t tx_buf_unavailable_irq_n[8]; uint32_t rx_buf_unavailable_irq_n[8]; uint32_t rx_watchdog_irq_n; uint32_t fatal_bus_error_irq_n; uint32_t pmt_irq_n; /* Tx/Rx IRQ Events */ uint32_t tx_normal_irq_n[8]; uint32_t rx_normal_irq_n[8]; uint32_t napi_poll_n; uint32_t tx_clean_n[8]; /* EEE */ uint32_t tx_path_in_lpi_mode_irq_n; uint32_t tx_path_exit_lpi_mode_irq_n; uint32_t rx_path_in_lpi_mode_irq_n; uint32_t rx_path_exit_lpi_mode_irq_n; /* Tx/Rx frames */ uint32_t tx_pkt_n; uint32_t rx_pkt_n; uint32_t tx_vlan_pkt_n; uint32_t rx_vlan_pkt_n; uint32_t tx_timestamp_captured_n; uint32_t rx_timestamp_captured_n; uint32_t tx_tso_pkt_n; uint32_t rx_split_hdr_pkt_n; /* Tx/Rx frames per channels/queues */ uint32_t q_tx_pkt_n[8]; uint32_t q_rx_pkt_n[8]; }; struct DWC_ETH_QOS_prv_data { struct net_device *dev; struct pci_dev *pdev; spinlock_t lock; spinlock_t tx_lock; spinlock_t pmt_lock; uint32_t mem_start_addr; uint32_t mem_size; int irq_number; hw_interface_t hw_if; hw_config_t hw_cfg; struct desc_if_struct desc_if; // uint32_t tx_error_counters; uint32_t rx_error_counters; rx_pkt_features_t rx_pkt_features; tx_pkt_features_t tx_pkt_features; /* TX Queue */ struct DWC_ETH_QOS_tx_queue *tx_queue; uint8_t tx_queue_cnt; uint32_t tx_qInx; /* RX Queue */ struct DWC_ETH_QOS_rx_queue *rx_queue; struct napi_struct rx_napi; uint8_t rx_queue_cnt; uint32_t rx_qInx; struct hrtimer rx_itr_timer; bool rx_napi_pending; struct mii_bus *mii; struct phy_device *phydev; int oldlink; int speed; int oldduplex; int phyaddr; int bus_id; uint32_t dev_state; uint32_t interface; /* saving state for Wake-on-LAN */ int wolopts; /* Helper macros for handling FLOW control in HW */ #define DWC_ETH_QOS_FLOW_CTRL_OFF 0 #define DWC_ETH_QOS_FLOW_CTRL_RX 1 #define DWC_ETH_QOS_FLOW_CTRL_TX 2 #define DWC_ETH_QOS_FLOW_CTRL_TX_RX (DWC_ETH_QOS_FLOW_CTRL_TX |\ DWC_ETH_QOS_FLOW_CTRL_RX) unsigned int flow_ctrl; /* keeps track of previous programmed flow control options */ unsigned int oldflow_ctrl; struct DWC_ETH_QOS_hw_features hw_feat; /* for sa(source address) insert/replace */ uint32_t tx_sa_ctrl_via_desc; uint32_t tx_sa_ctrl_via_reg; unsigned char mac_addr[DWC_ETH_QOS_MAC_ADDR_LEN]; /* Keeps track of power mode */ uint32_t power_state; /* AXI parameters */ uint32_t incr_incrx; uint32_t axi_pbl; uint32_t axi_worl; uint32_t axi_rorl; /* for hanlding jumbo frames and split header feature on rx path */ int (*clean_rx) (struct DWC_ETH_QOS_prv_data *pdata, int quota, uint32_t qInx); int (*alloc_rx_buf) (struct DWC_ETH_QOS_prv_data *pdata, struct DWC_ETH_QOS_rx_buffer *buffer, gfp_t gfp); unsigned int rx_buffer_len; /* variable frame burst size */ uint32_t drop_tx_pktburstcnt; unsigned int mac_enable_count; /* counter for enabling MAC transmit at drop tx packet */ struct DWC_ETH_QOS_mmc_counters mmc; struct DWC_ETH_QOS_extra_stats xstats; /* rx split header mode */ unsigned char rx_split_hdr; /* for MAC loopback */ unsigned int mac_loopback_mode; /* for hw time stamping */ unsigned char hwts_tx_en; unsigned char hwts_rx_en; struct ptp_clock *ptp_clock; struct ptp_clock_info ptp_clock_ops; spinlock_t ptp_lock; /* protects registers */ unsigned int default_addend; bool one_nsec_accuracy; /* set to 1 if one nano second accuracy is enabled else set to zero */ /* for filtering */ int max_hash_table_size; int max_addr_reg_cnt; /* L3/L4 filtering */ unsigned int l3_l4_filter; unsigned char vlan_hash_filtering; unsigned int l2_filtering_mode; /* 0 - if perfect and 1 - if hash filtering */ /* For handling PCS(TBI/RTBI/SGMII) and RGMII/SMII interface */ unsigned int pcs_link; unsigned int pcs_duplex; unsigned int pcs_speed; unsigned int pause; unsigned int duplex; unsigned int lp_pause; unsigned int lp_duplex; /* for handling EEE */ struct timer_list eee_ctrl_timer; bool tx_path_in_lpi_mode; bool use_lpi_tx_automate; int eee_enabled; int eee_active; int tx_lpi_timer; /* arp offload enable/disable. */ uint32_t arp_offload; /* set to 1 when ptp offload is enabled, else 0. */ uint32_t ptp_offload; /* ptp offloading mode - ORDINARY_SLAVE, ORDINARY_MASTER, * TRANSPARENT_SLAVE, TRANSPARENT_MASTER, PTOP_TRANSPERENT. * */ uint32_t ptp_offloading_mode; /* For configuring double VLAN via descriptor/reg */ int inner_vlan_tag; int outer_vlan_tag; /* op_type will be * 0/1/2/3 for none/delet/insert/replace respectively * */ int op_type; /* in_out will be * 1/2/3 for outer/inner/both respectively. * */ int in_out; /* 0 for via registers and 1 for via descriptor */ int via_reg_or_desc; /* this variable will hold vlan table value if vlan hash filtering * is enabled else hold vlan id that is programmed in HW. Same is * used to configure back into HW when device is reset during * jumbo/split-header features. * */ uint32_t vlan_ht_or_id; /* Used when LRO is enabled, * set to 1 if skb has TCP payload else set to 0 * */ int tcp_pkt; void __iomem *gbe_base; e_GBE_mux_config mux_cfg; uint32_t version; uint32_t rate; uint32_t itr_latency; /* In nano-seconds */ struct device_attribute rate_attr; struct device_attribute stats_attr; struct device_attribute itr_lat_attr; #ifdef GBE_DEBUG struct device_attribute debug_attr; struct device_attribute suspend_attr; #endif #ifdef GBE_POLLING struct hrtimer gbe_timer; #endif }; typedef enum { GBE_STOP_STATE, GBE_RUN_STATE, GBE_STANDBY_STATE } gbe_power_state_t; /* Function prototypes*/ void DWC_ETH_QOS_init_function_ptrs_dev(hw_interface_t *); void DWC_ETH_QOS_init_function_ptrs_desc(struct desc_if_struct *); struct net_device_ops *DWC_ETH_QOS_get_netdev_ops(void); struct ethtool_ops *DWC_ETH_QOS_get_ethtool_ops(void); int DWC_ETH_QOS_poll_rx(struct napi_struct *, int); void DWC_ETH_QOS_get_pdata(struct DWC_ETH_QOS_prv_data *pdata); /* Debugfs related functions. */ int create_debug_files(void); void remove_debug_files(void); int DWC_ETH_QOS_mdio_register(struct net_device *dev); void DWC_ETH_QOS_mdio_unregister(struct net_device *dev); int DWC_ETH_QOS_mdio_read_direct(struct DWC_ETH_QOS_prv_data *pdata, int phyaddr, int phyreg, int *phydata); int DWC_ETH_QOS_mdio_write_direct(struct DWC_ETH_QOS_prv_data *pdata, int phyaddr, int phyreg, int phydata); int DWC_ETH_QOS_mdio_read_ext(int regaddr, int *phydata); int DWC_ETH_QOS_mdio_write_ext(int regaddr, int phydata); void dbgpr_regs(void); void dump_phy_registers(struct DWC_ETH_QOS_prv_data *); void dump_tx_desc(struct DWC_ETH_QOS_prv_data *pdata, int first_desc_idx, int last_desc_idx, int flag, uint32_t qInx); void dump_rx_desc(uint32_t, rx_descriptor_t *desc, int cur_rx); void print_pkt(struct sk_buff *skb, int len, bool tx_rx, int desc_idx); void DWC_ETH_QOS_get_all_hw_features(struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_print_all_hw_features(struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_configure_flow_ctrl(struct DWC_ETH_QOS_prv_data *pdata); int DWC_ETH_QOS_powerup(struct net_device *); int DWC_ETH_QOS_powerdown(struct net_device *, uint32_t); uint32_t DWC_ETH_QOS_usec2riwt(uint32_t usec, struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_init_rx_coalesce(struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_enable_rx_interrupts(struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_disable_rx_interrupts(struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_update_rx_errors(struct net_device *, unsigned int); uint8_t get_tx_queue_count(void); uint8_t get_rx_queue_count(void); void DWC_ETH_QOS_mmc_read(struct DWC_ETH_QOS_mmc_counters *mmc); uint32_t DWC_ETH_QOS_get_total_desc_cnt(struct DWC_ETH_QOS_prv_data *pdata, struct sk_buff *skb, uint32_t qInx); int DWC_ETH_QOS_ptp_init(struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_ptp_remove(struct DWC_ETH_QOS_prv_data *pdata); phy_interface_t DWC_ETH_QOS_get_phy_interface(struct DWC_ETH_QOS_prv_data *pdata); bool DWC_ETH_QOS_eee_init(struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_handle_eee_interrupt(struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_disable_eee_mode(struct DWC_ETH_QOS_prv_data *pdata); void DWC_ETH_QOS_enable_eee_mode(struct DWC_ETH_QOS_prv_data *pdata); #define MIN(a,b) ((a) < (b))? (a) : (b) /* For debug prints*/ #define DRV_NAME "DWC_ETH_QOS_drv.c" #ifdef YDEBUG #define DBGPR(x...) printk(KERN_ALERT x) #define DBGPHY_REGS(x...) dump_phy_registers(x) #else #define DBGPR(x...) do { } while (0) #define DBGPHY_REGS(x...) do { } while (0) #endif #ifdef YDEBUG_PG #define DBGPR_PG(x...) printk(KERN_ALERT x) #else #define DBGPR_PG(x...) do {} while (0) #endif #ifdef YDEBUG_MDIO #define DBGPR_MDIO(x...) printk(KERN_ALERT x) #else #define DBGPR_MDIO(x...) do {} while (0) #endif #ifdef YDEBUG_PTP #define DBGPR_PTP(x...) printk(KERN_ALERT x) #else #define DBGPR_PTP(x...) do {} while (0) #endif #ifdef YDEBUG_FILTER #define DBGPR_FILTER(x...) printk(KERN_ALERT x) #else #define DBGPR_FILTER(x...) do {} while (0) #endif #ifdef YDEBUG_EEE #define DBGPR_EEE(x...) printk(KERN_ALERT x) #else #define DBGPR_EEE(x...) do {} while (0) #endif extern bool config_prints; #define CFG_PRINT(x...) \ do { \ if(config_prints) { \ printk(KERN_INFO x); \ } \ } while (0) #define ERR_PRINT(x) \ printk(KERN_ERR "[%s] ERROR: " x, __FUNCTION__) #define WRN_PRINT(x) \ printk(KERN_ALERT "[%s] WARNING: " x, __FUNCTION__) #ifdef GBE_DEBUG extern bool print_desc; extern uint metadata_on_crc; #define PRINT_TX_DESC(DESC, TYPE) \ do { \ if(print_desc) { \ printk(KERN_INFO "[TX_DESC:%s] 0x%08x:0x%08x:0x%08x:0x%08x\n", #TYPE, \ (DESC)->TDES0, (DESC)->TDES1, (DESC)->TDES2, (DESC)->TDES3); \ } \ } while (0) #endif //GBE_DEBUG uint32_t gbe_config_to_speed(uint32_t config); extern unsigned int gmac5to4_speed; unsigned int gbe_get_4to5_speed(void); #endif