/* * int34d9-regulator.h - Puma7 SoC PMIC Driver * * Copyright (C) 2015 - 2018 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License version * 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * */ #ifndef __LINUX_REGULATOR_INT34D9_H__ #define __LINUX_REGULATOR_INT34D9_H__ #include #include #include enum PUMA7_PMIC_REGULATOR_SUPPLIES { PUMA7_PMIC_VPLT, PUMA7_PMIC_VCC0, PUMA7_PMIC_V3P3_EXT, PUMA7_PMIC_VNN, PUMA7_PMIC_V1P15, PUMA7_PMIC_V1P05A, PUMA7_PMIC_VDDQ, PUMA7_PMIC_V1P8A, PUMA7_PMIC, PUMA7_PMIC_SUPPLY_NUMBER }; #define PUMA7_PMIC_MODE_ACTIVE 0x1 #define PUMA7_PMIC_MODE_BBU 0x2 #define PUMA7_PMIC_MODE_FAST_STANDBY 0x4 #define PUMA7_PMIC_MODE_DEEP_STANDBY 0x8 #define PUMA7_PMIC_LPM_CFG_ACTIVE 0x0 #define PUMA7_PMIC_LPM_CFG_BBU 0x19 #define PUMA7_PMIC_LPM_CFG_FAST_STANDBY 0x1F #define PUMA7_PMIC_LPM_CFG_DEEP_STANDBY 0xFF #define PUMA7_PMIC_LPMCTRL_REG 0x54 #define PUMA7_PMIC_LPM_CFG_MASK 0xF4 #define PUMA7_PMIC_IRQLVL1_REG 0x02 #define PUMA7_PMIC_IRQLVL1_THRM 0x02 #define PUMA7_PMIC_IRQLVL1_PWRSRC 0x01 #define PUMA7_PMIC_THRMIRQ_REG 0x05 #define PUMA7_PMIC_THRMIRQ_PMICHOT 0x01 #define PUMA7_PMIC_PWRSRCIRQ_REG 0x03 #define PUMA7_PMIC_THRMIRQ_DCINDET 0x02 #define PUMA7_PMIC_MIRQLVL1_REG 0x0E #define PUMA7_PMIC_MTHRMIRQ_REG 0x12 #define PUMA7_PMIC_MPWRSRCIRQS0_REG 0x0F #define PUMA7_PMIC_MPWRSRCIRQSX_REG 0x10 #define PUMA7_PMIC_SPWRSRC_REG 0x1E #define PUMA7_PMIC_SPWRSRC_SDCINDET 0x02 #define PUMA7_PMIC_VPLT_EN_MASK 0x80 #define PUMA7_PMIC_VCC0_EN_MASK 0x40 #define PUMA7_PMIC_V3P3_EXT_EN_MASK 0x20 #define PUMA7_PMIC_VNN_EN_MASK 0x10 #define PUMA7_PMIC_V1P15_EN_MASK 0x08 #define PUMA7_PMIC_V1P05A_EN_MASK 0x04 #define PUMA7_PMIC_VDDQ_EN_MASK 0x02 #define PUMA7_PMIC_V1P8A_EN_MASK 0x01 #define PUMA7_PMIC_EN_MASK 0xFF #define PUMA7_PMIC_THERMAL_NOTIFY_CRITICAL 0x90 #define PUMA7_PMIC_BATTERY_NOTIFY_STATUS_CHANGE 0x82 #define ACPI_PUMA7_PMIC_CLASS "regulator" #define ACPI_PUMA7_PMIC_DEVICE_NAME "INT34D9" #define NAME_MAX_LEN 40 /** * List of Rohm/Holtek-Device Register */ #define PUMA7_PMIC_REG_ID0 0x00 #define PUMA7_PMIC_REG_REV 0x01 #define PUMA7_PMIC_REG_IRQLVL1 0x02 #define PUMA7_PMIC_REG_PWRSRCIRQ 0x03 #define PUMA7_PMIC_REG_VRIRQ 0x04 #define PUMA7_PMIC_REG_THRMIRQ 0x05 #define PUMA7_PMIC_REG_MIRQLVL1 0x0E #define PUMA7_PMIC_REG_MPWRSRCIRQS0 0x0F #define PUMA7_PMIC_REG_MPWRSRCIRQSX 0x10 #define PUMA7_PMIC_REG_MVRIRQ 0x11 #define PUMA7_PMIC_REG_MTHRMIRQ 0x12 #define PUMA7_PMIC_REG_SPWRSRC 0x1E #define PUMA7_PMIC_REG_REGLOCK 0x1F #define PUMA7_PMIC_REG_RESETSRC0 0x20 #define PUMA7_PMIC_REG_WAKESRC 0x22 #define PUMA7_PMIC_REG_PSDETCTRL 0x25 #define PUMA7_PMIC_REG_COLDRST 0x53 #define PUMA7_PMIC_REG_LPMCTRL 0x54 #define PUMA7_PMIC_REG_VDDQVTTCNT 0x55 #define PUMA7_PMIC_REG_V1P8ACNT 0x56 #define PUMA7_PMIC_REG_VDDQCNT 0x58 #define PUMA7_PMIC_REG_V1P05ACNT 0x63 #define PUMA7_PMIC_REG_V1P15CNT 0x64 #define PUMA7_PMIC_REG_V3P3SOCCNT 0x65 #define PUMA7_PMIC_REG_VSYSPLTCNT 0x66 #define PUMA7_PMIC_REG_V3P3EXTCNT 0x67 #define PUMA7_PMIC_REG_PWROKCNTL 0x6B #define PUMA7_PMIC_REG_FWREV 0x6D #define PUMA7_PMIC_REG_PWRGDMSK 0x6E #define PUMA7_PMIC_REG_RCVCFG 0x6F #define PUMA7_PMIC_REG_RCVNUM 0x70 #define PUMA7_PMIC_REG_SRCWAKECFG 0x8B #define PUMA7_PMIC_REG_PWRSEQCFG 0x8C #define PUMA7_PMIC_REG_VRFAULTEN 0x90 #define PUMA7_PMIC_REG_MVRFLTMASK0 0x91 #define PUMA7_PMIC_REG_MVRFLTMASK1 0x92 #define PUMA7_PMIC_REG_MVRFLTMASK2 0x93 #define PUMA7_PMIC_REG_LPMCTRL2 0x94 #define PUMA7_PMIC_REG_VCC0_STATUS1 0x10 #define PUMA7_PMIC_REG_VCC0_VBoot 0x26 #define PUMA7_PMIC_REG_VCC0_VSlew 0x2A #define PUMA7_PMIC_REG_VCC0_Vout_max 0x30 #define PUMA7_PMIC_REG_VCC0_VID 0x31 #define PUMA7_PMIC_REG_VCC0_PWRSTATE 0x32 #define PUMA7_PMIC_REG_VNN_STATUS1 0x10 #define PUMA7_PMIC_REG_VNN_VBoot 0x26 #define PUMA7_PMIC_REG_VNN_VSlew 0x2A #define PUMA7_PMIC_REG_VNN_Vout_max 0x30 #define PUMA7_PMIC_REG_VNN_VID 0x31 #define PUMA7_PMIC_REG_VNN_PWRSTATE 0x32 #define PUMA7_PMIC_REG_VNN_S0IX_VID 0x39 #define PUMA7_PMIC_REG_VNN_PHSEL 0x3A #define PUMA7_PMIC_REG_VNN_VAUXCNT 0x3B /** * struct puma7_pmic_subdev_data - regulator subdev data * @id: regulator id * @name: name of regulator * @regulator_data: regulator initialisation data */ struct puma7_pmic_subdev_data { int id; char name[NAME_MAX_LEN]; struct regulator_init_data regulator_data; }; /** * struct puma7_pmic_platform_data - platform data for PUMA7 PMIC * @num_subdevs: total number of regulators * @subdevs: pointer to regulatrs used */ struct puma7_pmic_platform_data { int num_subdevs; struct puma7_pmic_subdev_data *subdevs; }; /* Used to apply additional sub-devices. * Note: Page1 is already handled by main i2c_client. */ enum PMIC_PAGES { PMIC_PAGE0, PMIC_PAGE2, PMIC_PAGE3, PMIC_EXTRA_PAGECNT, PMIC_PAGE_MAIN = PMIC_EXTRA_PAGECNT, }; /** * struct puma7_pmic - Puma7 PMIC device * @client: points to i2c slave PMIC device * @handle: handle to the ACPI PMIC device * @mode: Low power mode * @platform_data: platform data for PUMA7 PMIC * @pages: three(!) additional sub_devices * @rdev: points to regulator device within PMIC */ struct puma7_pmic { struct i2c_client *client; acpi_handle handle; int mode; struct puma7_pmic_platform_data platform_data; struct i2c_client *pages[PMIC_EXTRA_PAGECNT]; struct regulator_dev *rdev[]; }; #endif /* __LINUX_REGULATOR_INT34D9_H__ */