--- zzzz-none-000/linux-4.9.279/drivers/acpi/acpi_lpss.c	2021-08-08 06:38:54.000000000 +0000
+++ puma7-atom-6591-750/linux-4.9.279/drivers/acpi/acpi_lpss.c	2023-02-08 11:43:42.000000000 +0000
@@ -57,6 +57,9 @@
 #define LPSS_LTR_MAX_VAL		0x3FF
 #define LPSS_TX_INT			0x20
 #define LPSS_TX_INT_MASK		BIT(1)
+/* CHT LPSS I2C PRIVATE OFFSET*/
+#define LPSS_CLOCK_PARAMS		0x00
+#define HS_SOURCE_CLOCK			BIT(0)
 
 #define LPSS_PRV_REG_COUNT		9
 
@@ -240,6 +243,30 @@
 	.setup = lpss_deassert_reset,
 };
 
+static void cht_i2c_setup(struct lpss_private_data *pdata)
+{
+	const struct lpss_device_desc *dev_desc = pdata->dev_desc;
+	unsigned int offset;
+	u32 reg;
+
+	offset = dev_desc->prv_offset + LPSS_CLOCK_PARAMS;
+    if (pdata->mmio_base != NULL){
+        reg = readl(pdata->mmio_base + offset);
+
+        /* indicate if the i2c uses 133MHz or 100Mhz */
+		if (reg & HS_SOURCE_CLOCK)
+			pdata->fixed_clk_rate = 133000000;
+    }
+}
+
+static struct lpss_device_desc cht_i2c_dev_desc = {
+	.flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
+			| LPSS_NO_D3_DELAY,
+	.clk_con_id = "baudclk",
+	.prv_offset = 0x800,
+	.setup = cht_i2c_setup,
+};
+
 #define ICPU(model)	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 
 static const struct x86_cpu_id lpss_cpu_ids[] = {
@@ -277,6 +304,14 @@
 	{ "INT33B2", },
 	{ "INT33FC", },
 
+	/* Cherrytrail LPSS devices */
+	{ "808622C1", (unsigned long)&cht_i2c_dev_desc },
+	{ "8086228A", (unsigned long)&byt_uart_dev_desc },
+	{ "80862286", (unsigned long)&lpss_dma_desc },
+	{ "808622C0", (unsigned long)&lpss_dma_desc },
+	{ "8086228E", (unsigned long)&byt_spi_dev_desc },
+	{ "80862288", }, /* CHT PWM */
+
 	/* Braswell LPSS devices */
 	{ "80862286", LPSS_ADDR(lpss_dma_desc) },
 	{ "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
@@ -285,6 +320,13 @@
 	{ "808622C0", LPSS_ADDR(lpss_dma_desc) },
 	{ "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
 
+	/* Puma7 LPSS devices */
+	{ "80862BC1", (unsigned long)&cht_i2c_dev_desc },
+	{ "80862B8A", (unsigned long)&byt_uart_dev_desc },
+	{ "80862B86", (unsigned long)&lpss_dma_desc },
+	{ "80862BC0", (unsigned long)&lpss_dma_desc },
+	{ "80862B8E", (unsigned long)&byt_spi_dev_desc },
+
 	/* Broadwell LPSS devices */
 	{ "INT3430", LPSS_ADDR(lpt_dev_desc) },
 	{ "INT3431", LPSS_ADDR(lpt_dev_desc) },
@@ -417,11 +459,20 @@
 				pdata->mmio_size = dev_desc->prv_size_override;
 			else
 				pdata->mmio_size = resource_size(rentry->res);
+
+			if (!pdata->mmio_size || !rentry->res->start) {
+				ret = -ENXIO;
+				goto err_out;
+			}
 			pdata->mmio_base = ioremap(rentry->res->start,
 						   pdata->mmio_size);
 			break;
 		}
-
+	if (!pdata->mmio_base) {
+		dev_warn(&adev->dev, "mmio_base address is NULL\n");
+		ret = -EFAULT;
+		goto err_out;
+	}
 	acpi_dev_free_resource_list(&resource_list);
 
 	if (!pdata->mmio_base) {
@@ -434,6 +485,13 @@
 	if (dev_desc->setup)
 		dev_desc->setup(pdata);
 
+	/*
+	 * This works around a known issue in ACPI tables where LPSS devices
+	 * have _PS0 and _PS3 without _PSC (and no power resources), so
+	 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
+	 */
+	acpi_device_fix_up_power(adev);
+
 	if (dev_desc->flags & LPSS_CLK) {
 		ret = register_device_clock(adev, pdata);
 		if (ret) {
@@ -443,13 +501,6 @@
 		}
 	}
 
-	/*
-	 * This works around a known issue in ACPI tables where LPSS devices
-	 * have _PS0 and _PS3 without _PSC (and no power resources), so
-	 * acpi_bus_init_power() will assume that the BIOS has put them into D0.
-	 */
-	acpi_device_fix_up_power(adev);
-
 	adev->driver_data = pdata;
 	pdev = acpi_create_platform_device(adev, dev_desc->properties);
 	if (!IS_ERR_OR_NULL(pdev)) {