/*
 * intel-ce2700.h
 *
 *  GPL LICENSE SUMMARY
 *
 *  Copyright(c) 2017-2019 Intel Corporation. All rights reserved.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of version 2 of the GNU General Public License as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope that it will be useful, but
 *  WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 *  General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *  The full GNU General Public License is included in this distribution
 *  in the file called LICENSE.GPL.
 *
 *  Contact Information:
 *    Intel Corporation
 *    2200 Mission College Blvd.
 *    Santa Clara, CA  97052
 *
 */
#ifndef _ASM_X86_INTEL_CE2700_H
#define _ASM_X86_INTEL_CE2700_H

#define IOCNFG_OK                 (0)
#define IOCNFG_FAIL               (-1)

#define GPIO_NORTHWEST_REGISTERS_ATOM_UART_TXD_PAD_MSGREGADDR 0x4810
#define GPIO_NORTHWEST_REGISTERS_ATOM_UART_RXD_PAD_MSGREGADDR 0x4820

/*IOSF port*/
#define IOSF_GPIONW_PORT         0x13


#define INTEL_CE2700_MEM_READ_OPCODE  0x00
#define INTEL_CE2700_MEM_WRITE_OPCODE 0x01

/*Pad Control Register 0*/
#define PCR0_GPIOCFG_MASK   (0x700)     /* Bits 10:8  */
#define PCR0_GPIOEN_MASK    (0x8000)    /* Bit 15     */


typedef union {
	struct {
		unsigned int GPIORXState:1; /* GPIO RX State, this is the
					current state of the PAD */
		unsigned int GPIOTXState:1; /* GPIO TX State is register
					that controls the output driven by the
					pad. This only applies when GPIO Config
					is set to enable the TX buffer.*/
		unsigned int GFDebSelect:1; /* Chooses between filtering
					using glitch filter(pulses < ~120nS
					filtered)and the debounce logic
						0 = Glitch Filter Logic
						1 = Debounce Filter*/
		unsigned int PSlewVal:2; /* This field is only used for
						 the following Cherryview pins:
						CX_PRDY_B,CX_PRDY_B_2, TCK,
						TRST_B, TMS, TDI, TDO,
						TDO_2,SVID0_ALERT_B,
						SVID0_DATA,SVID0_CLK,
						PROCHOT_B              */
		unsigned int NStrVal:2; /* Termination strength setting
					for the MSMV CFIO buffer Family.
						00 = 150 ohm Nominal
						01 = 75 ohm Nominal
						10 = 50 ohm Nominal
						11 = 35 ohm Nominal
					This field is only used for the
					following Cherryview pins:
					CX_PRDY_B, CX_PRDY_B_2, TCK,
					TRST_B, TMS, TDI, TDO, TDO_2,
					SVID0_ALERT_B, SVID0_DATA,
					SVID0_CLK, PROCHOT_B                */
		unsigned int GPIO_Light:1; /* This mode disables the
					following fields and muxes function 1
					directly out of the pad.(Pmode,
					GPIOCfg, GPIOEn, XTXEnCfg, GFCfg,
					IOSState, InvRXTX, ODEn)
					0 = Light Mode Disabled
					1 = Light Mode Enabled              */
		unsigned int GPIOCfg:3; /* 0 = GPIO (TX Enabled and RX
					Enabled)
					1 = GPO (TX Enabled and RX Disabled)
					2 = GPI (TX Disabled and RX Enabled)
					3 = Hi-Z (TX Disabled and RX Disabled)
					Others = Reserved          */
		unsigned int NSlewVal:2; /* This field is only used for
					the following Cherryview pins:
					CX_PRDY_B, CX_PRDY_B_2, TCK, TRST_B,
					TMS, TDI, TDO, TDO_2,
					SVID0_ALERT_B, SVID0_DATA, SVID0_CLK,
					PROCHOT_B                   */
		unsigned int PStrVal:2; /* Termination strength setting
					for the MSMV CFIO buffer Family.
						00 = 150 ohm Nominal
						01 = 75 ohm Nominal
						10 = 50 ohm Nominal
						11 = 35 ohm Nominal
					This field is only used for the
					following Cherryview pins:
					CX_PRDY_B, CX_PRDY_B_2,TCK, TRST_B,
					TMS, TDI, TDO, TDO_2,
					SVID0_ALERT_B, SVID0_DATA, SVID0_CLK,
					PROCHOT_B                   */
		unsigned int GPIOEn:1; /* This enables GPIO mode and
					function in Pad Mode no longer
					controls the Pad and the GPIO fields
					control the Pad.
						0 = GPIO disabled and and
						function defined in Pad Mode
						controls the pad.
						1 = GPIO enabled and
						Pad Register controls the pad*/
		unsigned int GPIOPM:4; /* This controls which function
					controls this particular Pad when
					GPIO Enable = 0.  */
		unsigned int TERM:4; /* The Pad Termination state
					defines the different weak pull-up and
					pull-down settings that are supported
					by the buffer.
						[3] 0 = Pulldown, 1 = Pullup.
						[2] = 1k pullup only.MSMV only.
						[1] = 5k
						[0] = 20k             */
		unsigned int RxTxEnCfg:2; /* This field controls the Rx
					and Tx Buffer enables when GPIO mode
					is disabled
						0 =  Function defined in Pad
						Mode controls TX and RX Enables
						1 = Function controls TX
						Enable and RX Always Disabled
						2 = Function controls TX
						Enable and RX Always Enabled
						3 = Both TX and RX Always
						Enabled */
		unsigned int GFCfg:2; /* Enable the Glitch Filter on
					the RX path to deglitch the incoming
					signal. This only makes sense when
					the buffer is configured as an input.
					0 = Disable (Bypass the glitch filter)
					1 = Enable for Edge Detect Only
					2 = Enable for RX Data Only
					3 = Enable for Edge Detectand RX Data*/
		unsigned int IntSel:4; /* The Interrupt Select defines
					which interrupt line driven from the
					GPIO Controller toggles when an
					interrupt is detected on this pad.
					Only applicable when parallel wires
					are used for Interrupt Wire
					Logic with the Interrupt Steering Logic
						0 = Interrupt Line 0
						1 = Interrupt Line 1
						15 = Interrupt Line 15     */
		} field;
	unsigned int val;
} IO_CFG0_t;

int intel_ce2700_config_atom_uartctrl(int enable);

#ifdef CONFIG_INTEL_UART_ENABLE_CONTROL
int intel_ce2700_read_atom_uartctrl(int *enable);
#endif

#endif