/* ========================================================================= * The Synopsys DWC ETHER QOS Software Driver and documentation (hereinafter * "Software") is an unsupported proprietary work of Synopsys, Inc. unless * otherwise expressly agreed to in writing between Synopsys and you. * * The Software IS NOT an item of Licensed Software or Licensed Product under * any End User Software License Agreement or Agreement for Licensed Product * with Synopsys or any supplement thereto. Permission is hereby granted, * free of charge, to any person obtaining a copy of this software annotated * with this license and the Software, to deal in the Software without * restriction, including without limitation the rights to use, copy, modify, * merge, publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, subject * to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * DAMAGE. * ========================================================================= */ #ifndef __DWC_ETH_QOS__REGACC__H__ #define __DWC_ETH_QOS__REGACC__H__ extern uint32_t dwc_eth_qos_pci_base_addr; #define ONE_BIT_MASK (0x1) /* Set value in 32-bit variable specific field */ #define VAR32_SET_FIELD(VAR, FIELD, VAL) \ do { \ VAR &= ~((FIELD ## _MASK) << (FIELD ## _OFF)); \ VAR |= ((VAL & (FIELD ## _MASK)) << (FIELD ## _OFF)); \ } while (0) /* Get value from 32-bit variable specific field */ #define VAR32_GET_FIELD(VAR, FIELD) \ ((VAR >> (FIELD ## _OFF)) & (FIELD ## _MASK)) /* Set bit in 32-bit variable specific field */ #define VAR32_SET_BIT(VAR, FIELD, VAL) \ do { \ VAR &= ~(ONE_BIT_MASK << (FIELD ## _OFF)); \ VAR |= ((VAL & ONE_BIT_MASK) << (FIELD ## _OFF)); \ } while (0) /* Get bit from 32-bit variable specific field */ #define VAR32_GET_BIT(VAR, FIELD) \ ((VAR >> (FIELD ## _OFF)) & ONE_BIT_MASK) /* Read DWC register */ #define DWC_REG_RD(REG) \ ioread32((void *)((volatile uint32_t *)(dwc_eth_qos_pci_base_addr + (REG)))) /* Write DWC register */ #define DWC_REG_WR(REG,VAL) \ iowrite32(VAL, (void *)((volatile uint32_t *)(dwc_eth_qos_pci_base_addr + (REG)))) /* Read specific DWC register field */ #define DWC_REG_RD_FIELD(REG,FIELD) \ ((DWC_REG_RD(REG) >> (FIELD ## _OFF)) & (FIELD ## _MASK)) /* Write specific DWC register field */ #define DWC_REG_WR_FIELD(REG,FIELD,VAL) \ do {\ uint32_t value = 0; \ value = DWC_REG_RD(REG) & (~((FIELD ## _MASK) << (FIELD ## _OFF))); \ value |= (VAL & (FIELD ## _MASK)) << (FIELD ## _OFF); \ DWC_REG_WR(REG, value); \ } while(0) /* Read specific DWC register bit */ #define DWC_REG_RD_BIT(REG,FIELD) \ ((DWC_REG_RD(REG) >> (FIELD ## _OFF)) & ONE_BIT_MASK) /* Write specific DWC register bit */ #define DWC_REG_WR_BIT(REG,FIELD,VAL) \ do {\ uint32_t value = DWC_REG_RD(REG) & (~(ONE_BIT_MASK << (FIELD ## _OFF))); \ value |= (VAL & ONE_BIT_MASK) << (FIELD ## _OFF); \ DWC_REG_WR(REG, value); \ } while(0) /* Read specific DWC register indexed field */ #define DWC_REG_RD_IDX_FIELD(REG,FIELD,IDX) \ ((DWC_REG_RD(REG) >> (FIELD ## _OFF)) & (FIELD ## _MASK)) /* Write specific DWC register indexed field */ #define DWC_REG_WR_IDX_FIELD(REG,FIELD,IDX,VAL) \ do {\ uint32_t value = DWC_REG_RD(REG) & (~((FIELD ## _MASK) << (FIELD(IDX)))); \ value |= (VAL & (FIELD ## _MASK)) << (FIELD(IDX)); \ DWC_REG_WR(REG, value); \ } while(0) /******************************* MAC REGISTERS *******************************/ /* MAC Configuration */ #define MAC_MCR 0x0 #define MAC_MCR_ARPEN_OFF 31 #define MAC_MCR_SARC_OFF 28 #define MAC_MCR_IPC_OFF 27 #define MAC_MCR_IPG_OFF 24 #define MAC_MCR_GPSLCE_OFF 23 #define MAC_MCR_S2KP_OFF 22 #define MAC_MCR_CST_OFF 21 #define MAC_MCR_ACS_OFF 20 #define MAC_MCR_WD_OFF 19 #define MAC_MCR_BE_OFF 18 #define MAC_MCR_JD_OFF 17 #define MAC_MCR_JE_OFF 16 #define MAC_MCR_PS_OFF 15 #define MAC_MCR_FES_OFF 14 #define MAC_MCR_DM_OFF 13 #define MAC_MCR_LM_OFF 12 #define MAC_MCR_ECRSFD_OFF 11 #define MAC_MCR_DO_OFF 10 #define MAC_MCR_DCRS_OFF 9 #define MAC_MCR_DR_OFF 8 #define MAC_MCR_BL_OFF 5 #define MAC_MCR_DC_OFF 4 #define MAC_MCR_PRELEN_OFF 2 #define MAC_MCR_TE_OFF 1 #define MAC_MCR_RE_OFF 0 #define MAC_MCR_SARC_MASK 0x7 #define MAC_MCR_IPG_MASK 0x7 #define MAC_MCR_BL_MASK 0x3 #define MAC_MCR_PRELEN_MASK 0x3 /* MAC Extended Configuration */ #define MAC_MECR 0x4 #define MAC_MECR_EIPG_OFF 25 #define MAC_MECR_EIPGEN_OFF 24 #define MAC_MECR_HDSMS_OFF 20 #define MAC_MECR_USP_OFF 18 #define MAC_MECR_SPEN_OFF 17 #define MAC_MECR_DCRCC_OFF 16 #define MAC_MECR_GPSL_OFF 0 #define MAC_MECR_EIPG_MASK 0x1F #define MAC_MECR_HDSMS_MASK 0x3 #define MAC_MECR_GPSL_MASK 0x7FFF /* MAC Packet Filter */ #define MAC_PFR 0x8 #define MAC_PFR_RA_OFF 31 #define MAC_PFR_DNTU_OFF 21 #define MAC_PFR_IPFE_OFF 20 #define MAC_PFR_VTFE_OFF 16 #define MAC_PFR_HPF_OFF 10 #define MAC_PFR_SAF_OFF 9 #define MAC_PFR_SAIF_OFF 8 #define MAC_PFR_PCF_OFF 6 #define MAC_PFR_DBF_OFF 5 #define MAC_PFR_PM_OFF 4 #define MAC_PFR_DAIF_OFF 3 #define MAC_PFR_HMC_OFF 2 #define MAC_PFR_HUC_OFF 1 #define MAC_PFR_PR_OFF 0 #define MAC_PFR_PCF_MASK 0x3 /* MAC Watchdog Timeout */ #define MAC_WTR 0xc #define MAC_WTR_PWE_OFF 8 #define MAC_WTR_WTO_OFF 0 #define MAC_WTR_WTO_MASK 0xF /* MAC Hash Table [1-7] */ #define MAC_HTR(IDX) (0x10 + ((IDX) * 0x4)) /* MAC VLAN Tag */ #define MAC_VLANTR 0x50 #define MAC_VLANTR_EIVLRXS_OFF 31 #define MAC_VLANTR_EIVLS_OFF 28 #define MAC_VLANTR_ERIVLT_OFF 27 #define MAC_VLANTR_EDVLP_OFF 26 #define MAC_VLANTR_VTHM_OFF 25 #define MAC_VLANTR_EVLRXS_OFF 24 #define MAC_VLANTR_EVLS_OFF 21 #define MAC_VLANTR_DOVLTC_OFF 20 #define MAC_VLANTR_ERSVLM_OFF 19 #define MAC_VLANTR_ESVL_OFF 18 #define MAC_VLANTR_VTIM_OFF 17 #define MAC_VLANTR_ETV_OFF 16 #define MAC_VLANTR_VL_OFF 0 #define MAC_VLANTR_EIVLS_MASK 0x3 #define MAC_VLANTR_EVLS_MASK 0x3 #define MAC_VLANTR_VL_MASK 0xFFFF /* MAC VLAN Hash Table */ #define MAC_VLANHTR 0x58 #define MAC_VLANHTR_VLHT_OFF 0 #define MAC_VLANHTR_VLHT_MASK 0xFFFF /* MAC VLAN Tag Inclusion */ #define MAC_VLAN_OUT_TAG_IDX 0 #define MAC_VLAN_IN_TAG_IDX 1 #define MAC_VLANTIR(IDX) (0x60 + ((IDX) * 4)) #define MAC_VLANTIR_VLTI_OFF 20 #define MAC_VLANTIR_CSVL_OFF 19 #define MAC_VLANTIR_VLP_OFF 18 #define MAC_VLANTIR_VLC_OFF 16 #define MAC_VLANTIR_VLT_OFF 0 #define MAC_VLANTIR_VLC_MASK 0x3 #define MAC_VLANTIR_VLT_MASK 0xFFFF /* MAC Tx Queue Flow Control */ #define MAC_TQFCR(IDX) (0x70 + ((IDX) * 0x4)) #define MAC_TQFCR_PT_OFF 16 #define MAC_TQFCR_DZPQ_OFF 7 #define MAC_TQFCR_PLT_OFF 4 #define MAC_TQFCR_TFE_OFF 1 #define MAC_TQFCR_FCB_OFF 0 #define MAC_TQFCR_PT_MASK 0xFFFF #define MAC_TQFCR_PLT_MASK 0x7 /* MAC Rx Queue Flow Control */ #define MAC_RQFCR 0x90 #define MAC_RQFCR_PFCE_OFF 8 #define MAC_RQFCR_UP_OFF 1 #define MAC_RQFCR_RFE_OFF 0 /* MAC Tx Queue Priority Map 0 */ #define MAC_TQPMR0 0x98 #define MAC_TQPMR0_PSTQ(IDX) ((IDX) * 8) #define MAC_TQPMR0_PSTQ_MASK 0xFF /* MAC Tx Queue Priority Map 1 */ #define MAC_TQPMR1 0x9c #define MAC_TQPMR1_PSTQ(IDX) (((IDX) - 4) * 8) #define MAC_TQPMR1_PSTQ_MASK 0xFF /* MAC Rx Queue Control 0 */ #define MAC_RQCR0 0xa0 #define MAC_RQCR0_QEN(IDX) ((IDX) * 2) #define MAC_RQCR0_QEN_MASK 0x3 /* MAC Rx Queue Control 1 */ #define MAC_RQCR1 0xa4 #define MAC_RQCR1_DCBCPQ_OFF 8 #define MAC_RQCR1_AVPTPQ_OFF 4 #define MAC_RQCR1_AVCPQ_OFF 0 #define MAC_RQCR1_DCBCPQ_MASK 0x7 #define MAC_RQCR1_AVPTPQ_MASK 0x7 #define MAC_RQCR1_AVCPQ_MASK 0x7 #define MAC_RQCR1_MCBCQEN_4_10_OFF 20 #define MAC_RQCR1_MCBCQ_4_10_OFF 16 #define MAC_RQCR1_UPQ_4_10_OFF 12 #define MAC_RQCR1_MCBCQ_4_10_MASK 0x7 #define MAC_RQCR1_UPQ_4_10_MASK 0x7 /* MAC Rx Queue Control 2 */ #define MAC_RQCR2 0xa8 #define MAC_RQCR2_PSRQ(IDX) ((IDX) * 8) #define MAC_RQCR2_PSRQ_MASK 0xFF /* MAC Rx Queue Control 3 */ #define MAC_RQCR3 0xac #define MAC_RQCR3_PSRQ(IDX) (((IDX) - 4) * 8) #define MAC_RQCR3_PSRQ_MASK 0xFF /* MAC Interrupt Status */ #define MAC_ISR 0xb0 #define MAC_ISR_GPIIS_OFF 15 #define MAC_ISR_RXSTSIS_OFF 14 #define MAC_ISR_TXSTSIS_OFF 13 #define MAC_ISR_TSIS_OFF 12 #define MAC_ISR_MMCRXIPIS_OFF 11 #define MAC_ISR_MMCTXIS_OFF 10 #define MAC_ISR_MMCRXIS_OFF 9 #define MAC_ISR_MMCIS_OFF 8 #define MAC_ISR_LPIIS_OFF 5 #define MAC_ISR_PMTIS_OFF 4 #define MAC_ISR_PHYIS_OFF 3 #define MAC_ISR_PCSANCIS_OFF 2 #define MAC_ISR_PCSLCHGIS_OFF 1 #define MAC_ISR_RGMIIIS_OFF 0 /* MAC Interrupt Enable */ #define MAC_IER 0xb4 #define MAC_IER_RXSTSIE_OFF 14 #define MAC_IER_TXSTSIE_OFF 13 #define MAC_IER_TSIE_OFF 12 #define MAC_IER_LPIIE_OFF 5 #define MAC_IER_PMTIE_OFF 4 #define MAC_IER_PHYIE_OFF 3 #define MAC_IER_PCSANCIE_OFF 2 #define MAC_IER_PCSLCHGIE_OFF 1 #define MAC_IER_RGMIIIE_OFF 0 /* MAC Receive-Transmit Status */ #define MAC_RxTx_SR 0xb8 #define MAC_RxTx_SR_RWT_OFF 8 #define MAC_RxTx_SR_EXCOL_OFF 5 #define MAC_RxTx_SR_LCOL_OFF 4 #define MAC_RxTx_SR_EXDEF_OFF 3 #define MAC_RxTx_SR_LCARR_OFF 2 #define MAC_RxTx_SR_NCARR_OFF 1 #define MAC_RxTx_SR_TJT_OFF 0 /* MAC PMT Control and Status */ #define MAC_PMT_CSR 0xc0 #define MAC_PMT_CSR_RWKFILTRST_OFF 31 #define MAC_PMT_CSR_RWKPTR_OFF 24 #define MAC_PMT_CSR_RWKPFE_4_10_OFF 10 #define MAC_PMT_CSR_GLBLUCAST_OFF 9 #define MAC_PMT_CSR_RWKPRCVD_OFF 6 #define MAC_PMT_CSR_MGKPRCVD_OFF 5 #define MAC_PMT_CSR_RWKPKTEN_OFF 2 #define MAC_PMT_CSR_MGKPKTEN_OFF 1 #define MAC_PMT_CSR_PWRDWN_OFF 0 #define MAC_PMT_CSR_RWKPTR_MASK 0x1f /* MAC Remote Wakeup Packet Filter */ #define MAC_RWK_PFR 0xc4 /* MAC LPI Control Status */ #define MAC_LPI_CSR 0xd0 #define MAC_LPI_CSR_LPITCSE_OFF 21 #define MAC_LPI_CSR_LPITE_OFF 20 #define MAC_LPI_CSR_LPITXA_OFF 19 #define MAC_LPI_CSR_PLSEN_OFF 18 #define MAC_LPI_CSR_PLS_OFF 17 #define MAC_LPI_CSR_LPIEN_OFF 16 #define MAC_LPI_CSR_RLPIST_OFF 9 #define MAC_LPI_CSR_TLPIST_OFF 8 #define MAC_LPI_CSR_RLPIEX_OFF 3 #define MAC_LPI_CSR_RLPIEN_OFF 2 #define MAC_LPI_CSR_TLPIEX_OFF 1 #define MAC_LPI_CSR_TLPIEN_OFF 0 /* MAC LPI Timers Control */ #define MAC_LPI_TCR 0xd4 #define MAC_LPI_TCR_LST_OFF 16 #define MAC_LPI_TCR_TWT_OFF 0 #define MAC_LPI_TCR_LST_MASK 0x3FF #define MAC_LPI_TCR_TWT_MASK 0xFFFF /* MAC AN Control */ #define MAC_ANCR 0xe0 #define MAC_ANCR_SGMRAL_OFF 18 #define MAC_ANCR_LR_OFF 17 #define MAC_ANCR_ECD_OFF 16 #define MAC_ANCR_ELE_OFF 14 #define MAC_ANCR_ANE_OFF 12 #define MAC_ANCR_RAN_OFF 9 /* MAC AN Status */ #define MAC_ANSR 0xe4 #define MAC_ANSR_ES_OFF 8 #define MAC_ANSR_ANC_OFF 5 #define MAC_ANSR_ANA_OFF 3 #define MAC_ANSR_LS_OFF 2 /* MAC AN Advertisement */ #define MAC_AADR 0xe8 #define MAC_AADR_NP_OFF 15 #define MAC_AADR_RFE_OFF 12 #define MAC_AADR_PSE_OFF 7 #define MAC_AADR_HD_OFF 6 #define MAC_AADR_FD_OFF 5 #define MAC_AADR_RFE_MASK 0x3 #define MAC_AADR_PSE_MASK 0x3 /* MAC AN Link Partner Ability */ #define MAC_ALPAR 0xec #define MAC_ALPAR_NP_OFF 15 #define MAC_ALPAR_ACK_OFF 14 #define MAC_ALPAR_RFE_OFF 12 #define MAC_ALPAR_PSE_OFF 7 #define MAC_ALPAR_HD_OFF 6 #define MAC_ALPAR_FD_OFF 5 #define MAC_ALPAR_RFE_MASK 0x3 #define MAC_ALPAR_PSE_MASK 0x3 /* MAC AN Expansion */ #define MAC_AER 0xf0 #define MAC_AER_NPA_OFF 2 #define MAC_AER_NPR_OFF 1 /* MAC TBI Extended Status */ #define MAC_TBI_ESR 0xf4 #define MAC_TBI_ESR_GFD_OFF 15 #define MAC_TBI_ESR_GHD_OFF 14 /* MAC PHYIF Control Status */ #define MAC_PHY_CSR 0xf8 #define MAC_PHY_CSR_FALSCARDET_OFF 21 #define MAC_PHY_CSR_JABTO_OFF 20 #define MAC_PHY_CSR_LNKSTS_OFF 19 #define MAC_PHY_CSR_LNKSPEED_OFF 17 #define MAC_PHY_CSR_LNKMOD_OFF 16 #define MAC_PHY_CSR_SMIDRXS_OFF 4 #define MAC_PHY_CSR_SFTERR_OFF 2 #define MAC_PHY_CSR_LUD_OFF 1 #define MAC_PHY_CSR_TC_OFF 0 #define MAC_PHY_CSR_LNKSPEED_MASK 0x3 /* MAC Version */ #define MAC_VR 0x110 #define MAC_VR_USERVER_OFF 8 #define MAC_VR_SNPSVER_OFF 0 #define MAC_VR_USERVER_MASK 0xFF #define MAC_VR_SNPSVER_MASK 0xFF /* MAC Debug */ #define MAC_DR 0x114 #define MAC_DR_TFCSTS_OFF 17 #define MAC_DR_TPESTS_OFF 16 #define MAC_DR_RFCFCSTS_OFF 1 #define MAC_DR_RPESTS_OFF 0 #define MAC_DR_TFCSTS_MASK 0x3 #define MAC_DR_RFCFCSTS_MASK 0x3 /* MAC Hardware Feature 0 */ #define MAC_HF0R 0x11c #define MAC_HF0R_ACTPHYSEL_OFF 28 #define MAC_HF0R_SAVLANINS_OFF 27 #define MAC_HF0R_TSSTSSEL_OFF 25 #define MAC_HF0R_MACADR64SEL_OFF 24 #define MAC_HF0R_MACADR32SEL_OFF 23 #define MAC_HF0R_ADDMACADRSEL_OFF 18 #define MAC_HF0R_RXCOESEL_OFF 16 #define MAC_HF0R_TXCOESEL_OFF 14 #define MAC_HF0R_EEESEL_OFF 13 #define MAC_HF0R_TSSEL_OFF 12 #define MAC_HF0R_ARPOFFSEL_OFF 9 #define MAC_HF0R_MMCSEL_OFF 8 #define MAC_HF0R_MGKSEL_OFF 7 #define MAC_HF0R_RWKSEL_OFF 6 #define MAC_HF0R_SMASEL_OFF 5 #define MAC_HF0R_VLHASH_OFF 4 #define MAC_HF0R_PCSSEL_OFF 3 #define MAC_HF0R_HDSEL_OFF 2 #define MAC_HF0R_GMIISEL_OFF 1 #define MAC_HF0R_MIISEL_OFF 0 #define MAC_HF0R_ACTPHYSEL_MASK 0x7 #define MAC_HF0R_TSSTSSEL_MASK 0x3 #define MAC_HF0R_ADDMACADRSEL_MASK 0x1F /* MAC Hardware Feature 1 */ #define MAC_HF1R 0x120 #define MAC_HF1R_L3L4FNUM_OFF 27 #define MAC_HF1R_HASHTBLSZ_OFF 24 #define MAC_HF1R_LPMODEEN_OFF 23 // Note: This is not included in the Synopsys Data Spec #define MAC_HF1R_AVSEL_OFF 20 #define MAC_HF1R_DBGMEMA_OFF 19 #define MAC_HF1R_TSOEN_OFF 18 #define MAC_HF1R_SPHEN_OFF 17 #define MAC_HF1R_DCBEN_OFF 16 #define MAC_HF1R_ADDR64_4_10_OFF 14 #define MAC_HF1R_ADVTHWORD_OFF 13 #define MAC_HF1R_PTOEN_4_10_OFF 12 #define MAC_HF1R_OSTEN_4_10_OFF 11 #define MAC_HF1R_TXFIFOSIZE_OFF 6 #define MAC_HF1R_RXFIFOSIZE_OFF 0 #define MAC_HF1R_L3L4FNUM_MASK 0xF #define MAC_HF1R_HASHTBLSZ_MASK 0x3 #define MAC_HF1R_TXFIFOSIZE_MASK 0x1F #define MAC_HF1R_RXFIFOSIZE_MASK 0x1F /* MAC Hardware Feature 2 */ #define MAC_HF2R 0x124 #define MAC_HF2R_AUXSNAPNUM_OFF 28 #define MAC_HF2R_PPSOUTNUM_OFF 24 #define MAC_HF2R_TXCHCNT_OFF 18 #define MAC_HF2R_RXCHCNT_OFF 12 #define MAC_HF2R_TXQCNT_OFF 6 #define MAC_HF2R_RXQCNT_OFF 0 #define MAC_HF2R_AUXSNAPNUM_MASK 0x7 #define MAC_HF2R_PPSOUTNUM_MASK 0x7 #define MAC_HF2R_TXCHCNT_MASK 0xF #define MAC_HF2R_RXCHCNT_MASK 0xF #define MAC_HF2R_TXQCNT_MASK 0xF #define MAC_HF2R_RXQCNT_MASK 0xF /* MAC MDIO Address */ #define MAC_MDIO_AR 0x200 #define MAC_MDIO_AR_PA_OFF 21 #define MAC_MDIO_AR_GMIIR_OFF 16 #define MAC_MDIO_AR_CR_OFF 8 #define MAC_MDIO_AR_SKAP_OFF 4 #define MAC_MDIO_AR_GOC_OFF 2 #define MAC_MDIO_AR_C45E_OFF 1 #define MAC_MDIO_AR_GB_OFF 0 #define MAC_MDIO_AR_PA_MASK 0x1F #define MAC_MDIO_AR_GMIIR_MASK 0x1F #define MAC_MDIO_AR_CR_MASK 0xF #define MAC_MDIO_AR_GOC_MASK 0x3 #define MAC_MDIO_AR_PSE_4_10_OFF 27 #define MAC_MDIO_AR_BTB_4_10_OFF 26 #define MAC_MDIO_AR_NTC_4_10_OFF 12 #define MAC_MDIO_AR_NTC_4_10_MASK 0x7 /* MAC MDIO Data */ #define MAC_MDIO_DR 0x204 #define MAC_MDIO_DR_RA_OFF 16 #define MAC_MDIO_DR_GD_OFF 0 #define MAC_MDIO_DR_RA_MASK 0xFFFF #define MAC_MDIO_DR_GD_MASK 0xFFFF /* MAC GPIO Control */ #define MAC_GPIO_CR 0x208 #define MAC_GPIO_CR_GPIT_OFF 16 #define MAC_GPIO_CR_GPIE_OFF 0 #define MAC_GPIO_CR_GPIT_MASK 0xFFFF #define MAC_GPIO_CR_GPIE_MASK 0xF /* MAC GPIO Status */ #define MAC_GPIO_SR 0x20c #define MAC_GPIO_SR_GPO_OFF 16 #define MAC_GPIO_SR_GPIS_OFF 0 #define MAC_GPIO_SR_GPO_MASK 0xFFFF #define MAC_GPIO_SR_GPIS_MASK 0xFFFF /* MAC Address High */ #define MAC_MAHR(IDX) (0x300 + ((IDX) * 0x8)) #define MAC_MAHR_AE_OFF 31 #define MAC_MAHR_SA_OFF 30 #define MAC_MAHR_MBC_OFF 24 #define MAC_MAHR_DCS_OFF 16 #define MAC_MAHR_ADDRHI_OFF 0 #define MAC_MAHR_MBC_MASK 0x3F #define MAC_MAHR_DCS_MASK 0x7 #define MAC_MAHR_ADDRHI_MASK 0xFFFF /* MAC Address Low */ #define MAC_MALR(IDX) (0x304 + ((IDX) * 0x8)) /* MAC ARPA */ #define MAC_ARPA_4_00 0xae0 #define MAC_ARPA_4_10 0x210 /* MAC L3 Address Registers */ #define MAC_L3AxRy(ADDR,REG) (0x910 + ((REG) * 0x30) + ((ADDR) * 0x4)) /* MAC L4 Address registers */ #define MAC_L4A(IDX) (0x904 + ((IDX) * 0x30)) #define MAC_L4A_L4DP_OFF 16 #define MAC_L4A_L4SP_OFF 0 #define MAC_L4A_L4SP_MASK 0xFFFF #define MAC_L4A_L4DP_MASK 0xFFFF /* MAC L3/L4 Control registers */ #define MAC_L3L4CR(IDX) (0x900 + ((IDX) * 0x30)) #define MAC_L3L4CR_DMCHEN_OFF 28 #define MAC_L3L4CR_DMCHN_OFF 24 #define MAC_L3L4CR_L4DPIM_OFF 21 #define MAC_L3L4CR_L4DPM_OFF 20 #define MAC_L3L4CR_L4SPIM_OFF 19 #define MAC_L3L4CR_L4SPM_OFF 18 #define MAC_L3L4CR_L4PEN_OFF 16 #define MAC_L3L4CR_L3HDBM_OFF 11 #define MAC_L3L4CR_L3HSBM_OFF 6 #define MAC_L3L4CR_L3DAIM_OFF 5 #define MAC_L3L4CR_L3DAM_OFF 4 #define MAC_L3L4CR_L3SAIM_OFF 3 #define MAC_L3L4CR_L3SAM_OFF 2 #define MAC_L3L4CR_L3PEN_OFF 0 #define MAC_L3L4CR_DMCHN_MASK 0x7 #define MAC_L3L4CR_L3HDBM_MASK 0x1F #define MAC_L3L4CR_L3HSBM_MASK 0x1F /* MAC Timestamp Control */ #define MAC_TCR 0xb00 #define MAC_TCR_AV8021ASMEN_OFF 28 #define MAC_TCR_TXTSSTSM_OFF 24 #define MAC_TCR_ESTI_OFF 20 #define MAC_TCR_TSENMACADDR_OFF 18 #define MAC_TCR_SNAPTYPSEL_OFF 16 #define MAC_TCR_TSMSTRENA_OFF 15 #define MAC_TCR_TSEVNTENA_OFF 14 #define MAC_TCR_TSIPV4ENA_OFF 13 #define MAC_TCR_TSIPV6ENA_OFF 12 #define MAC_TCR_TSIPENA_OFF 11 #define MAC_TCR_TSVER2ENA_OFF 10 #define MAC_TCR_TSCTRLSSR_OFF 9 #define MAC_TCR_TSENALL_OFF 8 #define MAC_TCR_TSADDREG_OFF 5 #define MAC_TCR_TSTRIG_OFF 4 #define MAC_TCR_TSUPDT_OFF 3 #define MAC_TCR_TSINIT_OFF 2 #define MAC_TCR_TSCFUPDT_OFF 1 #define MAC_TCR_TSENA_OFF 0 #define MAC_TCR_SNAPTYPSEL_MASK 0x3 /* MAC Sub-Second Increment */ #define MAC_SSIR 0xb04 #define MAC_SSIR_SSINC_OFF 16 #define MAC_SSIR_SNSINC_OFF 8 #define MAC_SSIR_SSINC_MASK 0xFF #define MAC_SSIR_SNSINC_MASK 0xFF /* MAC System Time-Seconds */ #define MAC_STSR 0xb08 /* MAC System Time-Nanoseconds */ #define MAC_STNR 0xb0c #define MAC_STNR_TSSS_OFF 0 #define MAC_STNR_TSSS_MASK 0x7FFFFFFF /* MAC System Time-Seconds Update */ #define MAC_STSUR 0xb10 /* MAC System Time-Nanoseconds Update */ #define MAC_STNUR 0xb14 #define MAC_STNUR_ADDSUB_OFF 31 #define MAC_STNUR_TSSS_OFF 0 #define MAC_STNUR_TSSS_MASK 0x7FFFFFFF /* MAC Timestamp Addend */ #define MAC_TAR 0xb18 /* MAC System Time - Higher Word Seconds */ #define MAC_STHWR 0xb1c #define MAC_STHWR_TSHWR_OFF 0 #define MAC_STHWR_TSHWR_MASK 0xFFFF /* MAC Timestamp Status */ #define MAC_TSR 0xb20 #define MAC_TSR_ATSNS_OFF 25 #define MAC_TSR_ATSNS_MASK 0x1F #define MAC_TSR_ATSSTM_OFF 24 #define MAC_TSR_ATSSTN_OFF 16 #define MAC_TSR_ATSSTN_MASK 0xF #define MAC_TSR_TXTSSIS_OFF 15 #define MAC_TSR_TSTRGTERR3_OFF 9 #define MAC_TSR_TSTARGT3_OFF 8 #define MAC_TSR_TSTRGTERR2_OFF 7 #define MAC_TSR_TSTARGT2_OFF 6 #define MAC_TSR_TSTRGTERR1_OFF 5 #define MAC_TSR_TSTARGT1_OFF 4 #define MAC_TSR_TSTRGTERR0_OFF 3 #define MAC_TSR_AUXTSTRIG_OFF 2 #define MAC_TSR_TSTARGT0_OFF 1 #define MAC_TSR_TSSOVF_OFF 0 /* MAC Tx Timestamp Status Nanoseconds */ #define MAC_TxTSNR 0xb30 #define MAC_TxTSNR_TXTSSTSMIS_OFF 31 #define MAC_TxTSNR_TXTSSTSLO_OFF 0 #define MAC_TxTSNR_TXTSSTSLO_MASK 0x7FFFFFFF /* MAC Tx Timestamp Status Seconds */ #define MAC_TxTSSR 0xb34 /* MAC Auxiliary Timestamp Control */ #define MAC_ATCR 0xb40 #define MAC_ATCR_ATSEN3_OFF 7 #define MAC_ATCR_ATSEN2_OFF 6 #define MAC_ATCR_ATSEN1_OFF 5 #define MAC_ATCR_ATSEN0_OFF 4 #define MAC_ATCR_ATSFC_OFF 0 /* MAC Auxiliary Timestamp Nanoseconds */ #define MAC_ATNR 0xb48 #define MAC_ATNR_AUXTSLO_OFF 0 #define MAC_ATNR_AUXTSLO_MASK 0x7FFFFFFF /* MAC Auxiliary Timestamp Seconds */ #define MAC_ATSR 0xb4c /* MAC Timestamp Ingress Asymmetry Correction */ #define MAC_TIACR 0xb50 /* MAC Timestamp Egress Asymmetry Correction */ #define MAC_TEACR 0xb54 /* MAC Timestamp Timestamp Ingress Correction */ #define MAC_TICR 0xb58 /* MAC Timestamp Timestamp Egress Correction */ #define MAC_TECR 0xb5c /* MAC PPS Control */ #define MAC_PPSC 0xb70 #define MAC_PPSC_TRGTMODSEL3_OFF 29 #define MAC_PPSC_PPSCMD3_OFF 24 #define MAC_PPSC_TRGTMODSEL2_OFF 21 #define MAC_PPSC_PPSCMD2_OFF 16 #define MAC_PPSC_TRGTMODSEL1_OFF 13 #define MAC_PPSC_PPSCMD1_OFF 8 #define MAC_PPSC_TRGTMODSEL0_OFF 5 #define MAC_PPSC_PPSEN0_OFF 4 #define MAC_PPSC_PPSCTRL0_OFF 0 #define MAC_PPSC_PPSCMD0_OFF 0 #define MAC_PPSC_TRGTMODSEL3_MASK 0x3 #define MAC_PPSC_PPSCMD3_MASK 0x7 #define MAC_PPSC_TRGTMODSEL2_MASK 0x3 #define MAC_PPSC_PPSCMD2_MASK 0x7 #define MAC_PPSC_TRGTMODSEL1_MASK 0x3 #define MAC_PPSC_PPSCMD1_MASK 0x7 #define MAC_PPSC_TRGTMODSEL0_MASK 0x3 #define MAC_PPSC_PPSCTRL0_MASK 0x7 #define MAC_PPSC_PPSCMD0_MASK 0x7 /* MAC PPS Target Time Seconds */ #define MAC_PPS_TTS(IDX) (0xb80 + ((IDX) * 0x10)) /* MAC PPS Target Time Nanoseconds */ #define MAC_PPS_TTNS(IDX) (0xb84 + ((IDX) * 0x10)) #define MAC_PPS_TTNS_TRGTBUSY0_OFF 31 #define MAC_PPS_TTNS_TTSL0_OFF 0 #define MAC_PPS_TTNS_TTSL0_MASK 0x7FFFFFFF /* MAC PPS Interval */ #define MAC_PPS_INT(IDX) (0xb88 + ((IDX) * 0x10)) /* MAC PPS Width */ #define MAC_PPS_WIDTH(IDX) (0xb8c + ((IDX) * 0x10)) /* MAC PTO Control */ #define MAC_PTO_CR 0xbc0 #define MAC_PTO_CR_DN_OFF 8 #define MAC_PTO_CR_DRRDIS_OFF 6 #define MAC_PTO_CR_APDREQTRIG_OFF 5 #define MAC_PTO_CR_ASYNCTRIG_OFF 4 #define MAC_PTO_CR_APDREQEN_OFF 2 #define MAC_PTO_CR_ASYNCEN_OFF 1 #define MAC_PTO_CR_PTOEN_OFF 0 #define MAC_PTO_CR_DN_MASK 0xFF /* MAC Source Port Identity */ #define MAC_SPI0 0xbc4 #define MAC_SPI1 0xbc8 #define MAC_SPI2 0xbcc #define MAC_SPI2_MASK 0xFFFF /* MAC Log Message Interval */ #define MAC_LMIR 0xbd0 #define MAC_LMIR_LMPDRI_OFF 24 #define MAC_LMIR_DRSYNCR_OFF 8 #define MAC_LMIR_LSI_OFF 0 #define MAC_LMIR_LMPDRI_MASK 0xFF #define MAC_LMIR_DRSYNCR_MASK 0x7 #define MAC_LMIR_LSI_MASK 0Xff /******************************* MMC REGISTERS *******************************/ /* MMC Control */ #define MMC_CR 0x700 #define MMC_CR_UCDBC_OFF 8 #define MMC_CR_CNTPRSTLVL_OFF 5 #define MMC_CR_CNTPRST_OFF 4 #define MMC_CR_CNTFREEZ_OFF 3 #define MMC_CR_RSTONRD_OFF 2 #define MMC_CR_CNTSTOPRO_OFF 1 #define MMC_CR_CNTRST_OFF 0 /* MMC Rx Interrupt */ #define MMC_RX_IR 0x704 #define MMC_RX_IR_RXCTRLPIS_OFF 25 #define MMC_RX_IR_RXRCVERRPIS_OFF 24 #define MMC_RX_IR_RXWDOGPIS_OFF 23 #define MMC_RX_IR_RXVLANGBPIS_OFF 22 #define MMC_RX_IR_RXFOVPIS_OFF 21 #define MMC_RX_IR_RXPAUSPIS_OFF 20 #define MMC_RX_IR_RXORANGEPIS_OFF 19 #define MMC_RX_IR_RXLENERPIS_OFF 18 #define MMC_RX_IR_RXUCGPIS_OFF 17 #define MMC_RX_IR_RX1024TMAXOCTGBPIS_OFF 16 #define MMC_RX_IR_RX512T1023OCTGBPIS_OFF 15 #define MMC_RX_IR_RX256T511OCTGBPIS_OFF 14 #define MMC_RX_IR_RX128T255OCTGBPIS_OFF 13 #define MMC_RX_IR_RX65T127OCTGBPIS_OFF 12 #define MMC_RX_IR_RX64OCTGBPIS_OFF 11 #define MMC_RX_IR_RXOSIZEGPIS_OFF 10 #define MMC_RX_IR_RXUSIZEGPIS_OFF 9 #define MMC_RX_IR_RXJABERPIS_OFF 8 #define MMC_RX_IR_RXRUNTPIS_OFF 7 #define MMC_RX_IR_RXALGNERPIS_OFF 6 #define MMC_RX_IR_RXCRCERPIS_OFF 5 #define MMC_RX_IR_RXMCGPIS_OFF 4 #define MMC_RX_IR_RXBCGTIS_OFF 3 #define MMC_RX_IR_RXGOCTIS_OFF 2 #define MMC_RX_IR_RXGBOCTIS_OFF 1 #define MMC_RX_IR_RXGBPKTIS_OFF 0 /* MMC Tx Interrupt */ #define MMC_TX_IR 0x708 #define MMC_TX_IR_TXOSIZEGPIS_OFF 25 #define MMC_TX_IR_TXVLANGPIS_OFF 24 #define MMC_TX_IR_TXPAUSPIS_OFF 23 #define MMC_TX_IR_TXEXDEFPIS_OFF 22 #define MMC_TX_IR_TXGPKTIS_OFF 21 #define MMC_TX_IR_TXGOCTIS_OFF 20 #define MMC_TX_IR_TXCARERPIS_OFF 19 #define MMC_TX_IR_TXEXCOLPIS_OFF 18 #define MMC_TX_IR_TXLATCOLPIS_OFF 17 #define MMC_TX_IR_TXDEFPIS_OFF 16 #define MMC_TX_IR_TXMCOLGPIS_OFF 15 #define MMC_TX_IR_TXSCOLGPIS_OFF 14 #define MMC_TX_IR_TXUFLOWERFIS_OFF 13 #define MMC_TX_IR_TXBCGBPIS_OFF 12 #define MMC_TX_IR_TXMCGBPIS_OFF 11 #define MMC_TX_IR_TXUCGBPIS_OFF 10 #define MMC_TX_IR_TX1024TMAXOCTGBFIS_OFF 9 #define MMC_TX_IR_TX512T1023OCTGBPIS_OFF 8 #define MMC_TX_IR_TX256T511OCTGBPIS_OFF 7 #define MMC_TX_IR_TX128T255OCTGBPIS_OFF 6 #define MMC_TX_IR_TX65T127OCTGBPIS_OFF 5 #define MMC_TX_IR_TX64OCTGBPIS_OFF 4 #define MMC_TX_IR_TXMCGPIS_OFF 3 #define MMC_TX_IR_TXBCGPIS_OFF 2 #define MMC_TX_IR_TXGBPKTIS_OFF 1 #define MMC_TX_IR_TXGBOCTIS_OFF 0 /* MMC Rx Interrupt Mask */ #define MMC_RX_IMR 0x70c #define MMC_RX_IMR_RXCTRLPIM_OFF 25 #define MMC_RX_IMR_RXRCVERRPIM_OFF 24 #define MMC_RX_IMR_RXWDOGPIM_OFF 23 #define MMC_RX_IMR_RXVLANGBPIM_OFF 22 #define MMC_RX_IMR_RXFOVPIM_OFF 21 #define MMC_RX_IMR_RXPAUSPIM_OFF 20 #define MMC_RX_IMR_RXORANGEPIM_OFF 19 #define MMC_RX_IMR_RXLENERPIM_OFF 18 #define MMC_RX_IMR_RXUCGPIM_OFF 17 #define MMC_RX_IMR_RX1024TMAXOCTGBPIM_OFF 16 #define MMC_RX_IMR_RX512T1023OCTGBPIM_OFF 15 #define MMC_RX_IMR_RX256T511OCTGBPIM_OFF 14 #define MMC_RX_IMR_RX128T255OCTGBPIM_OFF 13 #define MMC_RX_IMR_RX65T127OCTGBPIM_OFF 12 #define MMC_RX_IMR_RX64OCTGBPIM_OFF 11 #define MMC_RX_IMR_RXOSIZEGPIM_OFF 10 #define MMC_RX_IMR_RXUSIZEGPIM_OFF 9 #define MMC_RX_IMR_RXJABERPIM_OFF 8 #define MMC_RX_IMR_RXRUNTPIM_OFF 7 #define MMC_RX_IMR_RXALGNERPIM_OFF 6 #define MMC_RX_IMR_RXCRCERPIM_OFF 5 #define MMC_RX_IMR_RXMCGPIM_OFF 4 #define MMC_RX_IMR_RXBCGTIM_OFF 3 #define MMC_RX_IMR_RXGOCTIM_OFF 2 #define MMC_RX_IMR_RXGBOCTIM_OFF 1 #define MMC_RX_IMR_RXGBPKTIM_OFF 0 /* MMC Tx Interrupt Mask */ #define MMC_TX_IMR 0x710 #define MMC_TX_IMR_TXOSIZEGPIM_OFF 25 #define MMC_TX_IMR_TXVLANGPIM_OFF 24 #define MMC_TX_IMR_TXPAUSPIM_OFF 23 #define MMC_TX_IMR_TXEXDEFPIM_OFF 22 #define MMC_TX_IMR_TXGPKTIM_OFF 21 #define MMC_TX_IMR_TXGOCTIM_OFF 20 #define MMC_TX_IMR_TXCARERPIM_OFF 19 #define MMC_TX_IMR_TXEXCOLPIM_OFF 18 #define MMC_TX_IMR_TXLATCOLPIM_OFF 17 #define MMC_TX_IMR_TXDEFPIM_OFF 16 #define MMC_TX_IMR_TXMCOLGPIM_OFF 15 #define MMC_TX_IMR_TXSCOLGPIM_OFF 14 #define MMC_TX_IMR_TXUFLOWERFIM_OFF 13 #define MMC_TX_IMR_TXBCGBPIM_OFF 12 #define MMC_TX_IMR_TXMCGBPIM_OFF 11 #define MMC_TX_IMR_TXUCGBPIM_OFF 10 #define MMC_TX_IMR_TX1024TMAXOCTGBFIM_OFF 9 #define MMC_TX_IMR_TX512T1023OCTGBPIM_OFF 8 #define MMC_TX_IMR_TX256T511OCTGBPIM_OFF 7 #define MMC_TX_IMR_TX128T255OCTGBPIM_OFF 6 #define MMC_TX_IMR_TX65T127OCTGBPIM_OFF 5 #define MMC_TX_IMR_TX64OCTGBPIM_OFF 4 #define MMC_TX_IMR_TXMCGPIM_OFF 3 #define MMC_TX_IMR_TXBCGPIM_OFF 2 #define MMC_TX_IMR_TXGBPKTIM_OFF 1 #define MMC_TX_IMR_TXGBOCTIM_OFF 0 /* MMC Tx Octet Count Good Bad */ #define MMC_TX_OCTETS 0x714 /* MMC Tx Packet Count Good Bad */ #define MMC_TX_PKTS 0x718 /* MMC Tx Broadcast Packets Good */ #define MMC_TX_BROADCAST_GOOD 0x71c /* MMC Tx Multicast Packets Good */ #define MMC_TX_MULTICAST_GOOD 0x720 /* MMC Tx 64Octets Packets Good Bad */ #define MMC_TX_64_OCTETS 0x724 /* MMC Tx 65To127Octets Packets Good Bad */ #define MMC_TX_65TO127_OCTETS 0x728 /* MMC Tx 128To255Octets Packets Good Bad */ #define MMC_TX_128TO255_OCTETS 0x72c /* MMC Tx 256To511Octets Packets Good Bad */ #define MMC_TX_256TO511_OCTETS 0x730 /* MMC Tx 512To1023Octets Packets Good Bad */ #define MMC_TX_512TO1023_OCTETS 0x734 /* MMC Tx 1024ToMaxOctets Packets Good Bad */ #define MMC_TX_1024TOMAX_OCTETS 0x738 /* MMC Tx Unicast Packets Good Bad */ #define MMC_TX_UNICAST 0x73c /* MMC Tx Multicast Packets Good Bad */ #define MMC_TX_MULTICAST 0x740 /* MMC Tx Broadcast Packets Good Bad */ #define MMC_TX_BROADCAST 0x744 /* MMC Tx Underflow Error Packets */ #define MMC_TX_UNDERFLOW_ERROR 0x748 /* MMC Tx Single Collision Good Packets */ #define MMC_TX_SINGLE_COLLISION 0x74c /* MMC Tx Multiple Collision Good Packets */ #define MMC_TX_MULTI_COLLISION 0x750 /* MMC Tx Deferred Packets */ #define MMC_TX_DEFERRED 0x754 /* MMC Tx Late Collision Packets */ #define MMC_TX_LATE_COLLISION 0x758 /* MMC Tx Excessive Collision Packets */ #define MMC_TX_EXCESS_COLLISION 0x75c /* MMC Tx Carrier Error Packets */ #define MMC_TX_CARRIER_ERROR 0x760 /* MMC Tx Octet Count Good */ #define MMC_TX_OCTETS_GOOD 0x764 /* MMC Tx Packet Count Good */ #define MMC_TX_PKTS_GOOD 0x768 /* MMC Tx Excessive Deferral Error */ #define MMC_TX_EXCESS_DEFERRAL_ERR 0x76c /* MMC Tx Pause Packets */ #define MMC_TX_PAUSE_PKTS 0x770 /* MMC Tx VLAN Packets Good */ #define MMC_TX_VLAN_PKTS 0x774 /* MMC Tx OSize Packets Good */ #define MMC_TX_OVERSIZE_PKTS 0x778 /* MMC Rx Packets Count Good Bad */ #define MMC_RX_PKTS 0x780 /* MMC Rx Octet Count Good Bad */ #define MMC_RX_OCTETS 0x784 /* MMC Rx Octet Count Good */ #define MMC_RX_OCTET_GOOD 0x788 /* MMC Rx Broadcast Packets Good */ #define MMC_RX_BROADCAST_GOOD 0x78c /* MMC Rx Multicast Packets Good */ #define MMC_RX_MULTICAST_GOOD 0x790 /* MMC Rx CRC Error Packets */ #define MMC_RX_CRC_ERROR 0x794 /* MMC Rx Alignment Error Packets */ #define MMC_RX_ALIGN_ERROR 0x798 /* MMC Rx Runt Error Packets */ #define MMC_RX_RUNT_ERROR 0x79c /* MMC Rx Jabber Error Packets */ #define MMC_RX_JABBER_ERROR 0x7a0 /* MMC Rx Undersize Packets Good */ #define MMC_RX_UNDERSIZE_PKTS 0x7a4 /* MMC Rx Oversize Packets Good */ #define MMC_RX_OVERSIZE_PKTS 0x7a8 /* MMC Rx 64Octets Packets Good Bad */ #define MMC_RX_64_OCTETS 0x7ac /* MMC Rx 65To127Octets Packets Good Bad */ #define MMC_RX_65TO127_OCTETS 0x7b0 /* MMC Rx 128To255Octets Packets Good Bad */ #define MMC_RX_128TO255_OCTETS 0x7b4 /* MMC Rx 256To511Octets Packets Good Bad */ #define MMC_RX_256TO511_OCTETS 0x7b8 /* MMC Rx 512To1023Octets Packets Good Bad */ #define MMC_RX_512TO1023_OCTETS 0x7bc /* MMC Rx 1024ToMaxOctets Packets Good Bad */ #define MMC_RX_1024TOMAX_OCTETS 0x7c0 /* MMC Rx Unicast Packets Good */ #define MMC_RX_UNICAST_GOOD 0x7c4 /* MMC Rx Length Error Packets */ #define MMC_RX_LENGTH_ERROR 0x7c8 /* MMC Rx Out Of Range Type Packets */ #define MMC_RX_OUT_RANGE_TYPE 0x7cc /* MMC Rx Pause Packets */ #define MMC_RX_PAUSE_PKTS 0x7d0 /* MMC Rx FIFO Overflow Packets */ #define MMC_RX_FIFO_OVERFLOW 0x7d4 /* MMC Rx VLAN Packets Good Bad */ #define MMC_RX_VLAN_PKTS 0x7d8 /* MMC Rx Watchdog Error Packets */ #define MMC_RX_WATCHDOG_ERROR 0x7dc /* MMC Rx Receive Error Packets */ #define MMC_RX_RECEIVE_ERROR 0x7e0 /* MMC Rx Control Packets Good */ #define MMC_RX_CONTROL_PKTS 0x7e4 /* MMC IPC Rx Interrupt Mask */ #define MMC_IPC_RX_IMR 0x800 #define MMC_IPC_RX_IMR_RXICMPEROIM_OFF 29 #define MMC_IPC_RX_IMR_RXICMPGOIM_OFF 28 #define MMC_IPC_RX_IMR_RXTCPEROIM_OFF 27 #define MMC_IPC_RX_IMR_RXTCPGOIM_OFF 26 #define MMC_IPC_RX_IMR_RXUDPEROIM_OFF 25 #define MMC_IPC_RX_IMR_RXUDPGOIM_OFF 24 #define MMC_IPC_RX_IMR_RXIPV6NOPAYOIM_OFF 23 #define MMC_IPC_RX_IMR_RXIPV6HEROIM_OFF 22 #define MMC_IPC_RX_IMR_RXIPV6GOIM_OFF 21 #define MMC_IPC_RX_IMR_RXIPV4UDSBLOIM_OFF 20 #define MMC_IPC_RX_IMR_RXIPV4FRAGOIM_OFF 19 #define MMC_IPC_RX_IMR_RXIPV4NOPAYOIM_OFF 18 #define MMC_IPC_RX_IMR_RXIPV4HEROIM_OFF 17 #define MMC_IPC_RX_IMR_RXIPV4GOIM_OFF 16 #define MMC_IPC_RX_IMR_RXICMPERPIM_OFF 13 #define MMC_IPC_RX_IMR_RXICMPGPIM_OFF 12 #define MMC_IPC_RX_IMR_RXTCPERPIM_OFF 11 #define MMC_IPC_RX_IMR_RXTCPGPIM_OFF 10 #define MMC_IPC_RX_IMR_RXUDPERPIM_OFF 9 #define MMC_IPC_RX_IMR_RXUDPGPIM_OFF 8 #define MMC_IPC_RX_IMR_RXIPV6NOPAYPIM_OFF 7 #define MMC_IPC_RX_IMR_RXIPV6HERPIM_OFF 6 #define MMC_IPC_RX_IMR_RXIPV6GPIM_OFF 5 #define MMC_IPC_RX_IMR_RXIPV4UDSBLPIM_OFF 4 #define MMC_IPC_RX_IMR_RXIPV4FRAGPIM_OFF 3 #define MMC_IPC_RX_IMR_RXIPV4NOPAYPIM_OFF 2 #define MMC_IPC_RX_IMR_RXIPV4HERPIM_OFF 1 #define MMC_IPC_RX_IMR_RXIPV4GPIM_OFF 0 /* MMC IPC Rx Interrupt */ #define MMC_IPC_RX_IR 0x808 #define MMC_IPC_RX_IR_RXICMPEROIS_OFF 29 #define MMC_IPC_RX_IR_RXICMPGOIS_OFF 28 #define MMC_IPC_RX_IR_RXTCPEROIS_OFF 27 #define MMC_IPC_RX_IR_RXTCPGOIS_OFF 26 #define MMC_IPC_RX_IR_RXUDPEROIS_OFF 25 #define MMC_IPC_RX_IR_RXUDPGOIS_OFF 24 #define MMC_IPC_RX_IR_RXIPV6NOPAYOIS_OFF 23 #define MMC_IPC_RX_IR_RXIPV6HEROIS_OFF 22 #define MMC_IPC_RX_IR_RXIPV6GOIS_OFF 21 #define MMC_IPC_RX_IR_RXIPV4UDSBLOIS_OFF 20 #define MMC_IPC_RX_IR_RXIPV4FRAGOIS_OFF 19 #define MMC_IPC_RX_IR_RXIPV4NOPAYOIS_OFF 18 #define MMC_IPC_RX_IR_RXIPV4HEROIS_OFF 17 #define MMC_IPC_RX_IR_RXIPV4GOIS_OFF 16 #define MMC_IPC_RX_IR_RXICMPERPIS_OFF 13 #define MMC_IPC_RX_IR_RXICMPGPIS_OFF 12 #define MMC_IPC_RX_IR_RXTCPERPIS_OFF 11 #define MMC_IPC_RX_IR_RXTCPGPIS_OFF 10 #define MMC_IPC_RX_IR_RXUDPERPIS_OFF 9 #define MMC_IPC_RX_IR_RXUDPGPIS_OFF 8 #define MMC_IPC_RX_IR_RXIPV6NOPAYPIS_OFF 7 #define MMC_IPC_RX_IR_RXIPV6HERPIS_OFF 6 #define MMC_IPC_RX_IR_RXIPV6GPIS_OFF 5 #define MMC_IPC_RX_IR_RXIPV4UDSBLPIS_OFF 4 #define MMC_IPC_RX_IR_RXIPV4FRAGPIS_OFF 3 #define MMC_IPC_RX_IR_RXIPV4NOPAYPIS_OFF 2 #define MMC_IPC_RX_IR_RXIPV4HERPIS_OFF 1 #define MMC_IPC_RX_IR_RXIPV4GPIS_OFF 0 /* MMC RxIPv4 Good Packets */ #define MMC_RX_IPV4_GOOD_PKTS 0x810 /* MMC RxIPv4 Header Error Packets */ #define MMC_RX_IPV4_HEADER_ERROR_PKTS 0x814 /* MMC RxIPv4 No Payload Packets */ #define MMC_RX_IPV4_NO_PAYLOAD_PKTS 0x818 /* MMC RxIPv4 Fragmented Packets */ #define MMC_RX_IPV4_FRAGMENTED_PKTS 0x81c /* MMC RxIPv4 UDP Checksum Disabled Packets */ #define MMC_RX_IPV4_UDP_CSUM_DIS_PKTS 0x820 /* MMC RxIPv6 Good Packets */ #define MMC_RX_IPV6_GOOD_PKTS 0x824 /* MMC RxIPv6 Header Error Packets */ #define MMC_RX_IPV6_HEADER_ERROR_PKTS 0x828 /* MMC RxIPv6 No Payload Packets */ #define MMC_RX_IPV6_NO_PAYLOAD_PKTS 0x82c /* MMC RxUDP Good Packets */ #define MMC_RX_UDP_GOOD_PKTS 0x830 /* MMC RxUDP Error Packets */ #define MMC_RX_UDP_ERROR_PKTS 0x834 /* MMC RxTCP Good Packets */ #define MMC_RX_TCP_GOOD_PKTS 0x838 /* MMC RxTCP Error Packets */ #define MMC_RX_TCP_ERROR_PKTS 0x83c /* MMC RxICMP Good Packets */ #define MMC_RX_ICMP_GOOD_PKTS 0x840 /* MMC RxICMP Error Packets */ #define MMC_RX_ICMP_ERROR_PKTS 0x844 /* MMC RxIPv4 Good Octets */ #define MMC_RX_IPV4_GOOD_OCTETS 0x850 /* MMC RxIPv4 Header Error Octets */ #define MMC_RX_IPV4_ERROR_OCTETS 0x854 /* MMC RxIPv4 No Payload Octets */ #define MMC_RX_IPV4_NO_PAYLOAD_OCTETS 0x858 /* MMC RxIPv4 Fragmented Octets */ #define MMC_RX_IPV4_FRAGMENTED_OCTETS 0x85c /* MMC RxIPv4 UDP Checksum Disable Octets */ #define MMC_RX_IPV4_UDP_CSUM_DIS_OCTETS 0x860 /* MMC RxIPv6 Good Octets */ #define MMC_RX_IPV6_GOOD_OCTETS 0x864 /* MMC RxIPv6 Header Error Octets */ #define MMC_RX_IPV6_HEADER_ERROR_OCTETS 0x868 /* MMC RxIPv6 No Payload Octets */ #define MMC_RX_IPV6_NO_PAYLOAD_OCTETS 0x86c /* MMC RxUDP Good Octets */ #define MMC_RX_UDP_GOOD_OCTETS 0x870 /* MMC RxUDP Error Octets */ #define MMC_RX_UDP_ERROR_OCTETS 0x874 /* MMC RxTCP Good Octets */ #define MMC_RX_TCP_GOOD_OCTETS 0x878 /* MMC RxTCP Error Octets */ #define MMC_RX_TCP_ERROR_OCTETS 0x87c /* MMC RxICMP Good Octets */ #define MMC_RX_ICMP_GOOD_OCTETS 0x880 /* MMC RxICMP Error Octets */ #define MMC_RX_ICMP_ERROR_OCTETS 0x884 /******************************* MTL REGISTERS *******************************/ /* MTL Operation Mode */ #define MTL_OMR 0xc00 #define MTL_OMR_CNTCLR_OFF 9 #define MTL_OMR_CNTPRST_OFF 8 #define MTL_OMR_SCHALG_OFF 5 #define MTL_OMR_RAA_OFF 2 #define MTL_OMR_DTXSTS_OFF 1 #define MTL_OMR_SCHALG_MASK 0x3 #define MTL_OMR_RAA_MASK 0x7 /* MTL FIFO Debug Access Control and Status */ #define MTL_FDACS 0xc08 #define MTL_FDACS_STSIE_OFF 15 #define MTL_FDACS_PKTIE_OFF 14 #define MTL_FDACS_FIFOSEL_OFF 12 #define MTL_FDACS_FIFOWREN_OFF 11 #define MTL_FDACS_FIFORDEN_OFF 10 #define MTL_FDACS_RSTSEL_OFF 9 #define MTL_FDACS_RSTALL_OFF 8 #define MTL_FDACS_PKTSTATE_OFF 5 #define MTL_FDACS_BYTEEN_OFF 2 #define MTL_FDACS_DBGMOD_OFF 1 #define MTL_FDACS_FDBGEN_OFF 0 #define MTL_FDACS_FIFOSEL_MASK 0x3 #define MTL_FDACS_PKTSTATE_MASK 0x3 #define MTL_FDACS_BYTEEN_MASK 0x3 /* MTL Debug Status */ #define MTL_DSR 0xc0c #define MTL_DSR_LOCR_OFF 16 #define MTL_DSR_STSI_OFF 9 #define MTL_DSR_PKTI_OFF 8 #define MTL_DSR_BYTE_EN_OFF 3 #define MTL_DSR_PKTSTATE_OFF 1 #define MTL_DSR_FIFOBUSY_OFF 0 #define MTL_DSR_LOCR_MASK 0xFFFF #define MTL_DSR_BYTE_EN_MASK 0x3 #define MTL_DSR_PKTSTATE_MASK 0x3 /* MTL FIFO Debug Data */ #define MTL_FDD 0xc10 /* MTL Interrupt Status */ #define MTL_ISR 0xc20 #define MTL_ISR_QIS_DBGIS 17 #define MTL_ISR_QIS_MACIS 16 #define MTL_ISR_QIS(IDX) (IDX) #define MTL_ISR_QIS_MASK 0x1 /* MTL Rx Queue DMA Channel Map 0 */ #define MTL_RQDCM0 0xc30 #define MTL_RQDCM0_RQ2DMA(IDX) ((IDX) * 8) #define MTL_RQDCM0_RQDADMACH(IDX) (((IDX) * 8) + 4) #define MTL_RQDCM0_RQ2DMA_MASK 0x7 #define MTL_RQDCM0_RQDADMACH_MASK 0x1 /* MTL Rx Queue DMA Channel Map 1 */ #define MTL_RQDCM1 0xc34 #define MTL_RQDCM1_RQ2DMA(IDX) (((IDX) - 4) * 8) #define MTL_RQDCM1_RQDADMACH(IDX) ((((IDX) - 4) * 8) + 4) #define MTL_RQDCM1_RQ2DMA_MASK 0x7 #define MTL_RQDCM1_RQDADMACH_MASK 0x1 /* MTL Tx Queue Operation Mode */ #define MTL_TXQ_OMR(IDX) (0xd00 + ((IDX) * 0x40)) #define MTL_TXQ_OMR_TQS_OFF 16 #define MTL_TXQ_OMR_TTC_OFF 4 #define MTL_TXQ_OMR_TXQEN_OFF 2 #define MTL_TXQ_OMR_TSF_OFF 1 #define MTL_TXQ_OMR_FTQ_OFF 0 #define MTL_TXQ_OMR_TQS_MASK 0x1FF #define MTL_TXQ_OMR_TTC_MASK 0x7 #define MTL_TXQ_OMR_TXQEN_MASK 0x3 /* MTL Tx Queue Underflow Counter */ #define MTL_TXQ_UCR(IDX) (0xd04 + ((IDX) * 0x40)) #define MTL_TXQ_UCR_UFCNTOVF_OFF 11 #define MTL_TXQ_UCR_UFPKTCNT_OFF 0 #define MTL_TXQ_UCR_UFPKTCNT_MASK 0x7FF /* MTL Tx Queue Transmit Debug */ #define MTL_TXQ_TDR(IDX) (0xd08 + ((IDX) * 0x40)) #define MTL_TXQ_TDR_STXSTSF_OFF 20 #define MTL_TXQ_TDR_PTXQ_OFF 16 #define MTL_TXQ_TDR_TXSTSFSTS_OFF 5 #define MTL_TXQ_TDR_TXQSTS_OFF 4 #define MTL_TXQ_TDR_TWCSTS_OFF 3 #define MTL_TXQ_TDR_TRCSTS_OFF 1 #define MTL_TXQ_TDR_TXQPAUSED_OFF 0 #define MTL_TXQ_TDR_STXSTSF_MASK 0x7 #define MTL_TXQ_TDR_PTXQ_MASK 0x7 #define MTL_TXQ_TDR_TRCSTS_MASK 0x3 /* MTL Tx Queue ETS Control */ #define MTL_TXQ_ECR(IDX) (0xd10 + ((IDX) * 0x40)) #define MTL_TXQ_ECR_ABPSSIE_OFF 24 #define MTL_TXQ_ECR_SLC_OFF 4 #define MTL_TXQ_ECR_CC_OFF 3 #define MTL_TXQ_ECR_AVALG_OFF 2 #define MTL_TXQ_ECR_SLC_MASk 0x7 /* MTL Tx Queue ETS Status */ #define MTL_TXQ_ESR(IDX) (0xd14 + ((IDX) * 0x40)) #define MTL_TXQ_ESR_ABS_OFF 0 #define MTL_TXQ_ESR_ABS_MASK 0xFFFFFF /* MTL Tx Queue Quantum Weight */ #define MTL_TXQ_QW(IDX) (0xd18 + ((IDX) * 0x40)) #define MTL_TXQ_QW_ISCQW_OFF 0 #define MTL_TXQ_QW_ISCQW_MASK 0x1FFFFF /* MTL Tx Queue SendSlope Credit */ #define MTL_TXQ_SSCR(IDX) (0xd1c + ((IDX) * 0x40)) #define MTL_TXQ_SSCR_SSC_OFF 0 #define MTL_TXQ_SSCR_SSC_MASK 0x3FFF /* MTL Tx Queue HiCredit */ #define MTL_TXQ_HCR(IDX) (0xd20 + ((IDX) * 0x40)) #define MTL_TXQ_HCR_HC_OFF 0 #define MTL_TXQ_HCR_HC_MASK 0x1FFFFFFF /* MTL Tx Queue LowCredit */ #define MTL_TXQ_LCR(IDX) (0xd24 + ((IDX) * 0x40)) #define MTL_TXQ_LCR_LC_OFF 0 #define MTL_TXQ_LCR_LC_MASK 0x1FFFFFFF /* MTL Rx Queue Operation Mode */ #define MTL_RXQ_OMR(IDX) (0xd30 + ((IDX) * 0x40)) #define MTL_RXQ_OMR_RQS_OFF 20 #define MTL_RXQ_OMR_EHFC_OFF 7 #define MTL_RXQ_OMR_DIS_TCP_EF_OFF 6 #define MTL_RXQ_OMR_RSF_OFF 5 #define MTL_RXQ_OMR_FEP_OFF 4 #define MTL_RXQ_OMR_FUP_OFF 3 #define MTL_RXQ_OMR_RTC_OFF 0 #define MTL_RXQ_OMR_RQS_MASK 0x3FF #define MTL_RXQ_OMR_RTC_MASK 0x3 #define MTL_RXQ_OMR_RFD_4_00_OFF 13 #define MTL_RXQ_OMR_RFA_4_00_OFF 8 #define MTL_RXQ_OMR_RFD_4_00_MASK 0x7 #define MTL_RXQ_OMR_RFA_4_00_MASK 0x7 #define MTL_RXQ_OMR_RFD_4_10_OFF 14 #define MTL_RXQ_OMR_RFA_4_10_OFF 8 #define MTL_RXQ_OMR_RFD_4_10_MASK 0x3F #define MTL_RXQ_OMR_RFA_4_10_MASK 0x3F /* MTL Rx Queue Missed Packet Overflow Counter */ #define MTL_RXQ_POC(IDX) (0xd34 + ((IDX) * 0x40)) #define MTL_RXQ_POC_MISCNTOVF_OFF 27 #define MTL_RXQ_POC_MISPKTCNT_OFF 16 #define MTL_RXQ_POC_OVFCNTOVF_OFF 11 #define MTL_RXQ_POC_OVFPKTCNT_OFF 0 #define MTL_RXQ_POC_MISPKTCNT_MASK 0x7FF #define MTL_RXQ_POC_OVFPKTCNT_MASK 0x7FF /* MTL Rx Queue Control */ #define MTL_RXQ_DR(IDX) (0xd38 + ((IDX) * 0x40)) #define MTL_RXQ_DR_PRXQ_OFF 16 #define MTL_RXQ_DR_RXQSTS_OFF 4 #define MTL_RXQ_DR_RRCSTS_OFF 1 #define MTL_RXQ_DR_RWCSTS_OFF 0 #define MTL_RXQ_DR_PRXQ_MASK 0x3FFF #define MTL_RXQ_DR_RXQSTS_MASK 0x3 #define MTL_RXQ_DR_RRCSTS_MASK 0x3 /* MTL Rx Queue Control */ #define MTL_RXQ_CR(IDX) (0xd3c + ((IDX) * 0x40)) #define MTL_RXQ_CR_PKT_ARBIT_OFF 3 #define MTL_RXQ_CR_WEGT_OFF 0 #define MTL_RXQ_CR_WEGT_MASK 0x7 /******************************* DMA REGISTERS *******************************/ /* DMA Bus Mode */ #define DMA_BMR 0x1000 #define DMA_BMR_INTM_4_10_OFF 16 #define DMA_BMR_PR_OFF 12 #define DMA_BMR_TXPR_OFF 11 #define DMA_BMR_TAA_OFF 2 #define DMA_BMR_DA_OFF 1 #define DMA_BMR_SWR_OFF 0 #define DMA_BMR_INTM_4_10_MASK 0x3 #define DMA_BMR_PR_MASK 0x7 #define DMA_BMR_TAA_MASK 0x7 /* DMA System Bus Mode */ #define DMA_SBMR 0x1004 #define DMA_SBMR_EN_LPI_OFF 31 #define DMA_SBMR_LPI_XIT_PKT_OFF 30 #define DMA_SBMR_WR_OSR_LMT_OFF 24 #define DMA_SBMR_RD_OSR_LMT_OFF 16 #define DMA_SBMR_RB_OFF 15 #define DMA_SBMR_MB_OFF 14 #define DMA_SBMR_ONEKBBE_OFF 13 #define DMA_SBMR_AAL_OFF 12 #define DMA_SBMR_EAME_4_10_OFF 11 #define DMA_SBMR_BLEN256_OFF 7 #define DMA_SBMR_BLEN128_OFF 6 #define DMA_SBMR_BLEN64_OFF 5 #define DMA_SBMR_BLEN32_OFF 4 #define DMA_SBMR_BLEN16_OFF 3 #define DMA_SBMR_BLEN8_OFF 2 #define DMA_SBMR_BLEN4_OFF 1 #define DMA_SBMR_FB_OFF 0 #define DMA_SBMR_WR_OSR_LMT_MASK 0x3 #define DMA_SBMR_RD_OSR_LMT_MASK 0x3 /* DMA Interrupt Status */ #define DMA_ISR 0x1008 #define DMA_ISR_MACIS_OFF 17 #define DMA_ISR_MTLIS_OFF 16 #define DMA_ISR_DC7IS_OFF 7 #define DMA_ISR_DC6IS_OFF 6 #define DMA_ISR_DC5IS_OFF 5 #define DMA_ISR_DC4IS_OFF 4 #define DMA_ISR_DC3IS_OFF 3 #define DMA_ISR_DC2IS_OFF 2 #define DMA_ISR_DC1IS_OFF 1 #define DMA_ISR_DC0IS_OFF 0 /* DMA Debug Status 0 */ #define DMA_DSR0 0x100c #define DMA_DSR0_TPS2_OFF 28 #define DMA_DSR0_RPS2_OFF 24 #define DMA_DSR0_TPS1_OFF 20 #define DMA_DSR0_RPS1_OFF 16 #define DMA_DSR0_TPS0_OFF 12 #define DMA_DSR0_RPS0_OFF 8 #define DMA_DSR0_AXRHSTS_OFF 1 #define DMA_DSR0_AXWHSTS_OFF 0 #define DMA_DSR0_TPS2_MASK 0xF #define DMA_DSR0_RPS2_MASK 0xF #define DMA_DSR0_TPS1_MASK 0xF #define DMA_DSR0_RPS1_MASK 0xF #define DMA_DSR0_TPS0_MASK 0xF #define DMA_DSR0_RPS0_MASK 0xF /* DMA Debug Status 1 */ #define DMA_DSR1 0x1010 #define DMA_DSR1_TPS6_OFF 28 #define DMA_DSR1_RPS6_OFF 24 #define DMA_DSR1_TPS5_OFF 20 #define DMA_DSR1_RPS5_OFF 16 #define DMA_DSR1_TPS4_OFF 12 #define DMA_DSR1_RPS4_OFF 8 #define DMA_DSR1_TPS3_OFF 4 #define DMA_DSR1_RPS3_OFF 0 #define DMA_DSR1_TPS6_MASK 0xF #define DMA_DSR1_RPS6_MASK 0xF #define DMA_DSR1_TPS5_MASK 0xF #define DMA_DSR1_RPS5_MASK 0xF #define DMA_DSR1_TPS4_MASK 0xF #define DMA_DSR1_RPS4_MASK 0xF #define DMA_DSR1_TPS3_MASK 0xF #define DMA_DSR1_RPS3_MASK 0xF /* DMA Debug Status 2 */ #define DMA_DSR2 0x1014 #define DMA_DSR2_TPS7_OFF 4 #define DMA_DSR2_RPS7_OFF 0 #define DMA_DSR2_TPS7_MASK 0xF #define DMA_DSR2_RPS7_MASK 0xF /* DMA Control */ #define DMA_CR(IDX) (0x1100 + ((IDX) * 0x80)) #define DMA_CR_SPH_OFF 24 #define DMA_CR_DSL_OFF 18 #define DMA_CR_PBLx8_OFF 16 #define DMA_CR_MSS_OFF 0 #define DMA_CR_DSL_MASK 0x7 #define DMA_CR_MSS_MASK 0x3FFF /* DMA Tx Control */ #define DMA_TCR(IDX) (0x1104 + ((IDX) * 0x80)) #define DMA_TCR_PBL_OFF 16 #define DMA_TCR_IPBL_OFF 15 #define DMA_TCR_TSE_OFF 12 #define DMA_TCR_OSP_OFF 4 #define DMA_TCR_TCW_OFF 1 #define DMA_TCR_ST_OFF 0 #define DMA_TCR_PBL_MASK 0x3F #define DMA_TCR_TCW_MASK 0x7 #define DMA_TCR_TQOS_4_10_OFF 24 #define DMA_TCR_TQOS_4_10_MASK 0xF /* DMA Rx Control */ #define DMA_RCR(IDX) (0x1108 + ((IDX) * 0x80)) #define DMA_RCR_PBL_OFF 16 #define DMA_RCR_RBSZ_OFF 1 #define DMA_RCR_SR_OFF 0 #define DMA_RCR_PBL_MASK 0x3F #define DMA_RCR_RBSZ_MASK 0x3FFF #define DMA_RCR_MAMS_4_00_OFF 27 #define DMA_RCR_RPF_4_10_OFF 31 #define DMA_RCR_RQOS_4_10_OFF 24 #define DMA_RCR_RQOS_4_10_MASK 0xF /* DMA Tx Descriptor List Address */ #define DMA_TDLAR(IDX) (0x1114 + ((IDX) * 0x80)) /* DMA Rx Descriptor List Address */ #define DMA_RDLAR(IDX) (0x111c + ((IDX) * 0x80)) /* DMA Tx Descriptor Tail Pointer */ #define DMA_TDTPR(IDX) (0x1120 + ((IDX) * 0x80)) /* DMA Rx Descriptor Tail Pointer */ #define DMA_RDTPR(IDX) (0x1128 + ((IDX) * 0x80)) /* DMA Tx Descriptor Ring Length */ #define DMA_TDRLR(IDX) (0x112c + ((IDX) * 0x80)) #define DMA_TDRLR_TDRL_OFF 0 #define DMA_TDRLR_TDRL_MASK 0x3FF /* DMA Rx Descriptor Ring Length */ #define DMA_RDRLR(IDX) (0x1130 + ((IDX) * 0x80)) #define DMA_RDRLR_RDRL_OFF 0 #define DMA_RDRLR_RDRL_MASK 0x3FF /* DMA Interrupt Enable */ #define DMA_IER(IDX) (0x1134 + ((IDX) * 0x80)) #define DMA_IER_NIE_4_00_OFF 16 #define DMA_IER_AIE_4_00_OFF 15 #define DMA_IER_NIE_4_10_OFF 15 #define DMA_IER_AIE_4_10_OFF 14 #define DMA_IER_CDEE_OFF 13 #define DMA_IER_FBEE_OFF 12 #define DMA_IER_ERIE_OFF 11 #define DMA_IER_ETIE_OFF 10 #define DMA_IER_RWTE_OFF 9 #define DMA_IER_RSE_OFF 8 #define DMA_IER_RBUE_OFF 7 #define DMA_IER_RIE_OFF 6 #define DMA_IER_TBUE_OFF 2 #define DMA_IER_TSE_OFF 1 #define DMA_IER_TIE_OFF 0 /* DMA Receive Interrupt Watchdog Timer */ #define DMA_RIWTR(IDX) (0x1138 + ((IDX) * 0x80)) #define DMA_RIWTR_RWT_OFF 0 #define DMA_RIWTR_RWT_MASK 0xFF /* DMA Slot Function Control and Status */ #define DMA_SFCSR(IDX) (0x113c + ((IDX) * 0x80)) #define DMA_SFCSR_RSN_OFF 16 #define DMA_SFCSR_ASC_OFF 1 #define DMA_SFCSR_ESC_OFF 0 #define DMA_SFCSR_RSN_MASK 0xF /* DMA Current Application Transmit Descriptor */ #define DMA_CATDR(IDX) (0x1144 + ((IDX) * 0x80)) /* DMA Current Application Receive Descriptor */ #define DMA_CARDR(IDX) (0x114c + ((IDX) * 0x80)) /* DMA Current Application Transmit Buffer Address */ #define DMA_CATBAR(IDX) (0x1154 + ((IDX) * 0x80)) /* DMA Current Application Receive Buffer Address */ #define DMA_CARBAR(IDX) (0x115c + ((IDX) * 0x80)) /* DMA Status */ #define DMA_SR(IDX) (0x1160 + ((IDX) * 0x80)) #define DMA_SR_REB_OFF 19 #define DMA_SR_TEB_OFF 16 #define DMA_SR_NIS_OFF 15 #define DMA_SR_AIS_OFF 14 #define DMA_SR_CDE_OFF 13 #define DMA_SR_FBE_OFF 12 #define DMA_SR_ERI_OFF 11 #define DMA_SR_ETI_OFF 10 #define DMA_SR_RWT_OFF 9 #define DMA_SR_RPS_OFF 8 #define DMA_SR_RBU_OFF 7 #define DMA_SR_RI_OFF 6 #define DMA_SR_TBU_OFF 2 #define DMA_SR_TPS_OFF 1 #define DMA_SR_TI_OFF 0 #define DMA_SR_REB_MASK 0x7 #define DMA_SR_TEB_MASK 0x7 /* DMA AXI Control Register */ #define DMA_AXI4_CR(IDX) (0x1164 + ((IDX) * 0x80)) #define DMA_AXI4_CR_ARQOS_OFF 16 #define DMA_AXI4_CR_AWQOS_OFF 0 #define DMA_AXI4_CR_ARQOS_MASK 0xF #define DMA_AXI4_CR_AWQOS_MASK 0xF /***************************** GBE TOP REGISTERS *****************************/ #define GBE_REG_RD(REG) \ be32_to_cpu(ioread32((void *)(reg_base + (REG)))) #define GBE_REG_WR(REG, VAL) \ iowrite32(cpu_to_be32(VAL),(void *)(reg_base + (REG))) #define GBE_REG_RD_FIELD(REG,FIELD) \ ((GBE_REG_RD(REG) >> (FIELD ## _OFF)) & (FIELD ## _MASK)) #define GBE_REG_WR_FIELD(REG,FIELD,VAL) \ do { \ uint32_t value = GBE_REG_RD(REG) & (~((FIELD ## _MASK) << (FIELD ## _OFF))); \ value |= (VAL & (FIELD ## _MASK)) << (FIELD ## _OFF); \ GBE_REG_WR(REG, value); \ } while(0) #define GBE_REG_RD_BIT(REG,FIELD) \ ((GBE_REG_RD(REG) >> (FIELD ## _OFF)) & ONE_BIT_MASK) #define GBE_REG_WR_BIT(REG,FIELD,VAL) \ do { \ uint32_t value = GBE_REG_RD(REG) & (~(ONE_BIT_MASK << (FIELD ## _OFF))); \ value |= (VAL & ONE_BIT_MASK) << (FIELD ## _OFF); \ GBE_REG_WR(REG, value); \ } while(0) #define GBE_GEN_REGISTER_OFF 0x0 #define GBE_GEN_ATOM_IC_OFF 0x2800 /* GMAC5 Interrupt Controller Registers */ #define GBE_ATOM_HIE (GBE_GEN_ATOM_IC_OFF + 0x0) // Hardware Interrupt #define GBE_ATOM_SWI (GBE_GEN_ATOM_IC_OFF + 0x4) // Software Interrupt #define GBE_ATOM_ELS (GBE_GEN_ATOM_IC_OFF + 0x8) // Edge/Level Register #define GBE_ATOM_IMV (GBE_GEN_ATOM_IC_OFF + 0xC) // Interrupt Mask Register #define GBE_ATOM_IRS (GBE_GEN_ATOM_IC_OFF + 0x10) // Interrupt Status Register #define GBE_ATOM_IMS (GBE_GEN_ATOM_IC_OFF + 0x14) // Interrupt Masked Status Register #define GBE_ATOM_INTC_OFF 7 /* GMAC5 Configuration Register */ #define GBE_GCR5 (GBE_GEN_REGISTER_OFF + 0x14) #define GBE_GCR5_ENABLE_OFF 31 // 1 - Enabled; 0 - Disabled #define GBE_GCR5_PHY_CFG_OFF 29 // 00 - GMII; 01 - RGMII; 10 - SGMII #define GBE_GCR5_ENDIANESS_OFF 28 // 0 - LE; 1 - BE #define GBE_GCR5_PHY_SPEED_OFF 25 // 10M, 100M, ... (values defined below) #define GBE_GCR5_RESET_OFF 24 // 0 - Reset; 1 - Out of reset #define GBE_GCR5_PHY_CFG_MASK 0x3 #define GBE_GCR5_PHY_SPEED_MASK 0x7 #define GBE_GCR5_PHY_SPEED_10M 2 #define GBE_GCR5_PHY_SPEED_100M 3 #define GBE_GCR5_PHY_SPEED_1G 0 #define GBE_GCR5_PHY_SPEED_2_5G 1 #define GBE_GCR5_PHY_SPEED_5G 4 /* GBE Mux Configuration Register */ #define GBE_GMCR (GBE_GEN_REGISTER_OFF + 0x18) #define GBE_GMCR_GMAC25_OFF 30 #define GBE_GMCR_GMAC25_MASK 0x3 #define GMCR_GMAC5_TO_GMAC4 0 #define GMCR_GMAC5_TO_PHY 2 /* GBE VBUS Endian Conversion Register */ #define GBE_GVBECR (GBE_GEN_REGISTER_OFF + 0x1C) #define GBE_GVBECR_GMAC5_OFF 18 /* GBE Status Registers (for debug) */ #define GBE_GSRH (GBE_GEN_REGISTER_OFF + 0x20) // Status Register High #define GBE_GSRL (GBE_GEN_REGISTER_OFF + 0x24) // Status Register Low /* Boot Config Register */ #define BCFG2SSX_GBEM_CFG 0x34 #define BCFG2SSX_GBEM_SNOOPED_OFF 15 /************************** DESCRIPTORS DEFINITIONS ***************************/ /** * Rx Normal Descriptor (Read Format) */ /* Header or Buffer 1 Address Pointer */ #define NORMAL_RF_RDES0_BUF1AP_OFF 0 #define NORMAL_RF_RDES0_BUF1AP_MASK 0xFFFFFFFF /* Buffer 2 Address Pointer */ #define NORMAL_RF_RDES2_BUF2AP_OFF 0 #define NORMAL_RF_RDES2_BUF2AP_MASK 0xFFFFFFFF /* Own Bit */ #define NORMAL_RF_RDES3_OWN_OFF 31 /* Interrupt Enable on Completion */ #define NORMAL_RF_RDES3_INTE_OFF 30 /* Buffer 2 Address Valid */ #define NORMAL_RF_RDES3_BUF2V_OFF 25 /* Buffer 1 Address Valid */ #define NORMAL_RF_RDES3_BUF1V_OFF 24 /** * Rx Normal Descriptor (Write-Back Format) */ /* VLAN Tag */ #define NORMAL_WB_RDES0_VT_OFF 0 #define NORMAL_WB_RDES0_VT_MASK 0xFFFF /* IP Type 1 Checksum, OAM Sub-Type Code, or MAC Control Packet opcode */ #define NORMAL_WB_RDES1_IPT1C_OFF 16 #define NORMAL_WB_RDES1_IPT1C_MASK 0xFFFF /* Timestamp Dropped */ #define NORMAL_WB_RDES1_TD_OFF 15 /* Timestamp Available */ #define NORMAL_WB_RDES1_TSA_OFF 14 /* PTP Version */ #define NORMAL_WB_RDES1_PV_OFF 13 /* PTP Packet Type */ #define NORMAL_WB_RDES1_PFT_OFF 12 /* PTP Message Type */ #define NORMAL_WB_RDES1_PMT_OFF 8 #define NORMAL_WB_RDES1_PMT_MASK 0xF /* IPC Checksum Error */ #define NORMAL_WB_RDES1_IPCE_OFF 7 /* IP Checksum Bypassed */ #define NORMAL_WB_RDES1_IPCB_OFF 6 /* IPv6 Header Present */ #define NORMAL_WB_RDES1_IPV6_OFF 5 /* IPv4 Header Present */ #define NORMAL_WB_RDES1_IPV4_OFF 4 /* IP Header Error */ #define NORMAL_WB_RDES1_IPHE_OFF 3 /* Payload Type */ #define NORMAL_WB_RDES1_PT_OFF 0 #define NORMAL_WB_RDES1_PT_MASK 0x7 /* Layer 3 and Layer 4 Filter Number Matched */ #define NORMAL_WB_RDES2_L3L4FM_OFF 29 #define NORMAL_WB_RDES2_L3L4FM_MASK 0x7 /* L4 Filter Match */ #define NORMAL_WB_RDES2_L4FM_OFF 28 /* L3 Filter Match */ #define NORMAL_WB_RDES2_L3FM_OFF 27 /* MAC Address Match or Hash Value */ #define NORMAL_WB_RDES2_MADRM_OFF 19 #define NORMAL_WB_RDES2_MADRM_MASK 0xFF /* Hash Filter Status */ #define NORMAL_WB_RDES2_HF_OFF 18 /* Destination Address Filter Fail */ #define NORMAL_WB_RDES2_DAF_OFF 17 /* SA Address Filter Fail */ #define NORMAL_WB_RDES2_SAF_OFF 16 /* VLAN Filter Status */ #define NORMAL_WB_RDES2_VF_OFF 15 /* L3/L4 Header Length */ #define NORMAL_WB_RDES2_HL_OFF 0 #define NORMAL_WB_RDES2_HL_MASK 0x3FF /* Own Bit */ #define NORMAL_WB_RDES3_OWN_OFF 31 /* Receive Context Descriptor */ #define NORMAL_WB_RDES3_TYPE_OFF 30 /* First Descriptor */ #define NORMAL_WB_RDES3_FD_OFF 29 /* Last Descriptor */ #define NORMAL_WB_RDES3_LD_OFF 28 /* Receive Status RDES2 Valid */ #define NORMAL_WB_RDES3_RS2V_OFF 27 /* Receive Status RDES1 Valid */ #define NORMAL_WB_RDES3_RS1V_OFF 26 /* Receive Status RDES0 Valid */ #define NORMAL_WB_RDES3_RS0V_OFF 25 /* CRC Error */ #define NORMAL_WB_RDES3_CE_OFF 24 /* Giant Packet */ #define NORMAL_WB_RDES3_GP_OFF 23 /* Receive Watchdog Timeout */ #define NORMAL_WB_RDES3_RWT_OFF 22 /* Overflow Error */ #define NORMAL_WB_RDES3_OE_OFF 21 /* Receive Error */ #define NORMAL_WB_RDES3_RE_OFF 20 /* Dribble Bit Error */ #define NORMAL_WB_RDES3_DE_OFF 19 /* Length/Type Field */ #define NORMAL_WB_RDES3_LT_OFF 16 #define NORMAL_WB_RDES3_LT_MASK 0x7 /* Error Summary */ #define NORMAL_WB_RDES3_ES_OFF 15 /* Packet Length */ #define NORMAL_WB_RDES3_PL_OFF 0 #define NORMAL_WB_RDES3_PL_MASK 0x7FFF /** * Rx Context Descriptor */ /* Receive Packet Timestamp Low */ #define CONTEXT_RDES0_RTSL_OFF 0 #define CONTEXT_RDES0_RTSL_MASK 0xFFFFFFFF /* Receive Packet Timestamp High */ #define CONTEXT_RDES1_RTSH_OFF 0 #define CONTEXT_RDES1_RTSH_MASK 0xFFFFFFFF /* Own Bit */ #define CONTEXT_RDES3_OWN_OFF 31 /* Context Type Indicator */ #define CONTEXT_RDES3_TYPE_OFF 30 /** * Tx Normal Descriptor (Read Format) */ /* Buffer 1 Address Pointer or Header Address Pointer */ #define NORMAL_RF_TDES0_BUF1AP_OFF 0 #define NORMAL_RF_TDES0_BUF1AP_MASK 0xFFFFFFFF /* Buffer 2 Address Pointer */ #define NORMAL_RF_TDES1_BUF2AP_OFF 0 #define NORMAL_RF_TDES1_BUF2AP_MASK 0xFFFFFFFF /* Interrupt On Completion */ #define NORMAL_RF_TDES2_IOC_OFF 31 /* Transmit Timestamp Enable */ #define NORMAL_RF_TDES2_TTSE_OFF 30 /* Buffer 2 Length */ #define NORMAL_RF_TDES2_B2L_OFF 16 #define NORMAL_RF_TDES2_B2L_MASK 0x3FFF /* VLAN Tag Insertion or Replacement */ #define NORMAL_RF_TDES2_VTIR_OFF 14 #define NORMAL_RF_TDES2_VTIR_MASK 0x3 /* Header or Buffer 1 Length */ #define NORMAL_RF_TDES2_HL_B1L_OFF 0 #define NORMAL_RF_TDES2_HL_B1L_MASK 0x3FFF /* Own Bit */ #define NORMAL_RF_TDES3_OWN_OFF 31 /* Context Type Indicator (should be 0 for Normal descriptor) */ #define NORMAL_RF_TDES3_TYPE_OFF 30 /* First Descriptor */ #define NORMAL_RF_TDES3_FD_OFF 29 /* Last Descriptor */ #define NORMAL_RF_TDES3_LD_OFF 28 /* CRC/PAD Control */ #define NORMAL_RF_TDES3_CPC_OFF 26 #define NORMAL_RF_TDES3_CPC_MASK 0x3 /* SA Insertion Control */ #define NORMAL_RF_TDES3_SAIC_OFF 23 #define NORMAL_RF_TDES3_SAIC_MASK 0x7 /* TCP Header Length */ #define NORMAL_RF_TDES3_THL_OFF 19 #define NORMAL_RF_TDES3_THL_MASK 0xF /* Slot Number for AV (Same as THL) */ #define NORMAL_RF_TDES3_SLOTNUM NORMAL_RF_TDES3_THL /* TCP Segmentation Enable */ #define NORMAL_RF_TDES3_TSE_OFF 18 /* Checksum Insertion Control */ #define NORMAL_RF_TDES3_CIC_OFF 16 #define NORMAL_RF_TDES3_CIC_MASK 0x3 /* Packet Length */ #define NORMAL_RF_TDES3_PL_OFF 0 #define NORMAL_RF_TDES3_PL_MASK 0x7FFF /* TCP Payload Length */ #define NORMAL_RF_TDES3_TPL_OFF 0 #define NORMAL_RF_TDES3_TPL_MASK 0x3FFFF /** * Tx Normal Descriptor (Write-Back Format) */ /* Transmit Packet Timestamp Low */ #define NORMAL_WB_TDES0_TTSL_OFF 0 #define NORMAL_WB_TDES0_TTSL_MASK 0xFFFFFFFF /* Transmit Packet Timestamp High */ #define NORMAL_WB_TDES1_TTSH_OFF 0 #define NORMAL_WB_TDES1_TTSH_MASK 0xFFFFFFFF /* Own Bit */ #define NORMAL_WB_TDES3_OWN_OFF 31 /* Context Type Indicator */ #define NORMAL_WB_TDES3_TYPE_OFF 30 /* First Descriptor */ #define NORMAL_WB_TDES3_FD_OFF 29 /* Last Descriptor */ #define NORMAL_WB_TDES3_LD_OFF 28 /* Tx Timestamp Status */ #define NORMAL_WB_TDES3_TTSS_OFF 17 /* Error Summary */ #define NORMAL_WB_TDES3_ES_OFF 15 /* Jabber Timeout */ #define NORMAL_WB_TDES3_JT_OFF 14 /* Packet Flushed */ #define NORMAL_WB_TDES3_FF_OFF 13 /* Payload Checksum Error */ #define NORMAL_WB_TDES3_PCE_OFF 12 /* Loss of Carrier */ #define NORMAL_WB_TDES3_LOC_OFF 11 /* No Carrier */ #define NORMAL_WB_TDES3_NC_OFF 10 /* Late Collision */ #define NORMAL_WB_TDES3_LC_OFF 9 /* Excessive Collision */ #define NORMAL_WB_TDES3_EC_OFF 8 /* Collision Count */ #define NORMAL_WB_TDES3_CC_OFF 4 #define NORMAL_WB_TDES3_CC_MASK 0xF /* Excessive Deferral */ #define NORMAL_WB_TDES3_ED_OFF 3 /* Underflow Error */ #define NORMAL_WB_TDES3_UF_OFF 2 /* Deferred Bit */ #define NORMAL_WB_TDES3_DB_OFF 1 /* IP Header Error */ #define NORMAL_WB_TDES3_IHE_OFF 0 /** * Tx Context Descriptor */ /* Transmit Packet Timestamp Low */ #define CONTEXT_TDES0_TTSL_OFF 0 #define CONTEXT_TDES0_TTSL_MASK 0xFFFFFFFF /* Transmit Packet Timestamp High */ #define CONTEXT_TDES1_TTSH_OFF 0 #define CONTEXT_TDES1_TTSH_MASK 0xFFFFFFFF /* Inner VLAN Tag */ #define CONTEXT_TDES2_IVT_OFF 16 #define CONTEXT_TDES2_IVT_MASK 0xFFFF /* Maximum Segment Size */ #define CONTEXT_TDES2_MSS_OFF 0 #define CONTEXT_TDES2_MSS_MASK 0x1FFF /* Own Bit */ #define CONTEXT_TDES3_OWN_OFF 31 /* Context Type Indicator */ #define CONTEXT_TDES3_TYPE_OFF 30 /* One-Step Timestamp Correction Enable */ #define CONTEXT_TDES3_OSTC_OFF 27 /* One-Step Timestamp Correction Input or MSS Valid */ #define CONTEXT_TDES3_TCMSSV_OFF 26 /* Context Descriptor Error */ #define CONTEXT_TDES3_CDE_OFF 23 /* Inner VLAN Tag Insert or Replace */ #define CONTEXT_TDES3_IVTIR_OFF 18 #define CONTEXT_TDES3_IVTIR_MASK 0x3 /* Inner VLAN Tag Valid */ #define CONTEXT_TDES3_IVLTV_OFF 17 /* VLAN Tag Valid */ #define CONTEXT_TDES3_VLTV_OFF 16 /* VLAN Tag */ #define CONTEXT_TDES3_VT_OFF 0 #define CONTEXT_TDES3_VT_MASK 0xFFFF /************************** ERROR BITS DEFINITIONS ****************************/ #define TX_ERROR_HEARTBEAT_OFF 4 #define TX_ERROR_WINDOW_OFF 3 #define TX_ERROR_FIFO_OFF 2 #define TX_ERROR_CARRIER_OFF 1 #define TX_ERROR_ABORTED_OFF 0 #define RX_ERROR_MISSED_OFF 5 #define RX_ERROR_FIFO_OFF 4 #define RX_ERROR_FRAME_OFF 3 #define RX_ERROR_CRC_OFF 2 #define RX_ERROR_OVERRUN_OFF 1 #define RX_ERROR_LENGTH_OFF 0 /*************************** FEATURES DEFINITIONS *****************************/ /** * TX PACKET FEATURES */ #define TX_PKT_FEATURES_ATTR_VLAN_PKT_OFF 3 #define TX_PKT_FEATURES_ATTR_PTP_ENABLE_OFF 2 #define TX_PKT_FEATURES_ATTR_TSO_ENABLE_OFF 1 #define TX_PKT_FEATURES_ATTR_CSUM_ENABLE_OFF 0 #define TX_PKT_FEATURES_VLAN_TAG_VT_OFF 0 #define TX_PKT_FEATURES_VLAN_TAG_VT_MASK 0xFFFF #define TX_PKT_FEATURES_VLAN_TAG_SVT_OFF 16 #define TX_PKT_FEATURES_VLAN_TAG_SVT_MASK 0xFFFF #define TX_PKT_FEATURES_TCP_PKT_TYPE_OFF 1 #define TX_PKT_FEATURES_IP_PKT_TYPE_OFF 0 /** * RX PACKET FEATURES */ #define RX_PKT_FEATURES_ATTR_VLAN_PKT_OFF 1 #define RX_PKT_FEATURES_ATTR_CSUM_DONE_OFF 0 #define RX_PKT_FEATURES_VLAN_TAG_VT_OFF 0 #define RX_PKT_FEATURES_VLAN_TAG_VT_MASK 0xFFFF #define RX_PKT_FEATURES_VLAN_TAG_SVT_OFF 16 #define RX_PKT_FEATURES_VLAN_TAG_SVT_MASK 0xFFFF #endif // __DWC_ETH_QOS__REGACC__H__