/* * * avalanche_intc.h * Description: * ATOM_INTC interrupt controller header file * * GPL LICENSE SUMMARY Copyright(c) 2008-2016 Intel Corporation. This program is free software; you can redistribute it and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. The full GNU General Public License is included in this distribution in the file called LICENSE.GPL. Contact Information: Intel Corporation 2200 Mission College Blvd. Santa Clara, CA 97052 */ #ifndef _AVALANCHE_INTC_H #define _AVALANCHE_INTC_H #ifndef NUM_INTS_PER_REG #define NUM_INTS_PER_REG (32) #endif /* * Interrupt Distributor relies on the below structure for SoC related * information */ /***************************************************************************/ /* avalanche_intc ***************************************************************************/ /**************************************************************************** * Avalanche interrupt controller register base ****************************************************************************/ /* NOTE: Read "ICTRL" as 'interrupt Controller' */ struct avalanche_ictrl_pacer_regs /* Avalanche Interrupt control pacer regs*/ { volatile unsigned long icpparamr; /* ICTRL Pacer Parameter Reg */ volatile unsigned long icpdecr; /* ICTRL Pacing Decrement Reg */ volatile unsigned long icpmap; /* ICTRL Pacer map Reg */ volatile unsigned long reserved; /* unused Reg */ }; typedef struct avalanche_ictrl_pacer_regs ICTRL_PACER_REGS; struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */ { volatile unsigned long icrevr; /* ICTRL Revision Reg 0x00*/ volatile unsigned long iccntlr; /* ICTRL Control Reg 0x04*/ volatile unsigned long unused1; /* 0x08 */ volatile unsigned long ichcntlr; /* ICTRL Host control Reg 0x0C */ volatile unsigned long icglber; /* ICTRL Global Enable Reg 0x10 */ volatile unsigned long unused2[2]; /* 0x14 to 0x18*/ volatile unsigned long icglbnlr; /* ICTRL Global Nesting Level Reg 0x1C */ volatile unsigned long icsisr; /* ICTRL Status index Set Reg 0x20 */ volatile unsigned long icsicr; /* ICTRL Status index Clear Reg 0x24 */ volatile unsigned long iceisr; /* ICTRL enable index Set Reg 0x28*/ volatile unsigned long iceicr; /* ICTRL enable index Clear Reg 0x2C */ volatile unsigned long icgwer; /* ICTRL Global Wakeup Enable Reg 0x30 */ volatile unsigned long ichinteisr; /* ICTRL host interrupt enable index Set Reg 0x34 */ volatile unsigned long ichinteicr; /* ICTRL host interrupt enable index Clear Reg 0x38 */ volatile unsigned long unused4; /* 0x3c */ volatile unsigned long icpprer; /* ICTRL Pacer Prescale Reg 0x40 */ volatile unsigned long unused5[3]; /* 0x44 to 0x4C */ volatile unsigned long icvbr; /* ICTRL Vector Base Reg 0x50 */ volatile unsigned long icvszr; /* ICTRL Vector Size Reg 0x54*/ volatile unsigned long icvnullr; /* ICTRL Vector Null Reg 0x58 */ volatile unsigned long unused7[9]; /* 0x5c to 0x7c */ volatile unsigned long icgpir; /* ICTRL Global Priority Index Reg 0x80 */ volatile unsigned long icgpvr; /* ICTRL Global Priority vector Reg0x84 */ volatile unsigned long unused17[2]; /* 0x88 to 0x8c */ volatile unsigned long icgsecinter; /* ICTRL Global security Interrupt Enable Reg 0x90 */ volatile unsigned long icsecpir; /* ICTRL Secure prioritised Index Reg 0x94 */ volatile unsigned long unused19[26];/* 0x098 to 0x0FC */ ICTRL_PACER_REGS icpacer [16]; /* ICTRL pacing Regs array 0x100 */ volatile unsigned long icrstar[32]; /* ICTRL Raw status Reg 0x200 */ volatile unsigned long icestar[32]; /* ICTRL Enabled Status Reg 0x280 */ volatile unsigned long icenbsr[32]; /* ICTRL Enabler set Reg 0x300 */ volatile unsigned long icenbcr[32]; /* ICTRL Enabler Clear Reg 0x380*/ volatile unsigned long icchnlmpr[256]; /* ICTRL Channel Map Reg 0x400 */ volatile unsigned long ichmpr[64]; /* ICTRL Host Map Reg 0x800 */ volatile unsigned long ichintpir[256]; /* ICTRL Host Interrupt Priotrized Index Reg 0x900 */ volatile unsigned long icpolr[32]; /* ICTRL polarity Reg 0xD00 */ volatile unsigned long ictypr[32]; /* ICTRL type Reg 0xD80 */ volatile unsigned long icwuper[64]; /* ICTRL Wakeup Enable Reg 0xE00 */ volatile unsigned long icdbgsetr[64]; /* ICTRL Debug Set Reg 0xF00*/ volatile unsigned long icsecer[64]; /* ICTRL secure Enble Reg 0x1000 */ volatile unsigned long ichintnlr[256]; /* ICTRL Host Interrupt Nesting level Reg 0x1100 */ volatile unsigned long ichinter[8]; /* ICTRL Host Interrupt Enable Reg 0x1500 */ volatile unsigned long unused45[184]; /* 0x1520 to 0x1800 */ }; /***************************************************************************** * Status Register Read/Clear APIs. ****************************************************************************/ /* Clear Interrupt Status Register bit for irq */ int avalanche_intc_clear_status( unsigned int irq ); /* Check Interrupt Status Registerbit for irq */ int avalanche_intc_get_status( unsigned int irq ); /* enable irq index */ void avalanche_intc_enable_irq( unsigned int irq ); /* disable irq index */ void avalanche_intc_disable_irq( unsigned int irq ); /***************************************************************************** * General and Global Regsiters INIT APIs ****************************************************************************/ /* INTI controller memory map Registers */ int avalanche_intc_init(void); void avalanche_intc_cleanup(void); #endif /* _AVALANCHE_INTD_H */