/*
  pal_cppi41.h
  Description:
  see below

  Copyright (C) 2020-2022 MaxLinear, Inc.
  Copyright (C) 2008-2020 Intel Corporation

  This software is licensed under
  (a) a 3-clause BSD license; or alternatively
  (b) the GPL v2 license

  -- A. BSD-3-Clause ----------------------------
  Redistribution and use in source and binary forms, with or without modification,
  are permitted provided that the following conditions are met:
  1. Redistributions of source code must retain the above copyright notice,
     this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice,
     this list of conditions and the following disclaimer in the documentation
     and/or other materials provided with the distribution.
  3. Neither the name of the copyright holder nor the names of its contributors
     may be used to endorse or promote products derived from this software
     without specific prior written permission.

  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS
  BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
  OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  -- B. GPL-2.0 ----------------------------
  This program is free software; you can redistribute it and/or modify it
  under the terms of the GNU General Public License, version 2, as published
  by the Free Software Foundation. 

  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.

  You should have received a copy of the GNU General Public License
  along with this program; if not, see <http://www.gnu.org/licenses/>.
  ------------------------------

  SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
*/

/** \file   pal_cppi41.h
 *  \brief PAL CPPI4.1 header file
 *  This file is minimized CPPI4.1 PAL header file to be
 *  included the datapipe driver which use CPPI4.1.
 *  This file is compliant to the PSP Framework 1.0 definitions
 *  and prototypes.
 *
 *  \author Idan Emergi
 */

#ifndef __PAL_CPPI4_H__
#define __PAL_CPPI4_H__

#ifndef CONFIG_ARM_AVALANCHE_SOC
#include <linux/avalanche/puma7/puma7_defs.h>
#include <linux/avalanche/generic/avalanche_pdsp_api.h>
#include <asm/cacheflush.h>
#endif

#include <linux/avalanche/generic/_tistdtypes.h>
#include <linux/avalanche/generic/pal.h>
#include <linux/avalanche/generic/cslr_cppi41.h>
#include <asm/io.h>

/**
 * General PAL defines
 */
#define PAL_CPPI_TESTS 0

typedef enum cppi_domain
{
    CPPI41_DOMAIN_PP = 0,
    CPPI41_DOMAIN_DSG,
    CPPI41_DOMAIN_DOCSIS_US,
    CPPI41_DOMAIN_NUM
} CPPI41_DOMAIN;

//#define PAL_CPPI_PP_QMGR_GLOBAL_DEFAULT_DESC_SIZE           (64)

/* convert cppi descriptor size tp descriptor hint */
#define PAL_CPPI4_DESCSIZE_2_QMGRSIZE(size)                 ((size - 24) / 4)

/**
 * Accumulator PDSP list entry types
 */
#define PAL_CPPI41_ACC_ENTRY_TYPE_D                         (0)
#define PAL_CPPI41_ACC_ENTRY_TYPE_CD                        (1)
#define PAL_CPPI41_ACC_ENTRY_TYPE_ABCD                      (2)


/**
 *  \defgroup CPPI4_PAL_Ioctl_Codes CPPI4 PAL Ioctl Codes
 */
/*@{*/
#define PAL_CPPI41_IOCTL_GET_SWVER               0       /**< Get software version */
#define PAL_CPPI41_IOCTL_GET_HWVER               1       /**< Get hardware version */
#define PAL_CPPI41_IOCTL_GET_FDQ_STARVE_CNT      2       /**< Get free descriptor queue starvation count */
#define PAL_CPPI41_IOCTL_GET_FDBQ_STARVE_CNT     3       /**< Get the free descriptor/buffer queue starvation count */
#define PAL_CPPI41_IOCTL_GET_QUEUE_PEND_STATUS   4       /**< Get the queue pending status */
#define PAL_CPPI41_IOCTL_GET_QUEUE_ENTRY_COUNT   5       /**< Get the queue entry count */
#define PAL_CPPI41_IOCTL_GET_QUEUE_BYTE_COUNT    6       /**< Get the queue byte count */
#define PAL_CPPI41_IOCTL_GET_QUEUE_HEAD_PKT_SIZE 7       /**< Get the head packet size */
#define PAL_CPPI41_IOCTL_QUEUE_DIVERT            8       /**< Divert contents of one queue to another */
#define PAL_CPPI41_IOCTL_BUFMGR_SOFT_RESET       9       /**< Soft reset the buffer manager */
#define PAL_CPPI41_IOCTL_BUF_REFCNT_INCR        10       /**< Increment buffer reference count */

/**
 * PAL Handles
 */
/* The PAL layer handle */
typedef void* PAL_Handle;
/* Accumulator PDSP channel handle, return from open accumulator channel */
typedef void* PAL_Cppi4AccChHnd;
/* CPPI Queue handle, return from open queue, used for push/pop/close queue operations */
typedef void* PAL_Cppi4QueueHnd;
/* The PAL CPPI4 Buffer descriptor type */
typedef unsigned int PAL_Cppi4BD;
#define CPPI41_EM_DESCINFO_DTYPE_SHIFT     30
#define CPPI41_EM_DESCINFO_DTYPE_MASK      (0x3u<<CPPI41_EM_DESCINFO_DTYPE_SHIFT)
#define CPPI41_EM_DESCINFO_DTYPE_EMB       0
#define CPPI41_EM_DESCINFO_SLOTCNT_SHIFT   27
#define CPPI41_EM_DESCINFO_SLOTCNT_MASK    (0x7u<<CPPI41_EM_DESCINFO_SLOTCNT_SHIFT)
#define CPPI41_EM_DESCINFO_PSWSIZE_SHIFT   22
#define CPPI41_EM_DESCINFO_PSWSIZE_MASK    (0x1Fu<<CPPI41_EM_DESCINFO_PSWSIZE_SHIFT)
#define CPPI41_EM_DESCINFO_PKTLEN_SHIFT    0
#define CPPI41_EM_DESCINFO_PKTLEN_MASK     (0x003FFFFFu<<CPPI41_EM_DESCINFO_PKTLEN_SHIFT)

#define CPPI41_EM_TAGINFO_SRCPORT_SHIFT    27
#define CPPI41_EM_TAGINFO_SRCPORT_MASK     (0x1Fu<<CPPI41_EM_TAGINFO_SRCPORT_SHIFT)
#define CPPI41_EM_TAGINFO_SRCCHN_SHIFT     21
#define CPPI41_EM_TAGINFO_SRCCHN_MASK      (0x3Fu<<CPPI41_EM_TAGINFO_SRCCHN_SHIFT)
#define CPPI41_EM_TAGINFO_SRCSUBCHN_SHIFT  16
#define CPPI41_EM_TAGINFO_SRCSUBCHN_MASK   (0x1Fu<<CPPI41_EM_TAGINFO_SRCSUBCHN_SHIFT)
#define CPPI41_EM_TAGINFO_DSTTAG_SHIFT     0
#define CPPI41_EM_TAGINFO_DSTTAG_MASK      (0xFFFFu<<CPPI41_EM_TAGINFO_DSTTAG_SHIFT)

#define CPPI41_EM_PKTINFO_PKTERROR_SHIFT    31
#define CPPI41_EM_PKTINFO_PKTERROR_MASK    (1u<<CPPI41_EM_PKTINFO_PKTERROR_SHIFT)

#define CPPI41_EM_PKTINFO_PKTTYPE_SHIFT     26
#define CPPI41_EM_PKTINFO_PKTTYPE_MASK     (0x1Fu<<CPPI41_EM_PKTINFO_PKTTYPE_SHIFT)
#define CPPI41_EM_PKTINFO_PKTTYPE_ATMAAL5           0
#define CPPI41_EM_PKTINFO_PKTTYPE_ATMNULLAAL        1
#define CPPI41_EM_PKTINFO_PKTTYPE_ATMOAM            2
#define CPPI41_EM_PKTINFO_PKTTYPE_ATMTRANSPARENT    3
#define CPPI41_EM_PKTINFO_PKTTYPE_EFM               4
#define CPPI41_EM_PKTINFO_PKTTYPE_USB               5
#define CPPI41_EM_PKTINFO_PKTTYPE_GENERIC           6
#define CPPI41_EM_PKTINFO_PKTTYPE_ETH               7


#define CPPI41_EM_PKTINFO_EOPIDX_SHIFT     20
#define CPPI41_EM_PKTINFO_EOPIDX_MASK      (0x7u<<CPPI41_EM_PKTINFO_EOPIDX_SHIFT)
#define CPPI41_EM_PKTINFO_PROTSPEC_SHIFT   16
#define CPPI41_EM_PKTINFO_PROTSPEC_MASK    (0xFu<<CPPI41_EM_PKTINFO_PROTSPEC_SHIFT)
#define CPPI41_EM_PKTINFO_RETPOLICY_SHIFT  15
#define CPPI41_EM_PKTINFO_RETPOLICY_MASK   (1u<<CPPI41_EM_PKTINFO_RETPOLICY_SHIFT)
#define CPPI41_EM_PKTINFO_ONCHIP_SHIFT     14
#define CPPI41_EM_PKTINFO_ONCHIP_MASK      (1u<<CPPI41_EM_PKTINFO_ONCHIP_SHIFT)
#define CPPI41_EM_PKTINFO_RETQMGR_SHIFT    12
#define CPPI41_EM_PKTINFO_RETQMGR_MASK     (0x3u<<CPPI41_EM_PKTINFO_RETQMGR_SHIFT)
#define CPPI41_EM_PKTINFO_RETQ_SHIFT       0
#define CPPI41_EM_PKTINFO_RETQ_MASK        (0x7FFu<<CPPI41_EM_PKTINFO_RETQ_SHIFT)

#define CPPI41_EM_BUF_VALID_SHIFT          31
#define CPPI41_EM_BUF_VALID_MASK           (1u << CPPI41_EM_BUF_VALID_SHIFT)
#define CPPI41_EM_BUF_MGR_SHIFT            29
#define CPPI41_EM_BUF_MGR_MASK             (0x3u << CPPI41_EM_BUF_MGR_SHIFT)
#define CPPI41_EM_BUF_POOL_SHIFT           24
#define CPPI41_EM_BUF_POOL_MASK            (0x1Fu << CPPI41_EM_BUF_POOL_SHIFT)
#define CPPI41_EM_BUF_BUFFLEN_MASK         (0x3FFFFFu)


/* Commonly used values */
#define CPPI41_EM_DESCINFO_SLOTCNT_MYCNT        ((EMSLOTCNT-1u)<<CPPI41_EM_DESCINFO_SLOTCNT_SHIFT)
#define CPPI41_EM_DESCINFO_SLOTCNT_PP           ((EMSLOTCNT_PP-1u)<<CPPI41_EM_DESCINFO_SLOTCNT_SHIFT)
#define CPPI41_EM_DESCINFO_SLOTCNT_MPEG         ((EMSLOTCNT-1u)<<CPPI41_EM_DESCINFO_SLOTCNT_SHIFT)
#define CPPI41_EM_DESCINFO_SLOTCNT_MPEG_ENCAP   ((EMSLOTCNT_EXT-1u)<<CPPI41_EM_DESCINFO_SLOTCNT_SHIFT)
#define CPPI41_EM_DESCINFO_DTYPE_EMBEDDED       (0u<<CPPI41_EM_DESCINFO_DTYPE_SHIFT)
#define CPPI41_EM_PKTINFO_RETPOLICY_RETURN      (1u<<CPPI41_EM_PKTINFO_RETPOLICY_SHIFT)

/**
 * \brief CPPI4.1 Host descriptor structure.
 *
 * The CPPI4.1 Host descriptor structure is defined here to enable its
 * reuse across various driver modules. The PAL CPPI (much like the
 * underlying hardware) does not use the descriptor structre internally
 * for any of its operations.
 */
typedef struct {
	Uint32 descInfo;     /**< Desc type, proto specific word cnt, pkt len (valid only in Host PD)*/
	Uint32 tagInfo;      /**< Source tag (31:16), Dest Tag (15:0) (valid only in Host PD)*/
	Uint32 pktInfo;      /**< pkt err state, type, proto flags, return info, desc location */
	Uint32 buffLen;      /**< Number of valid data bytes in the buffer */
	Uint32 bufPtr;       /**< Pointer to the buffer associated with this descriptor */
	Ptr nextBDPtr;       /**< Pointer to the next buffer descriptor */
	Uint32 orgBuffLen;   /**< Original buffer size */
	Uint32 orgBufPtr;    /**< Original buffer pointer */
	Uint32 netInfoWord0; /**< Network stack private communications info (valid only in Host PD) */
    Uint32 netInfoWord1; /**< Network stack private communications info (valid only in Host PD) */
} Cppi4HostDesc;

typedef struct
{
	Cppi4HostDesc       hw;         /* The Hardware Descriptor */
	int                 psi[5];     /* protocol specific information for fw  */
	struct sk_buff*     skb;        /* The data pointer virtual address */
} Cppi4HostDescLinux;

#define PAL_CPPI4_HOSTDESC_DESC_TYPE_SHIFT      27
#define PAL_CPPI4_HOSTDESC_DESC_TYPE_MASK       (0x1F << PAL_CPPI4_HOSTDESC_DESC_TYPE_SHIFT)
#define PAL_CPPI4_HOSTDESC_DESC_TYPE_HOST       16

#define PAL_CPPI4_HOSTDESC_PROT_WORD_CNT_SHIFT  22
#define PAL_CPPI4_HOSTDESC_PROT_WORD_CNT_MASK   (0x1F << PAL_CPPI4_HOSTDESC_PROT_WORD_CNT_SHIFT)

#define PAL_CPPI4_HOSTDESC_PKT_LEN_SHIFT        0
#define PAL_CPPI4_HOSTDESC_PKT_LEN_MASK         (0x1FFFFF << PAL_CPPI4_HOSTDESC_PKT_LEN_SHIFT)

#define PAL_CPPI4_HOSTDESC_PKT_ERR_SHIFT        31
#define PAL_CPPI4_HOSTDESC_PKT_ERR_MASK         (0x1 << PAL_CPPI4_HOSTDESC_PKT_ERR_SHIFT)
#define PAL_CPPI4_HOSTDESC_PKT_ERR_NOERR        0
#define PAL_CPPI4_HOSTDESC_PKT_ERR_ERR          1

#define PAL_CPPI4_HOSTDESC_PKT_TYPE_SHIFT       26
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_MASK        (0x1F << PAL_CPPI4_HOSTDESC_PKT_TYPE_SHIFT)
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_ATMAAL5             0
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_ATMNULLAAL          1
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_ATMOAM              2
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_ATMTRANSPARENT      3
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_EFM                 4
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_USB                 5
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_GENERIC             6
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_ETH                 7
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_MPEG                8
#define PAL_CPPI4_HOSTDESC_PKT_TYPE_CMD                 0x12

#define PAL_CPPI4_HOSTDESC_PKT_RETPLCY_SHIFT    15
#define PAL_CPPI4_HOSTDESC_PKT_RETPLCY_MASK     (0x1 << PAL_CPPI4_HOSTDESC_PKT_RETPLCY_SHIFT)
#define PAL_CPPI4_HOSTDESC_PKT_RETPLCY_LINKED   0
#define PAL_CPPI4_HOSTDESC_PKT_RETPLCY_UNLINKED 1

#define PAL_CPPI4_HOSTDESC_DESC_LOC_SHIFT       14
#define PAL_CPPI4_HOSTDESC_DESC_LOC_MASK        (0x1 << PAL_CPPI4_HOSTDESC_DESCLOC_SHIFT)
#define PAL_CPPI4_HOSTDESC_DESC_LOC_OFFCHIP     0
#define PAL_CPPI4_HOSTDESC_DESC_LOC_ONCHIP      1

#define PAL_CPPI4_HOSTDESC_PKT_RETQMGR_SHIFT    12
#define PAL_CPPI4_HOSTDESC_PKT_RETQMGR_MASK     (0x3 << PAL_CPPI4_HOSTDESC_PKT_RETQMGR_SHIFT)
#define PAL_CPPI4_HOSTDESC_PKT_RETQNUM_SHIFT    0
#define PAL_CPPI4_HOSTDESC_PKT_RETQNUM_MASK     (0xFFF << PAL_CPPI4_HOSTDESC_PKT_RETQNUM_SHIFT)

#define PAL_CPPI4_HOSTDESC_NETINFW0_DIVERT_FLAG_MASK    0x80
#define PAL_CPPI4_HOSTDESC_NETINFW0_DO_NOT_DISCARD      0x80000000
#if PUMA7_OR_NEWER_SOC_TYPE
#define PAL_CPPI4_HOSTDESC_NETINFW0_SESSION_VALID       0x00000001
#define PAL_CPPI4_HOSTDESC_NETINFW0_IPV4_DF             0x00000200
#define PAL_CPPI4_HOSTDESC_NETINFW0_HOST_PRIO_SET       0x00400000
#define PAL_CPPI4_HOSTDESC_NETINFW0_MTA_FLAG_MASK       0x00800000
#define PAL_CPPI4_HOSTDESC_NETINFW0_PTID_FLAG_MASK      0x40000000
#endif

#define PAL_CPPI4_MONODESC_DESC_TYPE_SHIFT      27
#define PAL_CPPI4_MONODESC_DESC_TYPE_MASK       (0x1F << PAL_CPPI4_MONODESC_DESC_TYPE_SHIFT)
#define PAL_CPPI4_MONODESC_DESC_TYPE_MONO       18

#define PAL_CPPI4_TDDESC_DESC_TYPE_SHIFT      27
#define PAL_CPPI4_TDDESC_DESC_TYPE_MASK       (0x1F << PAL_CPPI4_TDDESC_DESC_TYPE_SHIFT)
#define PAL_CPPI4_TDDESC_DESC_TYPE_TD         19

/**
 * The Queue Tuple
 * The basic queue tuple in CPPI 4.1 used across alldata
 * structures where a definition of a queue is required.
 */
typedef struct
{
    unsigned int qMgr;    /* The queue manager number */
    unsigned int qNum;    /* The queue number */
} Cppi4Queue;


/**
 * \brief The BufPool Tuple
 *   The basic BufPool tuple in CPPI 4.1 used across all data
 *   structures where a definition of a buffer pool is required.
 */
typedef struct
{
    Uint32 bMgr;        /**< The buffer manager number */
    Uint32 bPool;       /**< The buffer pool number */
} Cppi4BufPool;

/**
 * \brief The BufPool Info
 *  A broader information about a specific buffer pool
 */
typedef struct
{
    Uint32 bPoolPhyAddr;
    Uint32 bPoolSize;
    Uint32 bufSize;
    Uint32 numBuf;
    Uint32 bPoolTopPhyAddr;
    Uint32 bPoolOffset;
} Cppi4BufPoolInfo;

/**
 * \brief The CPPI4 descriptor region.
 * Defines the characteristics of a descriptor region.
 */
typedef struct
{
    Bool    isAllocated;    /**< Information on whether this region has been allocated or not   */
    Bool    isOnChip;       /**< Defines if the descriptor region is on chip or not             */
    Bool    isPreAllocated; /**< Defines if need to be internally allocated by CPPI init code   */
    Bool    reserved;

    Ptr     base;           /**< The base address of descriptor region. For off-chip descriptors, this is ignored. The CPPI4.1
                             initialization API will provide a base in this case. A base must be provided in case of on-chip descriptors.
                             This base should be physical address. In all cases, care should be taken to make sure the base addresses of
                             consecutive regions are in ascending order.    */
    Uint32  szDesc;         /**< Size of each descriptor in the region          */
    Uint32  numDesc;        /**< The number of descriptors in the region        */
} Cppi4DescReg;

/**
 * \brief Accumulator list mode configuration
 *
 * In the list mode accumulator pops a given queue and populates a list in memory
 * with the queue elements. Once done it raises an interrupt based on the pacing criteria.
 *
 * This structure defines the accumulator channel configuration when it is used
 * in the list mode. This structure is embedded as part of the ::Cppi4AccumulatorCfg
 * structure.
 */
typedef struct
{
    void          *listBase;        /**< The descriptor list base. */
    unsigned int  maxPageEntry;     /**< Maximum number of entries per page */
    unsigned int  pacingMode;       /**< Interrupt pacing mode: <BR>
                                         0 => None. Interrupt on entry threshold count. <BR>
                                         1 => Time delay since last interrupt. <BR>
                                         2 => delay since first new packet <BR>
                                         3 => delay since last new packet */
    unsigned int  stallAvoidance;   /**< 0 => Do not hold off interrupts to avoid a stall. <BR>
                                         1 => Hold off passing the final list page to the host when the host is congested <BR>
                                         and additional packet descriptors can be appended to the current list. */
    unsigned int  listCountMode;    /**< 0 => NULL Terminate Mode - The last list entry is used to store a NULL pointer record <BR>
                                         (NULL terminator) to mark the end of list. <BR>
                                         1 => Entry Count Mode - The first list entry is used to store the total list entry count <BR>
                                         (not including the length entry). */
    unsigned int listEntrySize;     /**< Type of descriptor information required in the list. <BR>
                                         0 => Reg D only (4 bytes), <BR>
                                         1 => Reg C & D (8 bytes) <BR>
                                         2 => Reg A, B, C, D */
    unsigned int maxPageCnt;        /**< Number of ping/pong pages. Valid values 2 or 3 */

} Cppi4AccListCfg;

/**
 * \brief Accumulator monitor mode configuration
 *
 * In the monitor mode accumulator only monitors a given queue to see if it has elements enqueued.
 * If the queue has reached the given element count it raises an interrupt based on the pacing criteria.
 *
 * This structure defines the accumulator channel configuration when it is used
 * in monitor mode. This structure is embedded as part of the ::Cppi4AccumulatorCfg
 * structure.
 */
typedef struct
{
    unsigned int  pktCountThresh; /**< The packet count threshold */
    unsigned int  pacingMode;     /**< Interrupt pacing mode: <BR>
                                          0 => None. Interrupt on entry threshold count. <BR>
                                          1 => Time delay since count threshold reached. <BR> */
} Cppi4AccMonitorCfg;

/**
 * \brief Accumulator channel configuration
 *
 * This defines the accumulator channel properties for a given host mode Tx/Rx channel
 * An instance of this structure will be part of the channel initial configuration
 * structure. This structure makes sense only for host mode channels.
 */
typedef struct
{
    unsigned int  accChanNum;         /**< Accumulator channel number */
    unsigned int  mode;               /**<    0 => list mode
                                              1 => monitor mode */
    Cppi4Queue    queue;              /**< The queue to monitor */

    unsigned int  pacingTickCnt;      /**< Number of 25us timer ticks to delay interrupt */

    Cppi4AccListCfg   list;           /**< Normal mode configuration */
    Cppi4AccMonitorCfg  monitor;      /**< Monitor mode configuration */

} Cppi4AccumulatorCfg;

/**
 * \brief Accumulator channel rate limit configuration
 *
 * This defines the accumulator channel properties for a given host mode Tx/Rx channel
 * An instance of this structure will be part of the channel initial configuration
 * structure. This structure makes sense only for host mode channels.
 */
typedef struct
{
    Uint32  accChanNum;         /**< Accumulator channel number */
    Uint16  retQ;            /**< Host FD Return Queue */
    Uint16  upperThreshold;  /**< Infra DMA OutQ threshold from which we start dropping packets */
    Uint16  lowerThreshold;  /**< Infra DMA OutQ threshold from which we stop dropping packets */
    Uint16  reserved;
} Cppi4AccumulatorRateLimitCfg;

/**
 *  \brief CPPI4 PAL Accumulator Channel object
 *
 *  CPPI4 PAL layer Object - encapsulates all bookeeping and data structures for
 *  CPPI4 PAL
 */
typedef struct PAL_Cppi4AccChObj_t
{
    struct Cppi4PALObj_t *palCppi4Obj;  /**< Back reference to the CPPI 4.1 structure */
    Uint32 curPage;                     /**< Current accumulator page. */
    Cppi4AccumulatorCfg initCfg;         /**< The accumulator channel init configuration */

} PAL_Cppi4AccChObj;

typedef enum cppi_desc_type
{
    CPPI41_DESC_TYPE_EMBEDDED = 0,
    CPPI41_DESC_TYPE_HOST,
    CPPI41_DESC_TYPE_MONOLITHIC,
    CPPI41_DESC_TYPE_TEARDOWN
} CPPI41_DESC_TYPE;

typedef enum desc_type
{
    DESC_EMBEDDED = 0,
    DESC_HOST = 16,
    DESC_MONOLITHIC = 18,
    DESC_TEARDOWN = 19
} DESC_TYPE;

typedef struct {

  Uint32 BufInfo;
  Uint32 BufPtr;                // Pointer to the physical data buffer
} Cppi4EmbdBuf;

typedef struct {
    Uint32 descInfo;     /**< Desc type, proto specific word cnt, pkt len (valid only in Host PD)*/
    Uint32 tagInfo;      /**< Source tag (31:16), Dest Tag (15:0) (valid only in Host PD)*/
    Uint32 pktInfo;      /**< pkt err state, type, proto flags, return info, desc location */
    Cppi4EmbdBuf Buf;
    Uint32 EPI[2];       /**< Extended Packet Information (from SR) */
} Cppi4EmbdDescPp;

typedef struct
{
    Uint32 descInfo;     /**< Desc type, proto specific word cnt, pkt len (valid only in Host PD)*/
    Uint32 tagInfo;      /**< Source tag (31:16), Dest Tag (15:0) (valid only in Host PD)*/
    Uint32 pktInfo;      /**< pkt err state, type, proto flags, return info, desc location */
    Cppi4EmbdBuf Buf[1];
    Uint32 EPI[2];       /**< Extended Packet Information (from SR) */
    Uint32 PS[3];       /**< Extended Packet Information (from SR) */
} Cppi4EmbdDesc_ps;

/***************************************/
/*  enum for endianness conversion    **/
/**************************************/
typedef struct
{
    Cppi4Queue          fdQueue;
    Uint32              qsmonThread;
    Uint32              qsmonThreshold;
    Bool                qsmonChEn;
    Bool                ralQEnable;
    Bool                direction;
} qsmonRal_t;

typedef enum
{
    PAL_CPPI_ALLOC_NONE,
    PAL_CPPI_ALLOC_CALLOC,
    PAL_CPPI_ALLOC_MALLOC,
    PAL_CPPI_ALLOC_SKB
}
FDqueueBuffAllocType_e;

typedef struct FDqueue
{
    Uint8                       descRegion;     /* Type: PAL_CPPI_PP_DESC_REGIONs_e */
    Uint8                       descType;       /* Type: CPPI41_DESC_TYPE */
    Uint16                      descCount;
    Uint16                      descSize;
    Uint16                      qId;
    Uint8                       qMgr;           /* Types: PAL_CPPI_PP_QMGRs_e, PAL_CPPI_DSG_QUEUE_MNGRS_e, ... */
    FDqueueBuffAllocType_e      allocType;
    Uint32                      bPool;          /* Used to calculate runtime the buffers required for each pool*/
}
FDqueue_t;

typedef enum
{
    endiannessBig,
    endiannessLittle
}endianness_e;

#ifdef __KERNEL__



/* convert DDR physical address to DDR virtual address - use netip_mmio functions if pp is present */
#ifdef CONFIG_TI_PACKET_PROCESSOR
#define PAL_CPPI4_PHYS_2_VIRT(addr)                        (netip_mmio_to_virtual(addr))  /* X86 implementation here */
/* convert DDR virtual address to DDR physical address */
#define PAL_CPPI4_VIRT_2_PHYS(addr)                        (netip_mmio_to_physical(addr))  /* X86 implementation here */
#else
/* convert DDR physical address to DDR virtual address */
#define PAL_CPPI4_VIRT_2_PHYS(addr)     PAL_osMemVirt2Phy((Ptr)(addr))
/* convert DDR virtual address to DDR physical address */
#define PAL_CPPI4_PHYS_2_VIRT(addr)     PAL_osMemPhy2Virt((Uint32)(addr))
#endif

#ifdef CONFIG_NET_SUBSYSTEM_SNOOPED_MODE

#define PAL_CPPI4_CACHE_WRITEBACK(addr, size)			do {} while(0);
#define PAL_CPPI4_CACHE_WRITEBACK_INVALIDATE(addr, size)	do {} while(0);
#define PAL_CPPI4_CACHE_INVALIDATE(addr, size)			do {} while(0);

#else

#define PAL_CPPI4_CACHE_WRITEBACK(addr, size)			clflush_cache_range(addr, size)
#define PAL_CPPI4_CACHE_WRITEBACK_INVALIDATE(addr, size)	clflush_cache_range(addr, size)
#define PAL_CPPI4_CACHE_INVALIDATE(addr, size)			clflush_cache_range(addr, size)

#endif

/**
 *  \brief PAL CPPI4.1 Initialization.
 *
 *  This function initializes the CPPI4.1 PAL layer.  This is the first function to be
 *  called by a module requiring CPPI4.1 support.  Multiple upper layers may call
 *  this function, although only one actual instance will be created.  After the
 *  first call, subsequent callers will simply be given the PAL Handle that was
 *  allocated during the first call.
 *
 *  In the typical scenerio, this API will be called once during system boot-up
 *  and other drivers/modules can call the API will NULL parameters to retrieve
 *  the PAL handle
 *
 *  The PAL handle that is returned must be used to close the PAL interface.
 *
 *  This function will bring the networking subsystem, out of reset, and
 *  initialize the queue manager/buffer manager and DMA hardware.
 *
 *  \note: The initCfg parameter values are only valid for the first caller - i.e.
 *  the CPPI4 PAL is initialized only once, regardless of the number of calls to
 *  this function.
 *
 *  @param  initCfg      [IN]      Pointer to CPPI4 config structure, to be
 *                                 allocated and loaded with values by the caller.
 *  @param  param        [IN]      Not used in this implementation. For future use.
 *
 *  @return a valid ::PAL_Handle on success, NULL otherwise.
 */
PAL_Handle PAL_cppi4Init (void * initCfg, Ptr param);

/**
 *  \brief PAL CPPI4.1 de-initialization.
 *
 *  @return 0 on success, non zero value otherwise.
 */
int PAL_cppi4Exit(PAL_Handle hnd, void *param);

/**
 *  \brief PAL CPPI4.1 Decrement the reference count of buffer
 *
 *  Decrement the reference count of the buffer.
 *
 *  @param  hnd        [IN]      PAL handle returned from a previous PAL_cppi4Init() call.
 *
 *  @param  pool       [IN]      The buffer pool to which buffer belonged.
 *
 *  @param  bufPtr     [IN]      Buffer pointer whose reference count needs to be decremented
 *
 *  @return PAL_SOK
 */
int PAL_cppi4BufDecRefCnt (PAL_Handle hnd, Cppi4BufPool pool, Ptr bufPtr);

/**
 *  \brief PAL CPPI4.1 Pop buffer and Increment reference count
 *
 *  Pop buffer from buffer pool and Increment reference count.
 *
 *  @param  hnd        [IN]      PAL handle returned from a previous PAL_cppi4Init() call.
 *
 *  @param  pool       [IN]      The buffer pool to which buffer belonged.
 *
 *  @return Buffer point, NULL is pool is empty
 */
Ptr PAL_cppi4BufPopBuf (PAL_Handle hnd, Cppi4BufPool pool);

/**
 *  \brief PAL CPPI4.1 Queue Open
 *
 *  This function configures and opens a specified Queue.
 *
 *  @param  hnd   [IN] - Handle to the PAL Layer.
 *  @param  queue [IN] - The queue to open.
 *
 *  @return a valid ::PAL_Cppi4QueueHnd on success and NULL on
 *          failure.
 */
PAL_Cppi4QueueHnd PAL_cppi4QueueOpen(PAL_Handle hnd, Cppi4Queue  queue);

/*
 *  PAL_cppi4QueueOpenNoReset
 *  - Sanity tool compatibility
 */
PAL_Cppi4QueueHnd PAL_cppi4QueueOpenNoReset (PAL_Handle hnd, Cppi4Queue  queue);

/**
 * \brief CPPI4.1 Queue Close
 *  closes a specified Queue when the last time it is called.
 *  For every other call it decrements the reference to the queue object.
 *  Actually it does nothing on APPCPU.
 *
 * @param hnd NULL
 * @param qHnd queue handle returned from queue open
 *
 * @return 0 on success or non zero value otherwise .
 */
int PAL_cppi4QueueClose(PAL_Handle hnd, PAL_Cppi4QueueHnd qHnd);

/**
 *  \brief CPPI4.1 Queue Push
 *
 *  This function is called to queue a descriptor onto a queue.
 *
 *  @param  hnd Handle to the Queue (PAL_Cppi4QueueHnd).
 *  @param  dAddr descriptor physical address.
 *  @param  dSize descriptor size.
 *  @param  pSize packet size.
 *
 *  \note pSize parameter is optional. Pass NULL in case not required.
 *
 *  @return a valid PAL_Cppi4QueueHnd on success and NULL on
 *          failure.
 */
static inline __attribute__((always_inline)) int PAL_cppi4QueuePush(PAL_Cppi4QueueHnd hnd, void *dAddr, unsigned int dSize, unsigned int pSize)
{
    volatile unsigned int tmp;
    CSL_Queue_Mgmt_Regs *qRegs;
    Cppi4HostDescLinux *desc;

    qRegs = (CSL_Queue_Mgmt_Regs *) hnd;
    desc = (Cppi4HostDescLinux *) dAddr;
    tmp = (dSize << QMGR_QUEUE_N_REG_D_DESCSZ_SHIFT) & QMGR_QUEUE_N_REG_D_DESCSZ_MASK;
    tmp|= ((volatile unsigned int)dAddr & QMGR_QUEUE_N_REG_D_DESC_ADDR_MASK);

    //printk("%s(%d): Pushing desc %p to queue 0x%08x\n", __FUNCTION__ , __LINE__, dAddr, netip_mmio_to_physical(qRegs));

   /* handle associated with ADP0 Queue */
#ifdef DEBUG_PAL_CPPI
    if(((int)hnd & 0xFFFF) == 0x1b30)
    {
        //printk("%s(%d): Qhandle=%p Desc=%p\n", __FUNCTION__ , __LINE__, hnd, desc);
    }
#endif

    /* refered from NPCPU pal_cpp:  Similar logic here what is there in NPCPU side */
    /* qRegs->Queue_Reg_C = cpu_to_be32(pSize); */

/* Swap endianness*/
    qRegs->Queue_Reg_D = cpu_to_be32(tmp);

    return 0;
}

/**
 *  \brief CPPI4.1 Queue Pop
 *
 *  This function is called to pop descriptor from specific
 *  queue.
 *
 *  @param  hnd Handle to the Queue (PAL_Cppi4QueueHnd).
 *
 *  @return Buffer descriptor physical address.
 */
static inline __attribute__((always_inline)) PAL_Cppi4BD *PAL_cppi4QueuePop(PAL_Cppi4QueueHnd hnd)
{
    PAL_Cppi4BD *bd;

    CSL_Queue_Mgmt_Regs *qRegs = (CSL_Queue_Mgmt_Regs *) hnd;

    bd = (PAL_Cppi4BD *)( (be32_to_cpu(qRegs->Queue_Reg_D)) & QMGR_QUEUE_N_REG_D_DESC_ADDR_MASK);

    //printk("%s(%d): Popped desc %p from queue 0x%08x\n", __FUNCTION__ , __LINE__, bd, netip_mmio_to_physical(qRegs));
    return bd;
}

/**
 *  \brief CPPI4.1 Queue Get Entries Count
 *
 *  This function is called to get the number of descriptors in
 *  a queue.
 *
 *  @param  hnd PAL handle returned from a previous
 *              PAL_cppi4Init() call
 *  @param  queue Handle to the Queue (PAL_Cppi4QueueHnd).
 *  @param  entryCount [out] Number of entries in queue.
 *
 *  @return 0 on succuss, non zero value otherwise.
 */
int PAL_cppi4QueueGetEntryCount(PAL_Handle hnd, Cppi4Queue queue, unsigned int *entryCount);

#ifdef CONFIG_MRPC_CPPI_CLIENT
/**
 *  \brief Get buffer pool info for WiFi TX Zero Copy feature
 *
 *  @param  hnd           [IN]      Handle to the PAL Layer.
 *  @param  pool          [IN]      Buffer pool num.
 *  @param  bp_info       [OUT]     Buffer Pool Info structure
 *                        Ptr.
 *
 *  @return PAL_SOK on success
 */
PAL_Result PAL_cppi4GetBufferPoolInfo(PAL_Handle hnd, Cppi4BufPool pool, Cppi4BufPoolInfo* bp_info);

/**
 * Retrieve all cppi buffers pools information from cppi driver
 * on ARM
 *
 * @param pools array to fill in the pools info
 *
 * @return int 0 on success, non-zero value otherwise
 */
PAL_Result PAL_cppi4GetAllBufferPoolsInfo(PAL_Handle hnd, Cppi4BufPoolInfo *pools);
#endif

/**
 *  \brief PAL CPPI 4.1 accumulator channel enable rate limit.
 *
 * Sets up an accumulator channel rate limit onfiguration
 * 
 *  @param  accCfg        [IN]      Pointer to the accumulator
 *                        rate limit configuration structure.
 *
 */
void PAL_cppi4AccChEnRateLimit(Cppi4AccumulatorRateLimitCfg* accCfg);

/**
 *  \brief PAL CPPI 4.1 pdsp_cmd_send registration.
 *
 * Sets up the pdsp_cmd_send function callback used by PAL CPPI
 * driver.
 *
 *  @param  cb            [IN]      pdsp_cmd_send callback
 *                                  function
 *
 *  @return PAL_SOK on success, else failure code.
 */
PAL_Result PAL_cppi4PdspCmdSendRegister(Int32 (*cb)(pdsp_id_t, pdsp_cmd_t, void *, Uint32, void *, Uint32));

/**
 *  \brief PAL CPPI 4.1 pdsp_cmd_send unregistration.
 *
 * Unregisters the pdsp_cmd_send function callback used by PAL
 * CPPI driver.
 *
 *  @return PAL_SOK on success, else failure code.
 */
PAL_Result PAL_cppi4PdspCmdSendUnregister(void);

/**
 *  \brief PAL CPPI 4.1 accumulator channel setup.
 *
 * Sets up an accumulator channel to monitor a queue.
 *
 *  @param  hnd PAL handle
 *  @param  accCfg Pointer to the accumulator configuration
 *                  structure.
 *
 *  @return pointer to a valid handle (PAL_Cppi4AccChHnd) on
 *          success, NULL otherwise.
 */
PAL_Cppi4AccChHnd PAL_cppi4AccChOpen(PAL_Handle hnd, Cppi4AccumulatorCfg* accCfg);

/**
 *  \brief PAL CPPI 4.1 accumulator channel setup with physical
 *         listbase address.
 *
 * Sets up an accumulator channel to monitor a queue.
 *
 *  @param  hnd PAL handle
 *  @param  accCfg Pointer to the accumulator configuration
 *                  structure.
 *
 *  @return pointer to a valid handle (PAL_Cppi4AccChHnd) on
 *          success, NULL otherwise.
 */
PAL_Cppi4AccChHnd PAL_cppi4AccChOpenAppCpu(PAL_Handle hnd, Cppi4AccumulatorCfg* accCfg);

/**
 *  \brief PAL CPPI 4.1 accumulator channel teardown.
 *
 *  Stop an accumulator channel from monitoring a queue.
 *
 *  @param  hnd Accumulator handle (::PAL_Cppi4AccChHnd)
 *  @param  closeArgs For future extension. Pass NULL for now.
 *
 *  @return 0 on success, non zero value otherwise.
 */
int PAL_cppi4AccChClose(PAL_Cppi4AccChHnd hnd, void *closeArgs);


/**
 *  \brief PAL CPPI 4.1 get transmit channel accumulator page.
 *
 *  This function returns pointer to the next page that the accumulator would have populated with
 *  BD list.
 *
 *  \note This function does not have information on whether the page it is returning has <B> really </B>
 *  been populated by accumulator. This information should be available to the driver using the
 *  INTD count register. It is the responsibility of the driver to call this function when it is sure that
 *  the accumulator is finished with updating a new page.
 *
 *  @param  hnd Accumulator channel handle (PAL_Cppi4AccChHnd).
 *
 *  @return Valid pointer (virtual address) to list page on success, NULL otherwise.
 */
void* PAL_cppi4AccChGetNextList(PAL_Cppi4AccChHnd hnd);

/* Following API will use NPCPU-APPCPU Shared memory to provide Accumulator fuctionalities */
/**
 *  \brief PAL CPPI 4.1 accumulator channel setup using shared memory.
 *
 * Sets up an accumulator channel to monitor a queue.
 *
 *  @param  hnd PAL handle
 *  @param  accCfg Pointer to the accumulator configuration
 *                  structure.
 *  @param SharedMemoryBase addres.
 *  @param accListPageSize size of accumulator page.
 *
 *  @return pointer to a valid handle (PAL_Cppi4AccChHnd) on
 *          success, NULL otherwise.
 */
PAL_Cppi4AccChHnd PAL_cppi4AccChOpenSharedMemory(PAL_Handle hnd, Cppi4AccumulatorCfg* accCfg, unsigned long SharedMemoryBase, unsigned long accListPageSize);

/**
 *  \brief PAL CPPI4.1 control API.
 *
 *  This function provides the capability for control operations to be performed
 *  on the PAL CPPI4 module.
 *
 *  The command (cmd) is used to direct the function to perform one or more of
 *  the supported operations.  The commands supported are:
 *
 *  - #PAL_CPPI41_IOCTL_QUEUE_DIVERT
 *          - cmdArg defines the source and destination queue. Also defines if packets
 *          should be added to head/tail of destination queue. This argument is a 32-bit integer
 *          and an exact map of the diversion register in the hardware. param provides the queue manager
 *          index to which the queue belongs.
 *
 *  @param  hnd           [IN]      Handle to the PAL Layer.
 *  @param  cmd           [IN]      Operation to be performed.
 *  @param  cmdArg    [IN/OUT]      Provides additional info for the operation.
 *  @param  param     [IN/OUT]      Cmd specific argument.
 *
 *  @return PAL_SOK on success, else failure code.
 */
int PAL_cppi4Control (PAL_Handle hnd, Uint32 cmd, Ptr cmdArg, Ptr param);

/**************************************************************************/
/*! \fn extern int cppi_get_pp_free_queue_info_according_to_q_manager_and_num
 *                                          (Cppi4Queue* q, FDqueue_t *info)
 **************************************************************************
 *  \brief Gets queue manager and id, and returns the queeeue info.
 **************************************************************************/
extern int cppi_get_pp_free_queue_info_according_to_q_manager_and_num(Cppi4Queue* q,
                                                                     FDqueue_t *info);
#endif /* __KERNEL__ */

#endif /* __PAL_CPPI4_H__ */