/* * * puma7.h * Description: * puma7 parent header file, has all macros related to H/W * This file is provided under a dual BSD/GPLv2 license. When using or redistributing this file, you may do so under either license. GPL LICENSE SUMMARY Copyright(c) 2014-2019 Intel Corporation. This program is free software; you can redistribute it and/or modify it under the terms of version 2 of the GNU General Public License as published by the Free Software Foundation. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. The full GNU General Public License is included in this distribution in the file called LICENSE.GPL. Contact Information: Intel Corporation 2200 Mission College Blvd. Santa Clara, CA 97052 BSD LICENSE Copyright(c) 2014-2019 Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef _PUMA7_H #define _PUMA7_H #define AVALANCHE_SOC_NAME "PUMA7" #include #define IO_ADDRESS(addr) ((unsigned long)netip_mmio_to_virtual(addr)) #define IO_PHY2VIRT(addr) (netip_mmio_to_virtual((unsigned long)addr)) /* X86 implementation here */ /* convert hardware virtual address to hardware physical address */ #define IO_VIRT2PHY(addr) (netip_mmio_to_physical((void *)addr)) /* X86 implementation here */ #define AVALANCHE_GBE0_ADDR ((0xF0300000)) #define AVALANCHE_GBE1_ADDR ((0xF0304000)) #define AVALANCHE_GBE2_ADDR ((0xF0308000)) #define AVALANCHE_GBE3_ADDR ((0xF030C000)) #define AVALANCHE_GBE4_ADDR ((0xF0310000)) #define AVALANCHE_GBE5_ADDR ((0xF0314000)) #define AVALANCHE_MOCA_ADDR ((0xFF800000)) #define ATOM_INTC_BASE ((0xF00E0000)) #define AVALANCHE_PFI_REGS (IO_ADDRESS(0xF0210000)) #define AVALANCHE_PFI_WIN_REGS (IO_ADDRESS(0xF0210400)) #define AVALANCHE_GBE0 (IO_ADDRESS(AVALANCHE_GBE0_ADDR)) #define AVALANCHE_GBE1 (IO_ADDRESS(AVALANCHE_GBE1_ADDR)) #define AVALANCHE_GBE2 (IO_ADDRESS(AVALANCHE_GBE2_ADDR)) #define AVALANCHE_GBE3 (IO_ADDRESS(AVALANCHE_GBE3_ADDR)) #define AVALANCHE_GBE4 (IO_ADDRESS(AVALANCHE_GBE4_ADDR)) #define AVALANCHE_GBE5 (IO_ADDRESS(AVALANCHE_GBE5_ADDR)) #define AVALANCHE_GBE_GENERAL (IO_ADDRESS(0xF0318000)) #define AVALANCHE_GBE_INT_CTRL_0 (IO_ADDRESS(0xF031A000)) #define AVALANCHE_GBE_INT_CTRL_1 (IO_ADDRESS(0xF031A400)) #define AVALANCHE_PHY_SLAVE (IO_ADDRESS(0xF0500000)) #define AVALANCHE_MOCA (IO_ADDRESS(AVALANCHE_MOCA_ADDR)) #define AVALANCHE_CRU_BASE (IO_ADDRESS(0xF00D0000)) /** * Interrupts Distributor 0 (INTD0) base address, has 32 ip * interrupts to 16 system interrupts. */ /******************************************************************************************/ /* follopwing Macros are moved into .c file and global varable */ /******************************************************************************************/ #define AVALANCHE_INTD_BASE_INT 24 // SRTR_INTD16, srtr_intr_16 /** INTD1 interrupt0's line in the system interrupt controller (INTC). */ #define AVALANCHE_INTD1_BASE_INT 40 // SRTR_INTD16, srtr_intr_16 /** * Convert INTD0 interrupt to INTC interrupt line. */ #define MAP_INTD_TO_INTC(intv) ((intv) + AVALANCHE_INTD_BASE_INT) /** * Convert INTD1 interrupt to INTC interrupt line. */ #define MAP_INTD1_TO_INTC(intv) ((intv) + AVALANCHE_INTD1_BASE_INT) typedef enum { e_Interrupt_Disable = 0, e_Interrupt_Enable } AVALANCHE_INTRPT_MODE_T; typedef volatile struct interrupt_bundle_struct { volatile unsigned int interrupt_enable; // Read/Write. volatile unsigned int sw_interrupt; // Write Only. volatile unsigned int edge_or_level; // Read/Write. Edge=0, Level=1 volatile unsigned int mask; // Read/Write. volatile unsigned int interrupt_status_pre_masked; // Read Only. volatile unsigned int interrupt_status_post_masked; // Read Only. Note: Reading cause to status bit clear ! } interrupt_bundle_struct_t; #if 0 /** * Packet Processor Queue Managers */ typedef enum PAL_CPPI_PP_QMGRs { PAL_CPPI_PP_QMGR_G0, PAL_CPPI_PP_QMGR_G1, PAL_CPPI_PP_QMGR_G2, PAL_CPPI_PP_QMGR_LOCAL, PAL_CPPI41_NUM_QUEUE_MGR }PAL_CPPI_PP_QMGRs_e; /** * Accumulator PDSP channels */ /* +-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ |A|c|c|u|m|u|l|a|t|o|r| |C|h|a|n|n|e|l|s| +-+-+-+-+-+-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+ */ /* following varabled are refered from arm SDK include\asm-arm\arch-avalanche\puma7\puma7_cppi_prv.h file */ typedef enum PAL_CPPI_PP_ACCUMULATOR_INTD0_CHANNELS { PAL_CPPI_PP_HOST2PP_TX_COMPLETE_INTD0_ACC_CH_BASE, PAL_CPPI_PP_HOST2PP_TX_COMPLETE_LOW_INTD0_ACC_CH_NUM = PAL_CPPI_PP_HOST2PP_TX_COMPLETE_INTD0_ACC_CH_BASE, // 0 PAL_CPPI_PP_HOST2PP_TX_COMPLETE_HIGH_INTD0_ACC_CH_NUM, // 1 PAL_CPPI_PP_HOST2PP_TX_COMPLETE_INTD0_ACC_CH_LAST = PAL_CPPI_PP_HOST2PP_TX_COMPLETE_HIGH_INTD0_ACC_CH_NUM, PAL_CPPI_PP_MoCA_RX_INTD0_ACC_CH_NUM, // 2 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_3, // 3 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_4, // 4 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_5, // 5 PAL_CPPI_PP_SGMII0_RX_LOW_INTD0_ACC_CH_NUM, // 6 PAL_CPPI_PP_SGMII0_RX_HIGH_INTD0_ACC_CH_NUM, // 7 PAL_CPPI_PP_SGMII1_RX_LOW_INTD0_ACC_CH_NUM, // 8 PAL_CPPI_PP_SGMII1_RX_HIGH_INTD0_ACC_CH_NUM, // 9 PAL_CPPI_PP_RGMII0_RX_LOW_INTD0_ACC_CH_NUM, // 10 PAL_CPPI_PP_RGMII0_RX_HIGH_INTD0_ACC_CH_NUM, // 11 PAL_CPPI_PP_RGMII1_RX_LOW_INTD0_ACC_CH_NUM, // 12 PAL_CPPI_PP_RGMII1_RX_HIGH_INTD0_ACC_CH_NUM, // 13 PAL_CPPI_PP_ATOM_RX_LOW_INTD0_ACC_CH_NUM, // 14 PAL_CPPI_PP_ATOM_RX_HIGH_INTD0_ACC_CH_NUM, // 15 PAL_CPPI_PP_DOCSIS_RX_MGMT_INTD0_ACC_CH_NUM, // 16 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_17, // 17 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_18, // 18 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_19, // 19 PAL_CPPI_PP_DOCSIS_RX_LOW_INTD0_ACC_CH_NUM, // 20 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_21, // 21 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_22, // 22 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_23, // 23 PAL_CPPI_PP_DOCSIS_RX_HIGH_INTD0_ACC_CH_NUM, // 24 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_25, // 25 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_26, // 26 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_27, // 27 PAL_CPPI_PP_VOICE_RX_INTD0_ACC_CH_NUM, // 28 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_29, // 29 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_30, // 30 PAL_CPPI_PP_RESERVED_INTD0_ACC_CH_NUM_31, // 31 PAL_CPPI_PP_INTD0_ACCUMULATOR_MAX_CHANNELS }PAL_CPPI_PP_ACCUMULATOR_INTD0_CHANNELS_e; typedef enum PAL_CPPI_PP_ACCUMULATOR_INTD1_CHANNELS { PAL_CPPI_PP_RESERVED_INTD1_ACC_CH_NUM_0, // 0 PAL_CPPI_PP_RESERVED_INTD1_ACC_CH_NUM_1, // 1 PAL_CPPI_PP_RESERVED_INTD1_ACC_CH_NUM_2, // 2 PAL_CPPI_PP_RESERVED_INTD1_ACC_CH_NUM_3, // 3 PAL_CPPI_PP_RESERVED_INTD1_ACC_CH_NUM_4, // 4 PAL_CPPI_PP_RESERVED_INTD1_ACC_CH_NUM_5, // 5 PAL_CPPI_PP_WiFi_RX_LOW_INTD1_ACC_CH_NUM, // 6 PAL_CPPI_PP_WiFi_RX_HIGH_INTD1_ACC_CH_NUM, // 7 PAL_CPPI_PP_NP2APP_RX_INTD1_ACC_CH_NUM, // 8 PAL_CPPI_PP_NP2APP_TX_COMPLETE_INTD1_ACC_CH_NUM, // 9 PAL_CPPI_PP_APP2NP_RX_INTD1_ACC_CH_NUM, // 10 PAL_CPPI_PP_APP2NP_TX_COMPLETE_INTD1_ACC_CH_NUM, // 11 PAL_CPPI_PP_RESERVED_INTD1_ACC_CH_NUM_12, // 12 PAL_CPPI_PP_RESERVED_INTD1_ACC_CH_NUM_13, // 13 PAL_CPPI_PP_RESERVED_INTD1_ACC_CH_NUM_14, // 14 PAL_CPPI_PP_RESERVED_INTD1_ACC_CH_NUM_15, // 15 PAL_CPPI_PP_INTD1_ACCUMULATOR_MAX_CHANNELS }PAL_CPPI_PP_ACCUMULATOR_INTD1_CHANNELS_e; /** * Accumulator PDSP interrupts vectors, these interrupt are the * outputs of the INTDs */ typedef enum PAL_CPPI_PP_ACCUMULATOR_INTD0_INTERRUPT_VECTORS { PAL_CPPI_PP_HOST2PP_TX_COMPLETE_INTD0_ACC_INTV_NUM, // 0 PAL_CPPI_PP_MoCA_RX_INTD0_ACC_INTV_NUM, // 1 PAL_CPPI_PP_SGMII0_LOW_RX_INTD0_ACC_INTV_NUM, // 2 PAL_CPPI_PP_SGMII0_HIGH_RX_INTD0_ACC_INTV_NUM, // 3 PAL_CPPI_PP_SGMII1_LOW_RX_INTD0_ACC_INTV_NUM, // 4 PAL_CPPI_PP_SGMII1_HIGH_RX_INTD0_ACC_INTV_NUM, // 5 PAL_CPPI_PP_RGMII0_LOW_RX_INTD0_ACC_INTV_NUM, // 6 PAL_CPPI_PP_RGMII0_HIGH_RX_INTD0_ACC_INTV_NUM, // 7 PAL_CPPI_PP_RGMII1_LOW_RX_INTD0_ACC_INTV_NUM, // 8 PAL_CPPI_PP_RGMII1_HIGH_RX_INTD0_ACC_INTV_NUM, // 9 PAL_CPPI_PP_ATOM_LOW_RX_INTD0_ACC_INTV_NUM, // 10 PAL_CPPI_PP_ATOM_HIGH_RX_INTD0_ACC_INTV_NUM, // 11 PAL_CPPI_PP_DOCSIS_RX_MGMT_INTD0_ACC_INTV_NUM, // 12 PAL_CPPI_PP_DOCSIS_RX_LOW_INTD0_ACC_INTV_NUM, // 13 PAL_CPPI_PP_DOCSIS_RX_HIGH_INTD0_ACC_INTV_NUM, // 14 PAL_CPPI_PP_VOICE_RX_INTD0_INTV_NUM, // 15 PAL_CPPI_PP_ACCUMULATOR_INTD0_MAX_INTERRUPT_VECTORS }PAL_CPPI_PP_ACCUMULATOR_INTERRUPT_VECTORS_e; typedef enum PAL_CPPI_PP_ACCUMULATOR_INTD1_INTERRUPT_VECTORS { PAL_CPPI_PP_RESERVED_INTD1_ACC_INTV_NUM_0, // 0 PAL_CPPI_PP_RESERVED_INTD1_ACC_INTV_NUM_1, // 1 PAL_CPPI_PP_WiFi_RX_LOW_INTD1_ACC_INTV_NUM, // 2 PAL_CPPI_PP_WiFi_RX_HIGH_INTD1_ACC_INTV_NUM, // 3 PAL_CPPI_PP_NP2APP_RX_INTD1_ACC_INTV_NUM, // 4 PAL_CPPI_PP_NP2APP_TX_COMPLETE_INTD1_ACC_INTV_NUM, // 5 PAL_CPPI_PP_APP2NP_RX_INTD1_ACC_INTV_NUM, // 6 PAL_CPPI_PP_APP2NP_TX_COMPLETE_INTD1_ACC_INTV_NUM, // 7 PAL_CPPI_PP_RESERVED_INTD1_ACC_INTV_NUM_8, // 8 PAL_CPPI_PP_RESERVED_INTD1_ACC_INTV_NUM_9, // 9 PAL_CPPI_PP_RESERVED_INTD1_ACC_INTV_NUM_10, // 10 PAL_CPPI_PP_RESERVED_INTD1_ACC_INTV_NUM_11, // 11 PAL_CPPI_PP_ACCUMULATOR_INTD1_MAX_INTERRUPT_VECTORS }PAL_CPPI_PP_ACCUMULATOR_INTD1_INTERRUPT_VECTORS_e; #endif #endif /*_PUMA7_H */