/* SPDX-License-Identifier: GPL-2.0-only */ /* * Intel PCH/PCU SPI flash driver. * * Copyright (C) 2016, Intel Corporation * Author: Mika Westerberg */ #ifndef INTEL_SPI_PDATA_H #define INTEL_SPI_PDATA_H #include enum intel_spi_type { INTEL_SPI_BYT = 1, INTEL_SPI_LPT, INTEL_SPI_BXT, INTEL_SPI_CNL, }; /** * struct intel_spi_boardinfo - Board specific data for Intel SPI driver * @type: Type which this controller is compatible with * @set_writeable: Try to make the chip writeable (optional) * @readonly: The chip is read-only * @data: Data to be passed to @set_writeable can be %NULL */ struct intel_spi_boardinfo { enum intel_spi_type type; bool (*set_writeable)(void __iomem *base, void *data); bool readonly; void *data; }; #define PLATFORM_MTD "Platform Data" #define FDR_MAGIC 0x0FF0A55Au #define FDR_MAGIC_OFF 0x10u #define FDR_SECTIONS_OFF 0x40u #define FDR_SECTIONS_NUM 5u #define FDR_SECTION_DESC 0u #define FDR_SECTION_BIOS 1u #define FDR_SECTION_ME 2u #define FDR_SECTION_GBE 3u #define FDR_SECTION_PDR 4u // PDR Image Directory Entry in the first page of PDR struct pdr_image_dir { __le32 id; __le32 offset; __le32 size; __le32 reserved; } __packed; #define PDR_IMAGE_DIR_SIZE 0x1000u #define PDR_IMAGE_DIR_MAX_CNT (PDR_IMAGE_DIR_SIZE / sizeof(struct pdr_image_dir)) #define PDR_IMAGE_ID_IMG_DIR 0x1d000000u #define PDR_IMAGE_ID_AID0 0x0000A1D0u #define PDR_IMAGE_ID_AID1 0x0000A1D1u #define PDR_IMAGE_ID_OEMD0 0x00000ED0u #define PDR_IMAGE_ID_END 0xFFFFFFFFu #endif /* INTEL_SPI_PDATA_H */