--- zzzz-none-000/linux-5.15.111/drivers/i2c/busses/i2c-designware-core.h	2023-05-11 14:00:40.000000000 +0000
+++ puma7-atom-6670-761/linux-5.15.111/drivers/i2c/busses/i2c-designware-core.h	2024-02-07 10:23:01.000000000 +0000
@@ -97,6 +97,11 @@
 #define DW_IC_INTR_GEN_CALL	BIT(11)
 #define DW_IC_INTR_RESTART_DET	BIT(12)
 
+#define        DW_IC_RESETS            0x804
+#define        DW_IC_RESETS_FUNC       BIT(0)
+#define        DW_IC_RESETS_APB        BIT(1)
+#define        DW_IC_GENERAL           0x808
+
 #define DW_IC_INTR_DEFAULT_MASK		(DW_IC_INTR_RX_FULL | \
 					 DW_IC_INTR_TX_ABRT | \
 					 DW_IC_INTR_STOP_DET)
@@ -231,6 +236,7 @@
  * @init: function to initialize the I2C hardware
  * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
  * @suspended: set to true if the controller is suspended
+ * @shared_host: if this host is shared by other units on the SoC
  *
  * HCNT and LCNT parameters can be used if the platform knows more accurate
  * values than the one computed based only on the input clock frequency.
@@ -279,6 +285,7 @@
 	u16			fp_lcnt;
 	u16			hs_hcnt;
 	u16			hs_lcnt;
+	int			shared_host;
 	int			(*acquire_lock)(void);
 	void			(*release_lock)(void);
 	bool			shared_with_punit;
@@ -289,6 +296,9 @@
 	int			mode;
 	struct i2c_bus_recovery_info rinfo;
 	bool			suspended;
+	int			polling;
+	int			(*acquire_ownership) (void);
+	int			(*release_ownership) (void);
 };
 
 #define ACCESS_INTR_MASK	BIT(0)
@@ -312,7 +322,9 @@
 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev);
 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev);
 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare);
+#if 0
 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev);
+#endif
 void i2c_dw_release_lock(struct dw_i2c_dev *dev);
 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev);
 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev);