#ifndef RTK_RG_PORT_H
#define RTK_RG_PORT_H

#if defined(CONFIG_RTL9607C_SERIES)
#ifdef CONFIG_RTL9600_SERIES
#undef CONFIG_RTL9600_SERIES
#endif
#endif

typedef enum rtk_rg_mac_port_idx_e
{
#if defined(CONFIG_RTL9600_SERIES) || defined(CONFIG_RTL9601B_SERIES)
	RTK_RG_MAC_PORT0=0,
	RTK_RG_MAC_PORT1,
	RTK_RG_MAC_PORT2,
	RTK_RG_MAC_PORT3,
	RTK_RG_MAC_PORT_PON,
	RTK_RG_MAC_PORT_RGMII,
	RTK_RG_MAC_PORT_CPU,
	RTK_RG_MAC_PORT_MAX,

#elif defined(CONFIG_XDSL_NEW_HWNAT_DRIVER)

	RTK_RG_MAC_PORT0=0,
	RTK_RG_MAC_PORT1=1,
	RTK_RG_MAC_PORT2=2,
	RTK_RG_MAC_PORT3=3,
	RTK_RG_MAC_PORT_PON=4,
	RTK_RG_MAC_PORT_RGMII=5,
	RTK_RG_MAC_PORT_CPU=6,
	RTK_RG_MAC_PORT_MAX,

#elif defined(CONFIG_RTL9607C_SERIES)

	RTK_RG_MAC_PORT0=0,
	RTK_RG_MAC_PORT1=1, 	
	RTK_RG_MAC_PORT2=2, 
	RTK_RG_MAC_PORT3=3,
	RTK_RG_MAC_PORT4=4,
	RTK_RG_MAC_PORT_PON=5, 
	RTK_RG_MAC_PORT_iNIC=6, 
	RTK_RG_MAC_PORT_SLAVECPU=7, 
	RTK_RG_MAC_PORT_RGMII=8, 
	RTK_RG_MAC_PORT_MASTERCPU_CORE0=9, 
	RTK_RG_MAC_PORT_MASTERCPU_CORE1=10,
	RTK_RG_MAC_PORT_MAX,

#elif defined(CONFIG_RTL9602C_SERIES)

	RTK_RG_MAC_PORT0=0,
	RTK_RG_MAC_PORT1,
	RTK_RG_MAC_PORT_PON,
	RTK_RG_MAC_PORT_CPU,
	RTK_RG_MAC_PORT_MAX,

#endif

} rtk_rg_mac_port_idx_t;

typedef enum rtk_rg_mac_ext_port_idx_e
{
#if defined(CONFIG_RTL9600_SERIES) || defined(CONFIG_RTL9601B_SERIES)

	RTK_RG_MAC_EXT_CPU=0,
	RTK_RG_MAC_EXT_PORT0=1,
	RTK_RG_MAC_EXT_PORT1=2, 	
	RTK_RG_MAC_EXT_PORT2=3, 
	RTK_RG_MAC_EXT_PORT3=4,
	RTK_RG_MAC_EXT_PORT4=5,
	RTK_RG_MAC_EXT_PORT_MAX,

#elif defined(CONFIG_XDSL_NEW_HWNAT_DRIVER)

	RTK_RG_MAC_EXT_CPU=0,
	RTK_RG_MAC_EXT_PORT0=1,
	RTK_RG_MAC_EXT_PORT1=2, 	
	RTK_RG_MAC_EXT_PORT2=3, 
	RTK_RG_MAC_EXT_PORT_MAX,

#elif defined(CONFIG_RTL9607C_SERIES)

	RTK_RG_MAC_EXT_CPU=0,
	RTK_RG_MAC_EXT_PORT0=1,
	RTK_RG_MAC_EXT_PORT1=2, 	
	RTK_RG_MAC_EXT_PORT2=3, 
	RTK_RG_MAC_EXT_PORT3=4,
	RTK_RG_MAC_EXT_PORT4=5,
	RTK_RG_MAC_EXT_PORT5=6,
	RTK_RG_MAC_EXT_PORT_MAX,

#elif defined(CONFIG_RTL9602C_SERIES)

	RTK_RG_MAC_EXT_CPU=0,
	RTK_RG_MAC_EXT_PORT0=1,
	RTK_RG_MAC_EXT_PORT1=2, 	
	RTK_RG_MAC_EXT_PORT2=3, 
	RTK_RG_MAC_EXT_PORT3=4,
	RTK_RG_MAC_EXT_PORT4=5,
	RTK_RG_MAC_EXT_PORT5=6,
	RTK_RG_MAC_EXT_PORT_MAX,

#endif

} rtk_rg_mac_ext_port_idx_t;



typedef enum rtk_rg_port_idx_e
{
#if defined(CONFIG_RTL9600_SERIES) || defined(CONFIG_RTL9601B_SERIES)

	RTK_RG_PORT0=0,
	RTK_RG_PORT1,
	RTK_RG_PORT2,
	RTK_RG_PORT3,
	RTK_RG_PORT_PON,
	RTK_RG_PORT_RGMII,
	RTK_RG_PORT_CPU,
	RTK_RG_EXT_PORT0=7,
	RTK_RG_EXT_PORT1,
	RTK_RG_EXT_PORT2,
	RTK_RG_EXT_PORT3,
	RTK_RG_EXT_PORT4,
	RTK_RG_PORT_MAX,

#elif defined(CONFIG_XDSL_NEW_HWNAT_DRIVER)

	RTK_RG_PORT0=0,
	RTK_RG_PORT1=1,
	RTK_RG_PORT2=2,
	RTK_RG_PORT3=3,
	RTK_RG_PORT_PON=4, 		//for xdsl RTK_RG_PORT_PON == WAN port
	RTK_RG_PORT_RGMII=5,
	RTK_RG_PORT_CPU=6,
	RTK_RG_EXT_PORT0=7,
	RTK_RG_EXT_PORT1=8,
	RTK_RG_EXT_PORT2=9,
	RTK_RG_PORT_MAX=10,
	
#elif defined(CONFIG_RTL9607C_SERIES)

	RTK_RG_PORT0=0,
	RTK_RG_PORT1,
	RTK_RG_PORT2,
	RTK_RG_PORT3,
	RTK_RG_PORT4,
	RTK_RG_PORT_PON=5,
	RTK_RG_PORT_iNIC,
	RTK_RG_PORT_SLAVECPU=7, 
	RTK_RG_PORT_RGMII,
	RTK_RG_PORT_MASTERCPU_CORE0=9,
	RTK_RG_PORT_MASTERCPU_CORE1=10,
	RTK_RG_EXT_PORT0=11,	// MAC9
	RTK_RG_EXT_PORT1,
	RTK_RG_EXT_PORT2,
	RTK_RG_EXT_PORT3,
	RTK_RG_EXT_PORT4,
	RTK_RG_EXT_PORT5,	
	RTK_RG_MAC10_EXT_PORT0=17,
	RTK_RG_MAC10_EXT_PORT1,
	RTK_RG_MAC10_EXT_PORT2,
	RTK_RG_MAC10_EXT_PORT3,
	RTK_RG_MAC10_EXT_PORT4,
	RTK_RG_MAC10_EXT_PORT5,
	RTK_RG_MAC7_EXT_PORT0=23,
	RTK_RG_MAC7_EXT_PORT1,
	RTK_RG_MAC7_EXT_PORT2,
	RTK_RG_MAC7_EXT_PORT3,
	RTK_RG_MAC7_EXT_PORT4,
	RTK_RG_MAC7_EXT_PORT5,
	RTK_RG_PORT_MAX=29,
		
#elif defined(CONFIG_RTL9602C_SERIES)

	RTK_RG_PORT0=0,
	RTK_RG_PORT1,
	RTK_RG_PORT_PON,
	RTK_RG_PORT_CPU,
	RTK_RG_EXT_PORT0=4,
	RTK_RG_EXT_PORT1,
	RTK_RG_EXT_PORT2,
	RTK_RG_EXT_PORT3,
	RTK_RG_EXT_PORT4,
	RTK_RG_EXT_PORT5,
	RTK_RG_PORT_MAX,

#endif
} rtk_rg_port_idx_t;

#if defined(CONFIG_XDSL_NEW_HWNAT_DRIVER)
#define RTK_RG_EXT_PORT3 9	/*xdsl useless port*/
#define RTK_RG_EXT_PORT4 9	/*xdsl useless port*/
#endif

#endif