/*
* ----------------------------------------------------------------
* Copyright c Realtek Semiconductor Corporation, 2002
* All rights reserved.
*
* $Header: /usr/local/dslrepos/linux-2.6.30/drivers/net/rtl819x/rtl865xc_swNic.h,v 1.7 2012/03/29 03:26:07 paula Exp $
*
* Abstract: Switch core polling mode NIC header file.
*
* $Author: paula $
*
* $Log: rtl865xc_swNic.h,v $
* Revision 1.7 2012/03/29 03:26:07 paula
* increase descriptor ring size
*
* Revision 1.6 2011/08/03 08:15:26 tylo
* ETH_REFILL_THRESHOLD5 should smaller than NUM_RX_PKTHDR_DESC5
*
* Revision 1.5 2011/08/02 12:11:22 tylo
* decrease rx ring size
*
* Revision 1.4 2011/07/11 09:00:05 cathy
* update NUM_TX_PKTHDR_DESC from 64 to 256 for 8192cd's throughput
*
* Revision 1.3 2011/06/16 05:53:48 ikevin362
* cpu IPQos support, change some para.
*
* Revision 1.2 2011/04/11 12:45:18 tylo
* update hw nat driver from AP team
*
* Revision 1.3 2008/04/11 10:12:38 bo_zhao
* *: swap nic drive to 8186 style
*
* Revision 1.2 2007/11/11 02:51:27 davidhsu
* Fix the bug that do not fre rx skb in rx descriptor when driver is shutdown
*
* Revision 1.1.1.1 2007/08/06 10:04:52 root
* Initial import source to CVS
*
* Revision 1.4 2006/09/15 03:53:39 ghhuang
* +: Add TFTP download support for RTL8652 FPGA
*
* Revision 1.3 2005/09/22 05:22:31 bo_zhao
* *** empty log message ***
*
* Revision 1.1.1.1 2005/09/05 12:38:24 alva
* initial import for add TFTP server
*
* Revision 1.2 2004/03/31 01:49:20 yjlou
* *: all text files are converted to UNIX format.
*
* Revision 1.1 2004/03/16 06:36:13 yjlou
* *** empty log message ***
*
* Revision 1.1.1.1 2003/09/25 08:16:56 tony
* initial loader tree
*
* Revision 1.1.1.1 2003/05/07 08:16:07 danwu
* no message
*
* ---------------------------------------------------------------
*/
#ifndef RTL865XC_SWNIC_H
#define RTL865XC_SWNIC_H
#if defined(CONFIG_RTL_HW_QOS_SUPPORT)
#define RTL_MULTIPLE_RX_TX_RING 1 /*enable multiple input queue(multiple rx ring)*/
#endif
#define RTL865X_SWNIC_RXRING_HW_PKTDESC 6
#ifdef CONFIG_RTL_8196D
#define RTL865X_SWNIC_TXRING_HW_PKTDESC 4
#else
#define RTL865X_SWNIC_TXRING_HW_PKTDESC 2
#endif
#if defined(CONFIG_RTL_8198) && !defined(CONFIG_RTL_8198_AP_ROOT)
#define MAX_PRE_ALLOC_RX_SKB 512
#define NUM_RX_PKTHDR_DESC 512
#define NUM_TX_PKTHDR_DESC 1024
#define ETH_REFILL_THRESHOLD 128 // must < NUM_RX_PKTHDR_DESC
#else
#ifdef DELAY_REFILL_ETH_RX_BUF
#if defined(CONFIG_RTL8685S) || defined(CONFIG_RTL8685SB)
#define MAX_PRE_ALLOC_RX_SKB 128 //ori=304
#else
#define MAX_PRE_ALLOC_RX_SKB 304
#endif
#ifdef CONFIG_FAST_FORWARDING
#define NUM_RX_PKTHDR_DESC 512
#else
#define NUM_RX_PKTHDR_DESC 256
#endif//end of CONFIG_FAST_FORWARDING
#define ETH_REFILL_THRESHOLD 96 // must < NUM_RX_PKTHDR_DESC
#define NUM_TX_PKTHDR_DESC 512
#else
#define MAX_PRE_ALLOC_RX_SKB 3072
#define NUM_RX_PKTHDR_DESC 1024
#define ETH_REFILL_THRESHOLD 96 // must < NUM_RX_PKTHDR_DESC
#define NUM_TX_PKTHDR_DESC 1024
#endif
#endif
#ifdef CONFIG_RTK_SWCORE_OVERWRITE_DESC_SIZE
#undef NUM_RX_PKTHDR_DESC
#undef NUM_TX_PKTHDR_DESC
#undef MAX_PRE_ALLOC_RX_SKB
#define NUM_RX_PKTHDR_DESC CONFIG_RTK_SWCORE_RX_DESC_NUM
#define NUM_TX_PKTHDR_DESC CONFIG_RTK_SWCORE_TX_DESC_NUM
#define MAX_PRE_ALLOC_RX_SKB CONFIG_RTK_SWCORE_PREALLOC_DESC_NUM
#endif
#if defined(RTL_MULTIPLE_RX_TX_RING)
//#define RTL_CPU_QOS_ENABLED 1
#define RTL865X_SWNIC_RXRING_MAX_PKTDESC 6
#define RTL865X_SWNIC_TXRING_MAX_PKTDESC 2
/* By default, only using rxring 0 and rxring 5
* in order to make different between low/high
* priority
*/
#define NUM_RX_PKTHDR_DESC1 0
#define NUM_RX_PKTHDR_DESC2 0
#define NUM_RX_PKTHDR_DESC3 0
#define NUM_RX_PKTHDR_DESC4 0
#define NUM_RX_PKTHDR_DESC5 64
#if defined(CONFIG_RTK_SKB_PRIO_ASSIGNMENT)
#define NUM_TX_PKTHDR_DESC1 128 /*NUM_TX_PKTHDR_DESC*/
#else
#define NUM_TX_PKTHDR_DESC1 8 /*NUM_TX_PKTHDR_DESC*/
#endif
#ifdef CONFIG_RTL_8196D
#define NUM_TX_PKTHDR_DESC2 2
#define NUM_TX_PKTHDR_DESC3 2
#endif
#define ETH_REFILL_THRESHOLD1 0 // must < NUM_RX_PKTHDR_DESC1
#define ETH_REFILL_THRESHOLD2 0 // must < NUM_RX_PKTHDR_DESC2
#define ETH_REFILL_THRESHOLD3 0 // must < NUM_RX_PKTHDR_DESC3
#define ETH_REFILL_THRESHOLD4 0 // must < NUM_RX_PKTHDR_DESC4
#define ETH_REFILL_THRESHOLD5 NUM_RX_PKTHDR_DESC5/2 // must < NUM_RX_PKTHDR_DESC5
#define QUEUEID0_RXRING_MAPPING 0x0000
#define QUEUEID1_RXRING_MAPPING 0x0000
#define QUEUEID2_RXRING_MAPPING 0x0000 //0x5555
#define QUEUEID3_RXRING_MAPPING 0x0000 //0x5555
#define QUEUEID4_RXRING_MAPPING 0x0000 //0x5555
#ifdef CONFIG_RTL_8685_8PRIQUE
#define QUEUEID5_RXRING_MAPPING 0x0000
#define QUEUEID6_RXRING_MAPPING 0x0000
#define QUEUEID7_RXRING_MAPPING 0x5555
#else
#define QUEUEID5_RXRING_MAPPING 0x5555
#endif
#else
#define RTL865X_SWNIC_RXRING_MAX_PKTDESC 1
#define RTL865X_SWNIC_TXRING_MAX_PKTDESC 1
#define NUM_RX_PKTHDR_DESC1 0
#define NUM_RX_PKTHDR_DESC2 0
#define NUM_RX_PKTHDR_DESC3 0
#define NUM_RX_PKTHDR_DESC4 0
#define NUM_RX_PKTHDR_DESC5 0
#define NUM_TX_PKTHDR_DESC1 4
#ifdef CONFIG_RTL_8196D
#define NUM_TX_PKTHDR_DESC2 2
#define NUM_TX_PKTHDR_DESC3 2
#endif
#define ETH_REFILL_THRESHOLD1 0 // must < NUM_RX_PKTHDR_DESC
#define ETH_REFILL_THRESHOLD2 0 // must < NUM_RX_PKTHDR_DESC
#define ETH_REFILL_THRESHOLD3 0 // must < NUM_RX_PKTHDR_DESC
#define ETH_REFILL_THRESHOLD4 0 // must < NUM_RX_PKTHDR_DESC
#define ETH_REFILL_THRESHOLD5 0 // must < NUM_RX_PKTHDR_DESC
#define QUEUEID0_RXRING_MAPPING 0
#define QUEUEID1_RXRING_MAPPING 0
#define QUEUEID2_RXRING_MAPPING 0
#define QUEUEID3_RXRING_MAPPING 0
#define QUEUEID4_RXRING_MAPPING 0
#define QUEUEID5_RXRING_MAPPING 0
#define QUEUEID6_RXRING_MAPPING 0
#define QUEUEID7_RXRING_MAPPING 0
#endif
#define RX_MULTIRING_BITMAP ((NUM_RX_PKTHDR_DESC ? 1 : 0) | (NUM_RX_PKTHDR_DESC1? 1<<1 : 0) | (NUM_RX_PKTHDR_DESC2? 1<<2 : 0) | (NUM_RX_PKTHDR_DESC3? 1<<3 : 0) | (NUM_RX_PKTHDR_DESC4? 1<<4 : 0) | (NUM_RX_PKTHDR_DESC5? 1<<5 : 0))
#define RX_ONLY_RING0 ((RX_MULTIRING_BITMAP == 1)? 1 : 0)
/* refer to rtl865xc_swNic.c & rtl865xc_swNic.h
*/
#define UNCACHE_MASK 0x20000000
/* rxPreProcess */
#define RTL8651_CPU_PORT 0x07 /* in rtl8651_tblDrv.h */
#define _RTL865XB_EXTPORTMASKS 7
/*romedriver modify Boyce 2014-07-10*/
#if defined(CONFIG_XDSL_NEW_HWNAT_DRIVER) && defined(CONFIG_XDSL_ROMEDRIVER)
//copy from fwdEngine
enum RE8670_STATUS_REGS
{
/*TX/RX share */
DescOwn = (1 << 31), /* Descriptor is owned by NIC */
RingEnd = (1 << 30), /* End of descriptor ring */
FirstFrag = (1 << 29), /* First segment of a packet */
LastFrag = (1 << 28), /* Final segment of a packet */
/*Tx descriptor opt1*/
IPCS = (1 << 27),
L4CS = (1 << 26),
KEEP = (1 << 25),
BLU = (1 << 24),
TxCRC = (1 << 23),
VSEL = (1 << 22),
DisLrn = (1 << 21),
CPUTag_ipcs = (1 << 20),
CPUTag_l4cs = (1 << 19),
/*Tx descriptor opt2*/
CPUTag = (1 << 31),
aspri = (1 << 30),
CPRI = (1 << 27),
TxVLAN_int = (0 << 25), //intact
TxVLAN_ins = (1 << 25), //insert
TxVLAN_rm = (2 << 25), //remove
TxVLAN_re = (3 << 25), //remark
//TxPPPoEAct = (1 << 23),
TxPPPoEAct = 23,
//TxPPPoEIdx = (1 << 20),
TxPPPoEIdx = 20,
Efid = (1 << 19),
//Enhan_Fid = (1 << 16),
Enhan_Fid = 16,
/*Tx descriptor opt3*/
SrcExtPort = 29,
TxDesPortM = 23,
TxDesStrID = 16,
TxDesVCM = 0,
/*Tx descriptor opt4*/
/*Rx descriptor opt1*/
CRCErr = (1 << 27),
IPV4CSF = (1 << 26),
L4CSF = (1 << 25),
RCDF = (1 << 24),
IP_FRAG = (1 << 23),
PPPoE_tag = (1 << 22),
RWT = (1 << 21),
PktType = (1 << 17),
RxProtoIP = 1,
RxProtoPPTP = 2,
RxProtoICMP = 3,
RxProtoIGMP = 4,
RxProtoTCP = 5,
RxProtoUDP = 6,
RxProtoIPv6 = 7,
RxProtoICMPv6 = 8,
RxProtoTCPv6 = 9,
RxProtoUDPv6 = 10,
L3route = (1 << 16),
OrigFormat = (1 << 15),
PCTRL = (1 << 14),
/*Rx descriptor opt2*/
PTPinCPU = (1 << 30),
SVlanTag = (1 << 29),
/*Rx descriptor opt3*/
SrcPort = (1 << 27),
DesPortM = (1 << 21),
Reason = (1 << 13),
IntPriority = (1 << 10),
ExtPortTTL = (1 << 5),
};
typedef struct dma_tx_desc {
u32 opts1;
u32 addr;
u32 opts2;
u32 opts3; //cputag
u32 opts4; //lso
}DMA_TX_DESC;
typedef struct dma_rx_desc {
u32 opts1;
u32 addr;
u32 opts2;
u32 opts3;
}DMA_RX_DESC;
struct ring_info {
struct sk_buff *skb;
dma_addr_t mapping;
unsigned frag;
};
struct cp_extra_stats {
unsigned long rx_frags;
unsigned long tx_timeouts;
//krammer add for rx info
unsigned int rx_hw_num;
unsigned int rx_sw_num;
unsigned int rer_runt;
unsigned int rer_ovf;
unsigned int rdu;
unsigned int frag;
#ifdef CONFIG_RG_JUMBO_FRAME
unsigned int toobig;
#endif
unsigned int crcerr;
unsigned int rcdf;
unsigned int rx_no_mem;
//krammer add for tx info
unsigned int tx_sw_num;
unsigned int tx_hw_num;
unsigned int tx_no_desc;
};
struct rx_info{
union{
struct{
unsigned int own:1;//31
unsigned int eor:1;//30
unsigned int fs:1;//29
unsigned int ls:1;//28
unsigned int crcerr:1;//27
unsigned int ipv4csf:1;//26
unsigned int l4csf:1;//25
unsigned int rcdf:1;//24
unsigned int ipfrag:1;//23
unsigned int pppoetag:1;//22
unsigned int rwt:1;//21
unsigned int pkttype:4;//17~20
unsigned int l3routing:1;//16
unsigned int origformat:1;//15
unsigned int pctrl:1;//14
#ifdef CONFIG_RG_JUMBO_FRAME
unsigned int data_length:14;//0~13
#else
unsigned int rsvd:2;//12~13
unsigned int data_length:12;//0~11
#endif
}bit;
unsigned int dw;//double word
}opts1;
unsigned int addr;
union{
struct{
unsigned int cputag:1;//31
unsigned int ptp_in_cpu_tag_exist:1;//30
unsigned int svlan_tag_exist:1;//29
unsigned int rsvd_2:2;//27~28
unsigned int pon_stream_id:7;//20~26
unsigned int rsvd_1:3;//17~19
unsigned int ctagva:1;//16
unsigned int cvlan_tag:16;//0~15
}bit;
unsigned int dw;//double word
}opts2;
union{
struct{
unsigned int src_port_num:5;//27~31
unsigned int dst_port_mask:6;//21~26
unsigned int reason:8;//13~20
unsigned int internal_priority:3;//10~12
unsigned int ext_port_ttl_1:5;//5~9
unsigned int rsvd:5;//0~4
}bit;
unsigned int dw;//double word
}opts3;
};
struct tx_info{
union{
struct{
unsigned int own:1;//31
unsigned int eor:1;//30
unsigned int fs:1;//29
unsigned int ls:1;//28
unsigned int ipcs:1;//27
unsigned int l4cs:1;//26
unsigned int keep:1;//25
unsigned int blu:1;//24
unsigned int crc:1;//23
unsigned int vsel:1;//22
unsigned int dislrn:1;//21
unsigned int cputag_ipcs:1;//20
unsigned int cputag_l4cs:1;//19
unsigned int cputag_psel:1;//18
unsigned int rsvd:1;//17
unsigned int data_length:17;//0~16
}bit;
unsigned int dw;//double word
}opts1;
unsigned int addr;
union{
struct{
unsigned int cputag:1;//31
unsigned int aspri:1;//30
unsigned int cputag_pri:3;//27~29
unsigned int tx_vlan_action:2;//25~26
unsigned int tx_pppoe_action:2;//23~24
unsigned int tx_pppoe_idx:3;//20~22
unsigned int efid:1;//19
unsigned int enhance_fid:3;//16~18
unsigned int vidl:8;//8~15
unsigned int prio:3;//5~7
unsigned int cfi:1;// 4
unsigned int vidh:4;//0~3
}bit;
unsigned int dw;//double word
}opts2;
union{
struct{
unsigned int extspa:3;//29~31
unsigned int tx_portmask:6;//23~28
unsigned int tx_dst_stream_id:7;//16~22
#if 0//def RTL0371
unsigned int tx_dst_vc_mask:16;//0~15
#else
unsigned int rsvd:12;// 4~15
unsigned int rsv1:1;// 3
unsigned int rsv0:1;// 2
unsigned int l34_keep:1;// 1
unsigned int ptp:1;//0
#endif
}bit;
unsigned int dw;//double word
}opts3;
union{
unsigned int dw;
}opts4;
};
#define MAX_RXRING_NUM 6
#define MAX_TXRING_NUM 5
#define SW_PORT_NUM 7
struct re_private {
void *regs;
struct net_device *dev;
spinlock_t lock;
DMA_RX_DESC *rx_Mring[MAX_RXRING_NUM];
unsigned rx_Mtail[MAX_RXRING_NUM];
char* rxdesc_Mbuf[MAX_RXRING_NUM];
DMA_TX_DESC *tx_Mhqring[MAX_TXRING_NUM];
char* txdesc_Mbuf[MAX_TXRING_NUM];
unsigned tx_Mhqhead[MAX_TXRING_NUM];
unsigned tx_Mhqtail[MAX_TXRING_NUM];
struct ring_info *tx_skb[MAX_TXRING_NUM];
struct ring_info *rx_skb[MAX_RXRING_NUM];
#ifdef CONFIG_DUALBAND_CONCURRENT
DMA_RX_DESC *default_rx_desc;
char *default_rxdesc_Mbuf;
struct ring_info *default_rx_skb;
unsigned old_tx_Mhqhead[MAX_TXRING_NUM];
unsigned old_tx_Mhqtail[MAX_TXRING_NUM];
unsigned old_rx_Mtail[MAX_RXRING_NUM];
#endif
unsigned rx_buf_sz;
dma_addr_t ring_dma;
u32 msg_enable;
struct cp_extra_stats cp_stats;
u32 isr_status;
u32 isr1_status;
struct pci_dev *pdev;
u32 rx_config;
struct sk_buff *frag_skb;
unsigned dropping_frag : 1;
//struct tq_struct rx_task;
//struct tq_struct tx_task;
struct tasklet_struct rx_tasklets;
//struct tasklet_struct tx_tasklets;
#if 1
struct tasklet_struct tx_tasklets;
#endif
struct net_device* port2dev[SW_PORT_NUM];
int (*port2rxfunc[SW_PORT_NUM])(struct re_private *cp, struct sk_buff *skb, struct rx_info *pRxInfo);
#ifdef CONFIG_RG_SIMPLE_PROTOCOL_STACK
struct net_device* multiWanDev[8]; //at most 7 WAN interface(reserved one interface for WAN)
int wanInterfaceIdx; //used for multi-WAN in SPS
#endif
#ifdef CONFIG_RG_JUMBO_FRAME
struct sk_buff *jumboFrame;
unsigned short jumboLength;
#endif
};
#endif //end CONFIG_XDSL_NEW_HWNAT_DRIVER
typedef struct {
uint16 vid;
uint16 pid;
uint16 len;
uint16 priority:3;
uint16 rxPri:3;
uint16 rxExtspa:2;
uint16 dpext:4;
uint16 rxOrg:1;
uint16 rxFwd:1;
void* input;
struct dev_priv* priv;
/*romedriver modify Boyce 2014-07-10*/
#if defined(CONFIG_XDSL_NEW_HWNAT_DRIVER) && defined(CONFIG_XDSL_ROMEDRIVER)
struct rx_info RxInfo;
#endif
uint32 isPdev;
} rtl_nicRx_info;
typedef struct {
uint16 vid;
uint16 portlist;
uint16 srcExtPort;
uint16 flags;
uint32 txIdx:1;
#if defined(CONFIG_RTL_HW_QOS_SUPPORT)
uint32 priority:3;
uint32 queueId:3;
#endif
#if defined(CONFIG_RTL_8685S_HWNAT)
uint32 _priority:3; //same as CONFIG_RTL_HW_QOS_SUPPORT priority,vlan priority
uint32 _queueId:3; //same as CONFIG_RTL_HW_QOS_SUPPORT queueId,tx queue id
uint32 CPUqueueId:3;
uint16 replaceTxDesc:1;
uint16 pktType:3;
uint16 vlanTagged: 1; /* the tag status after ALE */
uint16 llcTagged: 1; /* the tag status after ALE */
uint16 pppeTagged: 1; /* the tag status after ALE */
uint16 pppoeIdx: 3;
uint16 l3v4v6HdrFlag:3; //v4FIRST|v4HDR_FLAG|v6HDR_FLAG
uint16 v6HdrLen;
uint32 txCVlanTagAutoAdd; //port0-prot5 mask
#endif
#if defined(CONFIG_XDSL_NEW_HWNAT_DRIVER) && defined(CONFIG_XDSL_ROMEDRIVER)
uint16 fromRomeDriver;
struct tx_info* ptxInfo;
#endif
void *out_skb;
} rtl_nicTx_info;
#if defined(RTL_CPU_QOS_ENABLED)
#define RTL_NIC_QUEUE_LEN (32)
#define RTL_CPUQOS_TIMER_INTERVAL (HZ<<1)
#define RTL_CPUQOS_PKTCNT_THRESHOLD (1000)
#define RTL_ASSIGN_RX_PRIORITY ((highestPriority<cpuQosHoldLow)?((totalLowQueueCnt<RTL_CPUQOS_PKTCNT_THRESHOLD)?highestPriority:cpuQosHoldLow):highestPriority)
typedef struct {
int cnt;
int start;
int end;
rtl_nicRx_info entry[RTL_NIC_QUEUE_LEN];
} rtl_queue_entry;
#else
#define RTL_ASSIGN_RX_PRIORITY 0
#endif
/* --------------------------------------------------------------------
* ROUTINE NAME - swNic_init
* --------------------------------------------------------------------
* FUNCTION: This service initializes the switch NIC.
* INPUT :
userNeedRxPkthdrRingCnt[RTL865X_SWNIC_RXRING_MAX_PKTDESC]: Number of Rx pkthdr descriptors. of each ring
userNeedRxMbufRingCnt: Number of Rx mbuf descriptors.
userNeedTxPkthdrRingCnt[RTL865X_SWNIC_TXRING_MAX_PKTDESC]: Number of Tx pkthdr descriptors. of each ring
clusterSize: Size of a mbuf cluster.
* OUTPUT : None.
* RETURN : Upon successful completion, the function returns ENOERR.
Otherwise,
EINVAL: Invalid argument.
* NOTE : None.
* -------------------------------------------------------------------*/
int32 swNic_init(uint32 userNeedRxPkthdrRingCnt[],
uint32 userNeedRxMbufRingCnt,
uint32 userNeedTxPkthdrRingCnt[],
uint32 clusterSize);
/* --------------------------------------------------------------------
* ROUTINE NAME - swNic_intHandler
* --------------------------------------------------------------------
* FUNCTION: This function is the NIC interrupt handler.
* INPUT :
intPending: Pending interrupts.
* OUTPUT : None.
* RETURN : None.
* NOTE : None.
* -------------------------------------------------------------------*/
void swNic_intHandler(uint32 intPending);
int32 swNic_flushRxRingByPriority(int priority);
int32 swNic_receive(rtl_nicRx_info *info);
int32 swNic_send(void *skb, void * output, uint32 len, rtl_nicTx_info *nicTx);
//__MIPS16
int32 swNic_txDone(int idx);
void swNic_freeRxBuf(void);
int32 swNic_txRunout(void);
#if 0
int32 arpTableDump(void);
int32 arpTableDelete(void);
#endif
#ifdef DELAY_REFILL_ETH_RX_BUF
extern int return_to_rx_pkthdr_ring(unsigned char *head);
#endif
//extern uint32* rxMbufRing;
extern unsigned char *alloc_rx_buf(void **skb, int buflen);
extern void free_rx_buf(void *skb);
extern void tx_done_callback(void *skb);
extern void eth_save_and_cli(unsigned long *flags);
extern void eth_restore_flags(unsigned long flags);
#define RTL8651_IOCTL_GETWANLINKSTATUS 2000
#define RTL8651_IOCTL_GETLANLINKSTATUS 2001
#define RTL8651_IOCTL_GETWANTHROUGHPUT 2002
#define RTL8651_IOCTL_GETLANPORTLINKSTATUS 2003
#define RTL8651_IOCTL_GETWANPORTLINKSTATUS 2004
#define RTL8651_IOCTL_GETWANLINKSPEED 2100
//#define RTL8651_IOCTL_SETWANLINKSPEED 2101
#define RTL8651_IOCTL_GETLANLINKSTATUSALL 2105
#define RTL8651_IOCTL_SETWANLINKSTATUS 2200
#define RTL_NICRX_OK 0
#define RTL_NICRX_REPEAT -2
#define RTL_NICRX_NULL -1
#ifdef CONFIG_FAST_FORWARDING
#define RTL_NICRX_FF -3
#endif//end of CONFIG_FAST_FORWARDING
#if defined(CONFIG_RTL_PROC_DEBUG)
int32 rtl_dumpRxRing(void);
int32 rtl_dumpTxRing(void);
int32 rtl_dumpMbufRing(void);
#endif
struct ring_que {
int qlen;
int qmax;
int head;
int tail;
struct sk_buff **ring;
};
static inline void *UNCACHED_MALLOC(int size)
{
printk("Warning: \n"); dump_stack();
return ((void *)(((uint32)kmalloc(size, GFP_ATOMIC)) | UNCACHE_MASK));
}
static inline void *CACHED_MALLOC(int size)
{
return ((void *)(((uint32)kmalloc(size, GFP_ATOMIC))));
}
struct qos_mark2prio_s {
int en;
u32 mark;
u32 mask;
int prio; // 0-5
};
void sw_qos_mark2prio_set_enable(int en);
void sw_qos_mark2prio_get_enable(int *en);
int sw_qos_add_mark2prio(u32 mark, u32 mask, int prio);
int sw_qos_del_mark2prio(int index);
int sw_qos_get_mark2prio(int index, struct qos_mark2prio_s *m);
#endif /* _SWNIC_H */