/*
 *	PTM Registers definition
 */
#ifndef _PTM_REGS_H_
#define _PTM_REGS_H_

/* Registers definition */
enum PTM_MODULE_REGS
{
	/* System Registers */
	WCR = 0x0,
		Mode_Sel_Mask = (1<<0),
		Mode1_Sel = (0<<0),  /* PHY mode */
		Mode2_Sel = (1<<0),  /* Router mode */
		Qmap_at_stag_tx = (1<<1),
		Qmap_at_stag_rx = (1<<2),
		RXRESB = (1<<6),
		TXRESB = (1<<7),
	TTRL = 0x1,
	Stag_type_val = 0x4,
	Dummy_vid = 0x6,
	
	EntryValid_ADDR = 0xc,
	EntryMAC_ADDR = 0x10,
	CTag_ADDR = 0x40,
	STag_ADDR = 0x50,
	QMap_ADDR = 0x60,
	
	Entry_tx_pkt_cnt = 0x80,
	Entry_rx_pkt_cnt = 0xa0,
	Entry_tx_byte_cnt = 0xc0,
	Entry_rx_byte_cnt = 0xe0,

	SRestReg	 = 0x1c4,
		srstn = (1<<0),
	PCR 	= 0x1c8,
		TC_SYNC_LC = (1<<0),
		HDLC_MODE = (1<<1),
		EFM64BPE = (1<<2),
		EFM64BSP = (1<<3),
		TY_SYNC_F0 = (1<<4),
		TY_SYNC_F1 = (1<<5),
		TY_SYNC_F2 = (1<<6),
		TY_SYNC_F3 = (1<<7),
		TY_SYNC_S0 = (1<<8),
		TY_SYNC_S1 = (1<<9),
		TY_SYNC_S2 = (1<<10),
		TY_SYNC_S3 = (1<<11),	
		rxutp_clav_ext_en = (1<<12),	
		rxutp_clav_en = (1<<13),	
		txutp_clav_ext_en = (1<<14),	
		txutp_clav_en = (1<<15),	

	/* TC counter */
	TCTX_PKT = 0x1cc,
	TCRX_PKT = 0x1d0,
	TCRX_GPKT = 0x1d4,
	TCRX_BPKT = 0x1d8,
	TCRX_IPKT = 0x1dc,



	/* TX PTMx Total Codeword/Frame counter */
	TX_TOTAL_CF_P0 = 0x0220,
	TX_TOTAL_CF_P1 = 0x0224,
	TX_TOTAL_CF_P2 = 0x0228,
	TX_TOTAL_CF_P3 = 0x022c,
	TX_TOTAL_CF_P4 = 0x0230,
	TX_TOTAL_CF_P5 = 0x0234,
	TX_TOTAL_CF_P6 = 0x0238,
	TX_TOTAL_CF_P7 = 0x023c,

	/* TX PTMx Data Codeword/Frame counter */
	TX_DATA_CF_P0 = 0x0240,
	TX_DATA_CF_P1 = 0x0244,
	TX_DATA_CF_P2 = 0x0248,
	TX_DATA_CF_P3 = 0x024c,
	TX_DATA_CF_P4 = 0x0250,
	TX_DATA_CF_P5 = 0x0254,
	TX_DATA_CF_P6 = 0x0258,
	TX_DATA_CF_P7 = 0x025c,

	/* Total non-short packet counter */
	RX_HF_TPKT = 0x0260,
	RX_HS_TPKT = 0x0264,
	RX_LF_TPKT = 0x0268,
	RX_LS_TPKT = 0x026c,

	/* Total short packet counter */
	RX_HF_TPKT_SHT = 0x0270,
	RX_HS_TPKT_SHT = 0x0274,
	RX_LF_TPKT_SHT = 0x0278,
	RX_LS_TPKT_SHT = 0x027c,

	/* Rx total codeword/fragment counter */
	RX_DPKT_PTM0 = 0x02b0,
	RX_DPKT_PTM2 = 0x02b4,

	/* Rx PTMx codeword/fragment counter */
	RX_TPKT_PTM0 = 0x02b8,
	RX_TPKT_PTM1 = 0x02bc,
	RX_TPKT_PTM2 = 0x02c0,
	RX_TPKT_PTM3 = 0x02c4,
	RX_TPKT_PTM4 = 0x02c8,
	RX_TPKT_PTM5 = 0x02cc,
	RX_TPKT_PTM6 = 0x02d0,
	RX_TPKT_PTM7 = 0x02d4,
	RX_TPKT_PTM8 = 0x02d8,
	RX_TPKT_PTM9 = 0x02dc,
	RX_TPKT_PTM10 = 0x02e0,
	RX_TPKT_PTM11 = 0x02e4,
	RX_TPKT_PTM12 = 0x02e8,
	RX_TPKT_PTM13 = 0x02ec,
	RX_TPKT_PTM14 = 0x02f0,
	RX_TPKT_PTM15 = 0x02f4,

};

enum PTM_BONDING_REGS
{
	BOND_FRAG_LF = 0x1060,
	BD_SLV_NUM = 0x10d0,
	BD_TIMEOUT = 0x10d4,
	
};

enum PTM_DEBUG_REGS
{
	Debug_Sel = 0x1064,
		Update_en_tx = (1<<9),
		Update_en_rx = (1<<8),
		Enable_LS_flow = (1<<6),
		Enable_LF_flow = (1<<5),
};

enum PTM_ERROR_REGS
{
	/* CRC16 error packet counter */
	RX_CRC_ERR_HF = 0x0280,
	RX_CRC_ERR_HS = 0x0284,
	RX_CRC_ERR_LF = 0x0288,
	RX_CRC_ERR_LS = 0x028c,

	/* CRC16 error short-packet counter */
	RX_CRC_ERR_HF_SHT = 0x0290,
	RX_CRC_ERR_HS_SHT = 0x0294,
	RX_CRC_ERR_LF_SHT = 0x0298,
	RX_CRC_ERR_LS_SHT = 0x029c,	

	/* Rx Invlaid Frame */
	HDLC_INVLD_F	= 0x02a0,
	HDLC_INVLD_S	= 0x02a4,

	/* Rx coding Error */
	TC_CODING_ERR_F	= 0x02a8,
	TC_CODING_ERR_S	= 0x02ac,

};


enum PTM_UTPQOS_REGS
{
	UTP_APR32_F  = 0x1070,
	UTP_APR10_F  = 0x1074,
	UTP_APR32_S  = 0x1078,
	UTP_APR10_S  = 0x107c,
	UTP_APR_ALL  = 0x1080,
	UTP_WEIGHT_F = 0x1084,
	UTP_WEIGHT_S = 0x1088,
	UTP_QOS_MIS  = 0x108c,

	UTP_F0_ACC_INTERVAL = 0x1090,
	UTP_F1_ACC_INTERVAL = 0x1094,
	UTP_F2_ACC_INTERVAL = 0x1098,
	UTP_F3_ACC_INTERVAL = 0x109c,
	UTP_S0_ACC_INTERVAL = 0x10a0,
	UTP_S1_ACC_INTERVAL = 0x10a4,
	UTP_S2_ACC_INTERVAL = 0x10a8,
	UTP_S3_ACC_INTERVAL = 0x10ac,

	UTP_F0_ACC = 0x10b0,
	UTP_F1_ACC = 0x10b4,
	UTP_F2_ACC = 0x10b8,
	UTP_F3_ACC = 0x10bc,
	UTP_S0_ACC = 0x10c0,
	UTP_S1_ACC = 0x10c4,
	UTP_S2_ACC = 0x10c8,
	UTP_S3_ACC = 0x10cc,	
};



//#define PTM_PRI_NUM 8

#endif