--- zzzz-none-000/linux-3.18.24/arch/mips/kernel/cevt-r4k.c	2015-10-31 20:39:51.000000000 +0000
+++ rtl96-5690pro-762/linux-3.18.24/arch/mips/kernel/cevt-r4k.c	2024-08-14 08:36:36.000000000 +0000
@@ -16,6 +16,15 @@
 #include <asm/cevt-r4k.h>
 #include <asm/gic.h>
 
+static int plat_qemu;
+
+static int __init setup_qemu(char *s)
+{
+	plat_qemu = 1;
+	return 1;
+}
+__setup("qemu", setup_qemu);
+
 static int mips_next_event(unsigned long delta,
 			   struct clock_event_device *evt)
 {
@@ -50,22 +59,26 @@
 	 * performance counter interrupt was pending, so we have to run
 	 * the performance counter interrupt handler anyway.
 	 */
+#ifndef CONFIG_CPU_RLX
 	if (handle_perf_irq(r2))
 		goto out;
+#endif
 
 	/*
 	 * The same applies to performance counter interrupts.	But with the
 	 * above we now know that the reason we got here must be a timer
 	 * interrupt.  Being the paranoiacs we are we check anyway.
 	 */
-	if (!r2 || (read_c0_cause() & (1 << 30))) {
+	if (!r2 || (read_c0_cause() & (1 << CAUSEB_TI))) {
 		/* Clear Count/Compare Interrupt */
 		write_c0_compare(read_c0_compare());
 		cd = &per_cpu(mips_clockevent_device, cpu);
 		cd->event_handler(cd);
 	}
 
+#ifndef CONFIG_CPU_RLX
 out:
+#endif
 	return IRQ_HANDLED;
 }
 
@@ -89,7 +102,7 @@
 	if (cpu_has_veic)
 		return gic_get_timer_pending();
 #endif
-	return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
+	return (read_c0_cause() & (1 << CAUSEB_TI));
 }
 
 /*
@@ -108,6 +121,9 @@
     return 1;
 #endif
 
+	if (plat_qemu)
+		return 1;
+
 	/*
 	 * IP7 already pending?	 Try to clear it by acking the timer.
 	 */