/*
 * Jeff Harrell, jharrell@ti.com
 * Copyright (C) 2001 Texas Instruments, Inc.  All rights reserved.
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * Texas Instruments Sangam specific setup.
 */
#include <linux/config.h>
#include <asm/reboot.h>
#include <asm/avalanche/avalanche_map.h>
#include <asm/mips-boards/prom.h>
 
/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
#if defined (CONFIG_MIPS_AVALANCHE_VLYNQ) || defined (CONFIG_MIPS_AVALANCHE_VLYNQ_MODULE)
extern REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl;
#endif /*--- #if defined (CONFIG_MIPS_AVALANCHE_VLYNQ) || defined (CONFIG_MIPS_AVALANCHE_VLYNQ_MODULE) ---*/

extern SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn;


#define AUTO_MDIX_ENABLE_PIN        30
#define MDIX_NORMAL_MODE            0

#define AUTO_MDIX_GPIO_PIN          28
#define MDIX_MODE                   1
#define MDI_MODE                    0

#define AUTO_MDIX_CNTL_MASK        ( (1 << AUTO_MDIX_ENABLE_PIN) \
                                    |(1 << AUTO_MDIX_GPIO_PIN))
/* We ignore MDIX_NORMAL_MODE as it is 0 and we get to set 0 from the below 
   macros for the AUTO_MDIX_ENABLE_PIN. */
#define AUTO_MDIX_ON_WORD          (MDIX_MODE << AUTO_MDIX_GPIO_PIN)
#define AUTO_MDIX_OFF_WORD         (MDI_MODE << AUTO_MDIX_GPIO_PIN) 

int sangam_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
{
    if((!p_set_mdix_on_chip_fn) || (base_addr != AVALANCHE_LOW_CPMAC_BASE))
        return (-1);

    if(operation)
        /* 0perating on bit 29 and 30. Writing 1 to bit 29 and 0 to bit 30. */
        avalanche_gpio_out_value(AUTO_MDIX_ON_WORD, AUTO_MDIX_CNTL_MASK,0);
    else
        /* 0perating on bit 29 and 30. Writing 0 to bit 29 and 0 to bit 30. */
        avalanche_gpio_out_value(AUTO_MDIX_OFF_WORD, AUTO_MDIX_CNTL_MASK,0);

    return (0); 
}

/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
int avalanche_need(enum _avalanche_need_ need) {
    static char *HWRevision = NULL;
    static char *AutoMDIX = NULL;
    if(HWRevision == NULL) {
        HWRevision = prom_getenv("HWRevision");
        prom_printf("HWRevision=\"%s\"\n", HWRevision ? HWRevision : "<unknown>");
    }
    if(AutoMDIX == NULL) {
        AutoMDIX = prom_getenv("AutoMDIX");
        prom_printf("AutoMDIX=\"%s\"\n", AutoMDIX ? AutoMDIX : "<unknown>");
    }

    if(HWRevision == NULL) {
        return 0;
    }
    switch(need) {
        case avalanche_need_vlynq:
            if((HWRevision[0] == '6' && HWRevision[1] == '0') ||  /*--- Fritz Box SL WLAN Annex B ---*/
               (HWRevision[0] == '6' && HWRevision[1] == '1') ||  /*--- Fritz Box FON WLAN Annex B ---*/
               (HWRevision[0] == '6' && HWRevision[1] == '5') ||  /*--- Fritz Box SL WLAN Annex A ---*/
               (HWRevision[0] == '6' && HWRevision[1] == '6')) {  /*--- Fritz Box FON WLAN Annex A ---*/
                return 1;
            }
            break;
        case avalanche_need_auto_mdix:
            if((HWRevision[0] == '6' && HWRevision[1] == '0') ||  /*--- Fritz Box SL WLAN Annex B ---*/
               (HWRevision[0] == '6' && HWRevision[1] == '1') ||  /*--- Fritz Box FON WLAN Annex B ---*/
               (HWRevision[0] == '6' && HWRevision[1] == '5') ||  /*--- Fritz Box SL WLAN Annex A ---*/
               (HWRevision[0] == '6' && HWRevision[1] == '6') ||  /*--- Fritz Box FON WLAN Annex A ---*/
               (HWRevision[0] == '7' && HWRevision[1] == '1')) {  /*--- Fritz Box FON ATA ---*/
                return 1;
            }
            if(AutoMDIX && (AutoMDIX[0] == 'y')) {
                return 1;
            }
            break;
    }
    return 0;
}

/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
#if defined (CONFIG_MIPS_AVALANCHE_VLYNQ)
void avalanche_soc_platform_init_vlynq(void) {
    if(avalanche_need(avalanche_need_vlynq)) {
        p_remote_vlynq_dev_reset_ctrl = remote_vlynq_dev_reset_ctrl;
        vlynq_dev_init();
    }
}
#endif /*--- #if defined (CONFIG_MIPS_AVALANCHE_VLYNQ) ---*/

/*------------------------------------------------------------------------------------------*\
\*------------------------------------------------------------------------------------------*/
void avalanche_soc_platform_init(void)
{

    /* GPIO INIT */
    avalanche_gpio_init();
    
    avalanche_reset_ctrl(AVALANCHE_UART0_RESET_BIT, OUT_OF_RESET);
    avalanche_reset_ctrl(AVALANCHE_GPIO_RESET_BIT, OUT_OF_RESET);

//    avalanche_gpio_out_value(0xf3fc3ff0, 0xf3fc3ff0, 0);
    /* hack for now, to be cleaned up. */
    *(unsigned int *)0xa861090c = 0xf3fc3ff0;

//    REG32_WRITE(TNETD73XX_GPIOENR, 0xf3fc3ff0);

    avalanche_reset_ctrl(AVALANCHE_LOW_EPHY_RESET_BIT,IN_RESET);

//#if (!defined(CONFIG_MIPS_AR7WRD) && !defined(CONFIG_MIPS_AR7VWI))
#if (!defined(CONFIG_MIPS_AVALANCHE_MARVELL))
    avalanche_reset_ctrl(AVALANCHE_LOW_EPHY_RESET_BIT,OUT_OF_RESET);
#endif

                                                                                       
    /* CLK CTRl INIT */                                                                
    avalanche_clkc_init(AFECLK_FREQ, REFCLK_FREQ, OSC3_FREQ);                   


   /* initialize vbus frequency */
    avalanche_set_vbus_freq(avalanche_clkc_get_freq(CLKC_VBUS));

	/* This initialization is required to make the kernel work with ADAM2. */
	{
    volatile unsigned long *reset_cntl = AVALANCHE_RESET_CONTROL_BASE, *mdio_cntl  = ((int)AVALANCHE_MDIO_BASE + 0x4);		
		printk ("DEBUG: Bring MDIO out of reset.\n");

   *reset_cntl |= (1 << AVALANCHE_MDIO_RESET_BIT) | (1 << AVALANCHE_LOW_CPMAC_RESET_BIT) | (1 << AVALANCHE_HIGH_CPMAC_RESET_BIT) | (1 << AVALANCHE_LOW_EPHY_RESET_BIT);                                 
    *mdio_cntl   = (1 << 30) | (avalanche_get_vbus_freq()/2200000);    
	}

    /* Takes care of the CVR bug in the Sangam Chip as well. */
    if(((*(volatile unsigned int*) AVALANCHE_CVR) == 0x570005) ||
       ((*(volatile unsigned int*) AVALANCHE_CVR  == 0x200005))) {
        prom_printf("This SOC has MDIX cababilities on chip: ");
        if(avalanche_need(avalanche_need_auto_mdix)) {
            p_set_mdix_on_chip_fn = &sangam_set_mdix_on_chip;

            avalanche_gpio_ctrl(AUTO_MDIX_ENABLE_PIN, GPIO_PIN, GPIO_OUTPUT_PIN);
            avalanche_gpio_ctrl(AUTO_MDIX_GPIO_PIN, GPIO_PIN, GPIO_OUTPUT_PIN);
            prom_printf("MDIX enabled.\n");
        } else {
            prom_printf("MDIX disabled.\n");
        }

    } 
   
#if defined (CONFIG_MIPS_AVALANCHE_VLYNQ)
    avalanche_soc_platform_init_vlynq();
#endif
}