/*-------------------------------------------------------------------------------------*\ $Id: iom.c 1.18 2003/09/22 11:35:40Z mpommerenke Exp $ $Log: iom.c $ Revision 1.18 2003/09/22 11:35:40Z mpommerenke Revision 1.17 2003/07/17 11:58:08Z mbahr Behebung von Localbufferoverflow bei parallelem DSL & ISDN Revision 1.16 2003/06/27 12:13:58Z mbahr ISDN-Version passt Revision 1.15 2003/06/02 14:52:40Z mpommerenke Revision 1.14 2003/06/02 14:52:03Z mpommerenke Revision 1.13 2003/05/15 14:54:38Z mpommerenke Revision 1.12 2003/05/14 11:43:20Z mpommerenke Revision 1.11 2003/05/07 14:42:42Z mpommerenke Revision 1.10 2003/04/08 12:33:01Z mpommerenke Revision 1.9 2003/03/11 14:52:04Z mpommerenke Revision 1.8 2003/02/20 10:38:35Z mpommerenke Revision 1.7 2003/02/19 16:28:02Z mpommerenke Revision 1.6 2003/02/19 15:49:18Z mpommerenke Revision 1.5 2003/02/19 11:58:26Z mpommerenke Revision 1.4 2003/02/12 12:12:11Z mpommerenke Revision 1.3 2003/02/05 13:54:39Z mpommerenke Revision 1.2 2003/01/29 15:12:43Z mpommerenke Revision 1.1 2003/01/29 11:10:42Z mpommerenke Initial revision Revision 1.1 2003/01/24 11:26:30Z mpommerenke Initial revision Revision 1.1 2002/10/22 15:05:41Z mpommerenke Initial revision \*-------------------------------------------------------------------------------------*/ #include "raptor.h" #include "string.h" #include "debug.h" #include "mcbsp.h" #include "irq.h" #include "c6205_prot.h" #include "c6205_load.h" #include "link.h" #include "dma.h" #include "iom.h" #include "ipacx.h" #include "sbc.h" #include "timer.h" #include "eeprom.h" #define LINK_INTERNAL #include "link.h" #if 0 /*-------------------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------------------*/ void iom_memcpy(unsigned short *Dest, unsigned short *Source, unsigned int ShortCount) { while(ShortCount--) *Dest++ = *Source++; } /*-------------------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------------------*/ void iom__memset(unsigned int *Dest, unsigned int Value, unsigned int WordCount) { while(WordCount--) *Dest++ = Value; } #else /*-------------------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------------------*/ #define iom_memcpy _memcpy #define iom__memset __memset #endif /*-------------------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------------------*/ far struct _iom_data IOM_Data[2][2][IOM_SAMPLE_SIZE]; unsigned char IOM_Data_Index; unsigned char IOM_Init_Done; unsigned char IOM_BKanal_Open; unsigned int IOM_DMA_Disable; unsigned int IOM_McBSP_Disable; unsigned int IOM_Irq_Handle; #if !defined(NDEBUG) unsigned int IOM_Irq_Frame_Count, IOM_TxUnderrun, IOM_Irq_Overrun_Count; #endif /*--- #if !defined(NDEBUG) ---*/ far const struct _iom_data IOM_Ruhe_Frame = { 0xFF, 0xFF, 0xFF, 0x03, _SBC_AR10_CMD, 0x01, 0x01 }; far const struct _iom_short_data IOM_Short_Ruhe_Frame = { /*--- 0x01, 0x01, 0x09, 0x03, ---*/ /*--- 0x01, 0x01, 0x09, 0x03, ---*/ /*--- 0x01, 0x01, 0x09, 0x03, ---*/ /*--- 0x01, 0x01, 0x09, 0x03 ---*/ 0x01, 0x01, _SBC_DIU_CMD, 0x03, 0x01, 0x01, _SBC_DIU_CMD, 0x03, 0x01, 0x01, _SBC_DIU_CMD, 0x03, 0x01, 0x01, _SBC_DIU_CMD, 0x03 }; /*-------------------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------------------*/ volatile unsigned int IOM_Delay_Value; #pragma CODE_SECTION(IOM_Delay, ".code_overlay_4"); void IOM_Delay(unsigned int mSec) { /*--- TIME_STAMP läuft mit CPU_CLK / 4 ==> 13,5µs pro takt ---*/ /*--- signed int LastCount; ---*/ /*--- mSec *= 13500; ---*/ /*--- LastCount = (signed int)TIME_STAMP() + mSec; ---*/ /*--- while((LastCount - (signed int)TIME_STAMP()) > 0) ---*/ /*--- ; ---*/ mSec *= 100000; for( ; mSec-- ; ) IOM_Delay_Value = mSec; } /*-------------------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------------------*/ #pragma CODE_SECTION(IOM_Init, ".code_overlay_4"); void IOM_Init(void) { GPIO(ISAC_RESET, GPIO_HIGH); IOM_Delay(1); IOM_Irq_Handle = Irq_Set(DMA_INT1, USE_IOM_IRQ, IOM_Irq); *(IPACX_SRES(0)) = SRES_RES_CI | SRES_RES_BCHA | SRES_RES_BCHB | SRES_RES_MON | SRES_RES_DCH | SRES_RES_IOM | SRES_RES_TR | SRES_RES_RSTO; IOM_Delay(1); *(IPACX_MASK(0)) = MASK_ICA | MASK_ICB | MASK_ST | MASK_CIC | MASK_AUX | MASK_TRAN | MASK_MOS | MASK_ICD; *(IPACX_MASKD(0)) = MASKD_RME | MASKD_RPF | MASKD_RFO | MASKD_XPR | MASKD_XMR | MASKD_XDU; *(IPACX_MASKTR(0)) = MASKTR_LD | MASKTR_RIC | MASKTR_SQC | MASKTR_SQW; *(IPACX_TR_CONF0(0)) = 0x00; *(IPACX_TR_CONF2(0)) = 0x00; *(IPACX_DCI_CR(0)) = DCI_CR_DPS_CI1; *(IPACX_MODE2(0)) = 0x00; *(IPACX_MODED(0)) = MODED_DIM0; *(IPACX_CIX0(0)) = CIX0_CODX(_SBC_RS_CMD) | CIX0_TBA2 | CIX0_TBA1 | CIX0_TBA0 | CIX0_BAC; IOM_Delay(1); *(IPACX_CIX0(0)) = CIX0_CODX(_SBC_TIM_CMD) | CIX0_TBA2 | CIX0_TBA1 | CIX0_TBA0 | CIX0_BAC; IOM_Delay(1); *(IPACX_CIX0(0)) = CIX0_CODX(_SBC_DIU_CMD) | CIX0_TBA2 | CIX0_TBA1 | CIX0_TBA0; *(IPACX_IOM_CR(0)) = IOM_CR_TIC_DIS | IOM_CR_EN_BCL; /*--- disable TIC, enable BCL ---*/ /*---------------------------------------------------------------------------------*\ The serial port is configured and initialized via the serial-port control register (SPCR): \*---------------------------------------------------------------------------------*/ IOM_McBSP_Disable = McBSP[IOM_McBSP]->MCBSP_SPCR_ADDR.Register = ( /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- MCBSP_SPCR_FRST_YES | ---*/ MCBSP_SPCR_FRST_NO | 0 ) << _MCBSP_SPCR_FRST_SHIFT) | /*-------------------------------------------------------------------------*\ /GRST = 1. CLKG is clocking. \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_GRST_YES | /*--- MCBSP_SPCR_GRST_NO | ---*/ 0 ) << _MCBSP_SPCR_GRST_SHIFT) | /*-------------------------------------------------------------------------*\ R/X INTM = (depends on the application) !!!!!!!!!!!!!!!!!!!!!!! \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_XINTM_XRDY | /*--- MCBSP_SPCR_XINTM_EOS | ---*/ /*--- MCBSP_SPCR_XINTM_FRM | ---*/ /*--- MCBSP_SPCR_XINTM_XSYNCERR | ---*/ 0 ) << _MCBSP_SPCR_XINTM_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_XSYNCERR_NO | /*--- MCBSP_SPCR_XSYNCERR_YES | ---*/ 0 ) << _MCBSP_SPCR_XSYNCERR_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_XEMPTY_YES | /*--- MCBSP_SPCR_XEMPTY_NO | ---*/ 0 ) << _MCBSP_SPCR_XEMPTY_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- MCBSP_SPCR_XRDY_NO | ---*/ MCBSP_SPCR_XRDY_YES | 0 ) << _MCBSP_SPCR_XRDY_SHIFT) | /*-------------------------------------------------------------------------*\ R/X RST_ = 1. The transmit/receive operations are enabled. \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_XRST_YES | /*--- MCBSP_SPCR_XRST_NO | ---*/ 0 ) << _MCBSP_SPCR_XRST_SHIFT) | /*-------------------------------------------------------------------------*\ DLB = 0. The digital loop mode is disabled. \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_DLB_OFF | /*--- MCBSP_SPCR_DLB_ON | ---*/ 0 ) << _MCBSP_SPCR_DLB_SHIFT) | /*-------------------------------------------------------------------------*\ RJUST = 0 \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_RJUST_RZF | /*--- MCBSP_SPCR_RJUST_RSE | ---*/ /*--- MCBSP_SPCR_RJUST_LZF | ---*/ 0 ) << _MCBSP_SPCR_RJUST_SHIFT) | /*-------------------------------------------------------------------------*\ CLKSTP = 0. Clock stop mode is disabled. \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_CLKSTP_DISABLE | /*--- MCBSP_SPCR_CLKSTP_NODELAY | ---*/ /*--- MCBSP_SPCR_CLKSTP_DELAY | ---*/ 0 ) << _MCBSP_SPCR_CLKSTP_SHIFT) | /*-------------------------------------------------------------------------*\ R/X INTM = (depends on the application) !!!!!!!!!!!!!!!!!!!!!!! \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_RINTM_RRDY | /*--- MCBSP_SPCR_RINTM_EOS | ---*/ /*--- MCBSP_SPCR_RINTM_FRM | ---*/ /*--- MCBSP_SPCR_RINTM_RSYNCERR | ---*/ 0 ) << _MCBSP_SPCR_RINTM_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_RSYNCERR_NO | /*--- MCBSP_SPCR_RSYNCERR_YES | ---*/ 0 ) << _MCBSP_SPCR_RSYNCERR_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_RFULL_NO | /*--- MCBSP_SPCR_RFULL_YES | ---*/ 0 ) << _MCBSP_SPCR_RFULL_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- MCBSP_SPCR_RRDY_NO | ---*/ MCBSP_SPCR_RRDY_YES | 0 ) << _MCBSP_SPCR_RRDY_SHIFT) | /*-------------------------------------------------------------------------*\ R/X RST_ = 1. The transmit/receive operations are enabled. \*-------------------------------------------------------------------------*/ (( MCBSP_SPCR_RRST_YES | /*--- MCBSP_SPCR_RRST_NO | ---*/ 0 ) << _MCBSP_SPCR_RRST_SHIFT) | 0); /*---------------------------------------------------------------------------------*\ \*---------------------------------------------------------------------------------*/ IOM_DMA_Disable = dma->DMA_PRICTL_ADDR(1).Register = ( /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_DSTRLD_DEFAULT | ---*/ /*--- DMA_PRICTL_DSTRLD_NONE | ---*/ DMA_PRICTL_DSTRLD_B | /*--- DMA_PRICTL_DSTRLD_C | ---*/ /*--- DMA_PRICTL_DSTRLD_D | ---*/ 0 ) << _DMA_PRICTL_DSTRLD_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_SRCRLD_DEFAULT | ---*/ /*--- DMA_PRICTL_SRCRLD_NONE | ---*/ /*--- DMA_PRICTL_SRCRLD_B | ---*/ DMA_PRICTL_SRCRLD_C | /*--- DMA_PRICTL_SRCRLD_D | ---*/ 0 ) << _DMA_PRICTL_SRCRLD_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_EMOD_DEFAULT | ---*/ /*--- DMA_PRICTL_EMOD_NOHALT | ---*/ DMA_PRICTL_EMOD_HALT | 0 ) << _DMA_PRICTL_EMOD_SHIFT) | /*-------------------------------------------------------------------------*\ Frame synchronization FS = 0: disable FS = 1: RSYNC event used to synchronize entire frame \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_FS_DEFAULT | ---*/ DMA_PRICTL_FS_DISABLE | /*--- DMA_PRICTL_FS_RSYNC | ---*/ 0 ) << _DMA_PRICTL_FS_SHIFT) | /*-------------------------------------------------------------------------*\ DMA interrupt bit, TCINT = enabled \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_TCINT_DEFAULT | ---*/ DMA_PRICTL_TCINT_DISABLE | /*--- DMA_PRICTL_TCINT_ENABLE | ---*/ 0 ) << _DMA_PRICTL_TCINT_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_PRI_DEFAULT | ---*/ /*--- DMA_PRICTL_PRI_CPU | ---*/ DMA_PRICTL_PRI_DMA | 0 ) << _DMA_PRICTL_PRI_SHIFT) | /*-------------------------------------------------------------------------*\ No Write Synchronisation (write always after read) \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_WSYNC_DEFAULT | ---*/ /*--- DMA_PRICTL_WSYNC_NONE | ---*/ /*--- DMA_PRICTL_WSYNC_TINT0 | ---*/ /*--- DMA_PRICTL_WSYNC_TINT1 | ---*/ /*--- DMA_PRICTL_WSYNC_SDINT | ---*/ /*--- DMA_PRICTL_WSYNC_EXTINT4 | ---*/ /*--- DMA_PRICTL_WSYNC_EXTINT5 | ---*/ /*--- DMA_PRICTL_WSYNC_EXTINT6 | ---*/ /*--- DMA_PRICTL_WSYNC_EXTINT7 | ---*/ /*--- DMA_PRICTL_WSYNC_DMAINT0 | ---*/ /*--- DMA_PRICTL_WSYNC_DMAINT1 | ---*/ /*--- DMA_PRICTL_WSYNC_DMAINT2 | ---*/ /*--- DMA_PRICTL_WSYNC_DMAINT3 | ---*/ /*--- DMA_PRICTL_WSYNC_XEVT0 | ---*/ /*--- DMA_PRICTL_WSYNC_REVT0 | ---*/ DMA_PRICTL_WSYNC_XEVT1 | /*--- DMA_PRICTL_WSYNC_REVT1 | ---*/ /*--- DMA_PRICTL_WSYNC_DSPINT | ---*/ /*--- DMA_PRICTL_WSYNC_XEVT2 | ---*/ /*--- DMA_PRICTL_WSYNC_REVT2 | ---*/ 0 ) << _DMA_PRICTL_WSYNC_SHIFT) | /*-------------------------------------------------------------------------*\ Receive or transmit synchronization event, RSYNC = REVT from McBSP \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_RSYNC_DEFAULT | ---*/ /*--- DMA_PRICTL_RSYNC_NONE | ---*/ /*--- DMA_PRICTL_RSYNC_TINT0 | ---*/ /*--- DMA_PRICTL_RSYNC_TINT1 | ---*/ /*--- DMA_PRICTL_RSYNC_SDINT | ---*/ /*--- DMA_PRICTL_RSYNC_EXTINT4 | ---*/ /*--- DMA_PRICTL_RSYNC_EXTINT5 | ---*/ /*--- DMA_PRICTL_RSYNC_EXTINT6 | ---*/ /*--- DMA_PRICTL_RSYNC_EXTINT7 | ---*/ /*--- DMA_PRICTL_RSYNC_DMAINT0 | ---*/ /*--- DMA_PRICTL_RSYNC_DMAINT1 | ---*/ /*--- DMA_PRICTL_RSYNC_DMAINT2 | ---*/ /*--- DMA_PRICTL_RSYNC_DMAINT3 | ---*/ /*--- DMA_PRICTL_RSYNC_XEVT0 | ---*/ /*--- DMA_PRICTL_RSYNC_REVT0 | ---*/ /*--- DMA_PRICTL_RSYNC_XEVT1 | ---*/ DMA_PRICTL_RSYNC_REVT1 | /*--- DMA_PRICTL_RSYNC_DSPINT | ---*/ /*--- DMA_PRICTL_RSYNC_XEVT2 | ---*/ /*--- DMA_PRICTL_RSYNC_REVT2 | ---*/ 0 ) << _DMA_PRICTL_RSYNC_SHIFT) | /*-------------------------------------------------------------------------*\ No Global Index Register Used \*-------------------------------------------------------------------------*/ (( DMA_PRICTL_INDEX_DEFAULT | /*--- DMA_PRICTL_INDEX_NA | ---*/ /*--- DMA_PRICTL_INDEX_A | ---*/ /*--- DMA_PRICTL_INDEX_B | ---*/ 0 ) << _DMA_PRICTL_INDEX_SHIFT) | /*-------------------------------------------------------------------------*\ Use Global Count Relead Register A \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_CNTRLD_DEFAULT | ---*/ /*--- DMA_PRICTL_CNTRLD_NA | ---*/ DMA_PRICTL_CNTRLD_A | /*--- DMA_PRICTL_CNTRLD_B | ---*/ 0 ) << _DMA_PRICTL_CNTRLD_SHIFT) | /*-------------------------------------------------------------------------*\ Use Global Adress Register A as Splitt Addr \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_SPLIT_DEFAULT | ---*/ /*--- DMA_PRICTL_SPLIT_DISABLE | ---*/ DMA_PRICTL_SPLIT_A | /*--- DMA_PRICTL_SPLIT_B | ---*/ /*--- DMA_PRICTL_SPLIT_C | ---*/ 0 ) << _DMA_PRICTL_SPLIT_SHIFT) | /*-------------------------------------------------------------------------*\ DMA Element Size 32 Bit \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_ESIZE_DEFAULT | ---*/ DMA_PRICTL_ESIZE_8BIT | /*--- DMA_PRICTL_ESIZE_16BIT | ---*/ /*--- DMA_PRICTL_ESIZE_32BIT | ---*/ /*--- (With_BKanal ? DMA_PRICTL_ESIZE_32BIT : DMA_PRICTL_ESIZE_8BIT) | ---*/ 0 ) << _DMA_PRICTL_ESIZE_SHIFT) | /*-------------------------------------------------------------------------*\ Increment Destination Address \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_DSTDIR_DEFAULT | ---*/ /*--- DMA_PRICTL_DSTDIR_NONE | ---*/ DMA_PRICTL_DSTDIR_INC | /*--- DMA_PRICTL_DSTDIR_DEC | ---*/ /*--- DMA_PRICTL_DSTDIR_IDX | ---*/ 0 ) << _DMA_PRICTL_DSTDIR_SHIFT) | /*-------------------------------------------------------------------------*\ Increment Source Address \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_SRCDIR_DEFAULT | ---*/ /*--- DMA_PRICTL_SRCDIR_NONE | ---*/ DMA_PRICTL_SRCDIR_INC | /*--- DMA_PRICTL_SRCDIR_DEC | ---*/ /*--- DMA_PRICTL_SRCDIR_IDX | ---*/ 0 ) << _DMA_PRICTL_SRCDIR_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_STATUS_DEFAULT | ---*/ DMA_PRICTL_STATUS_STOPPED | /*--- DMA_PRICTL_STATUS_RUNNING | ---*/ /*--- DMA_PRICTL_STATUS_PAUSED | ---*/ /*--- DMA_PRICTL_STATUS_AUTORUNNING | ---*/ 0 ) << _DMA_PRICTL_STATUS_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_START_DEFAULT | ---*/ DMA_PRICTL_START_STOP | /*--- DMA_PRICTL_START_NORMAL | ---*/ /*--- DMA_PRICTL_START_PAUSE | ---*/ /*--- DMA_PRICTL_START_AUTOINIT | ---*/ 0 ) << _DMA_PRICTL_START_SHIFT) | 0); IOM_Init_Done = TRUE; return; } /*-------------------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------------------*/ void IOM_Irq(unsigned int Vector) { struct _Link_ToPc_LocalBuffer *ToPc_Transfer; struct _Link_FromPc_LocalBlocks *FromPc_Transfer; unsigned char *Start; unsigned int Length; unsigned int ThisChannel = IOM_BKanal_Open ? _c6205_channel_b1_kanal : _c6205_channel_d_kanal; unsigned int OtherChannel = IOM_BKanal_Open ? _c6205_channel_d_kanal : _c6205_channel_b1_kanal; /*--- static unsigned int Count = 0; ---*/ if(dma->DMA_SECCTL_ADDR(1).Bits.SXCOND) { #if !defined(NDEBUG) IOM_Irq_Overrun_Count++; #endif /*--- #if !defined(NDEBUG) ---*/ dma->DMA_SECCTL_ADDR(1).Bits.SXCOND = DMA_SECCTL_SXCOND_CLEAR; /*--- DebugPrintf("IOM_Irq: Overrun\n"); ---*/ } if(dma->DMA_SECCTL_ADDR(1).Bits.FRAMECOND) { #if !defined(NDEBUG) IOM_Irq_Frame_Count++; #endif /*--- #if !defined(NDEBUG) ---*/ dma->DMA_SECCTL_ADDR(1).Bits.FRAMECOND = DMA_SECCTL_FRAMECOND_CLEAR; } #if 0 if(McBSP[IOM_McBSP]->MCBSP_SPCR_ADDR.Register & ( (MCBSP_SPCR_XSYNCERR_YES << _MCBSP_SPCR_XSYNCERR_SHIFT) | (MCBSP_SPCR_RSYNCERR_YES << _MCBSP_SPCR_RSYNCERR_SHIFT) | (MCBSP_SPCR_RFULL_YES << _MCBSP_SPCR_RFULL_SHIFT) ) ) { DebugPrintf("MCBSP_SPCR_ADDR.Bits %x", McBSP[IOM_McBSP]->MCBSP_SPCR_ADDR.Register); McBSP[IOM_McBSP]->MCBSP_SPCR_ADDR.Register &= ~( (MCBSP_SPCR_XSYNCERR_YES << _MCBSP_SPCR_XSYNCERR_SHIFT) | (MCBSP_SPCR_RSYNCERR_YES << _MCBSP_SPCR_RSYNCERR_SHIFT) | (MCBSP_SPCR_RFULL_YES << _MCBSP_SPCR_RFULL_SHIFT) ); } #endif /*---------------------------------------------------------------------------------*\ Daten aus IOM_Data[..][IOM_Data_Index] sind fertig \*---------------------------------------------------------------------------------*/ ToPc_Transfer = Link_ToPc_AllocBuffer(ThisChannel, IOM_SAMPLE_SIZE * sizeof(unsigned int), &Start); if(ToPc_Transfer) { iom_memcpy((unsigned short *)Start, (unsigned short *)IOM_Data[IOM_RX][IOM_Data_Index], IOM_SAMPLE_SIZE * 2); Link_ToPc_PutBuffer(ToPc_Transfer, Start, _ToPc_Send_DataValid); } /*---------------------------------------------------------------------------------*\ Daten auf der "anderen" queue komplett verwerfen \*---------------------------------------------------------------------------------*/ do { FromPc_Transfer = Link_FromPc_GetBuffer(OtherChannel, &Length, &Start); if(FromPc_Transfer) { Link_FromPc_FreeBuffer(FromPc_Transfer); } } while(FromPc_Transfer); /*---------------------------------------------------------------------------------*\ Daten auf der "richtigen" queue bis auf 2 Elemente komplett verwerfen \*---------------------------------------------------------------------------------*/ { LOCK(); while(Link_FromPc_QueuedElements(ThisChannel) > 2) { FromPc_Transfer = Link_FromPc_GetBuffer(ThisChannel, &Length, &Start); Link_FromPc_FreeBuffer(FromPc_Transfer); } UNLOCK(); } FromPc_Transfer = Link_FromPc_GetBuffer(ThisChannel, &Length, &Start); /*---------------------------------------------------------------------------------*\ \*---------------------------------------------------------------------------------*/ if(FromPc_Transfer) { iom_memcpy((unsigned short *)IOM_Data[IOM_TX][IOM_Data_Index], (unsigned short *)Start, IOM_SAMPLE_SIZE * 2); Link_FromPc_FreeBuffer(FromPc_Transfer); } else { unsigned int *Source = IOM_BKanal_Open ? (unsigned int *)&IOM_Ruhe_Frame : (unsigned int *)&IOM_Short_Ruhe_Frame; iom__memset((unsigned int *)IOM_Data[IOM_TX][IOM_Data_Index], *Source, IOM_SAMPLE_SIZE); #if !defined(NDEBUG) IOM_TxUnderrun++; #endif /*--- #if !defined(NDEBUG) ---*/ /*--- DebugPrintf("IOM:Tx:No Buffer\n"); ---*/ } /*--- if((Count & 0x3F) == 0) ---*/ /*--- DebugPrintf("IOM:Rx %x Tx %x\n", ---*/ /*--- *((unsigned int *)IOM_Data[IOM_RX][IOM_Data_Index]), ---*/ /*--- *((unsigned int *)IOM_Data[IOM_TX][IOM_Data_Index]) ---*/ /*--- ); ---*/ /*--- Count++; ---*/ /*---------------------------------------------------------------------------------*\ Source reload use: Global Adress Register C \*---------------------------------------------------------------------------------*/ dma->DMA_GBLADDRC_ADDR = (unsigned int)IOM_Data[IOM_TX][IOM_Data_Index]; /*---------------------------------------------------------------------------------*\ Destination reload use: Global Adress Register B \*---------------------------------------------------------------------------------*/ dma->DMA_GBLADDRB_ADDR = (unsigned int)IOM_Data[IOM_RX][IOM_Data_Index] ; /*---------------------------------------------------------------------------------*\ Transfer counter = number of elements to be transferred (global Count reload register A) \*---------------------------------------------------------------------------------*/ dma->DMA_GBLCNTA_ADDR = ( (( 1 | /*--- DMA_XFRCNT_FRMCNT_DEFAULT | ---*/ 0 ) << _DMA_XFRCNT_FRMCNT_SHIFT) | (( (IOM_BKanal_Open ? IOM_SAMPLE_SIZE : IOM_SAMPLE_SIZE * 4) | /*--- DMA_XFRCNT_ELECNT_DEFAULT | ---*/ 0 ) << _DMA_XFRCNT_ELECNT_SHIFT) | 0); IOM_Data_Index = !IOM_Data_Index; return; } /*-------------------------------------------------------------------------------------*\ Multichannel Buffered Serial Port ================================= The 32-bit bit reversal feature is only available on the C621x/C671x/C64x device. Normally all transfers are sent and received with the MSB first. However, you can reverse the receive/transmit bit ordering of a 32-bit element (LSB first) by setting all of the following: \*-------------------------------------------------------------------------------------*/ enum _c6205_link_prot_reason IOM_Open(unsigned int With_BKanal) { if(IOM_Init_Done == FALSE) return _c6205_reason_not_in_current_state; for( ;; ) { struct _Link_FromPc_LocalBlocks *FromPc_Transfer; unsigned char *Start; unsigned int Length; FromPc_Transfer = Link_FromPc_GetBuffer(With_BKanal ? _c6205_channel_d_kanal : _c6205_channel_b1_kanal, &Length, &Start); if(FromPc_Transfer == NULL) { break; } Link_FromPc_FreeBuffer(FromPc_Transfer); } /*---------------------------------------------------------------------------------*\ McBSP Register Configuration FSR, FSX, CLKS, and DR are inputs; DX is an output. To configure the McBSP pins, the pin control register (PCR) must be initialized: * GSYNC = 1. Because DCL generates FSC and the internal sample rate generator clock signal (CLKG) is the DCL divided by two, you must synchronize CLKG with the external frame-synchronization signal input (FSR/FSX). This ensures that the McBSP and the external device have the same phase relationship. Figure 5 shows CLKG and the framing signal (FSG). In case 1, the external framesync FSC occurs at the rising edge of CLKG; thus, there is no need for \*---------------------------------------------------------------------------------*/ McBSP[IOM_McBSP]->MCBSP_PCR_ADDR.Register = ( /*-------------------------------------------------------------------------*\ X/R IOEN = 0. Serial port pins are not general-purpose I/Os. \*-------------------------------------------------------------------------*/ (( MCBSP_PCR_XIOEN_SP | /*--- MCBSP_PCR_XIOEN_GPIO | ---*/ 0 ) << _MCBSP_PCR_XIOEN_SHIFT) | (( MCBSP_PCR_RIOEN_SP | /*--- MCBSP_PCR_RIOEN_GPIO | ---*/ 0 ) << _MCBSP_PCR_RIOEN_SHIFT) | /*-------------------------------------------------------------------------*\ FSXM = 0. The frame sync signal (FSX) is derived from the IOM-2 frame sync signal (FSC). \*-------------------------------------------------------------------------*/ (( MCBSP_PCR_FSXM_EXTERNAL | /*--- MCBSP_PCR_FSXM_INTERNAL | ---*/ 0 ) << _MCBSP_PCR_FSXM_SHIFT) | /*-------------------------------------------------------------------------*\ FSRM = 0. The frame-sync signal (FSR) is derived from the IOM-2 frame-sync signal (FSC). \*-------------------------------------------------------------------------*/ (( MCBSP_PCR_FSRM_EXTERNAL | /*--- MCBSP_PCR_FSRM_INTERNAL | ---*/ 0 ) << _MCBSP_PCR_FSRM_SHIFT) | /*-------------------------------------------------------------------------*\ CLKX/RM = 1. Receive and transmit clocks (CLKR and CLKX) are driven by the sample rate generator. \*-------------------------------------------------------------------------*/ (( /*--- MCBSP_PCR_CLKXM_INPUT | ---*/ MCBSP_PCR_CLKXM_OUTPUT | 0 ) << _MCBSP_PCR_CLKXM_SHIFT) | (( /*--- MCBSP_PCR_CLKRM_INPUT | ---*/ MCBSP_PCR_CLKRM_OUTPUT | 0 ) << _MCBSP_PCR_CLKRM_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( MCBSP_PCR_CLKSSTAT_0 | /*--- MCBSP_PCR_CLKSSTAT_1 | ---*/ 0 ) << _MCBSP_PCR_CLKSSTAT_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( MCBSP_PCR_DXSTAT_0 | /*--- MCBSP_PCR_DXSTAT_1 | ---*/ 0 ) << _MCBSP_PCR_DXSTAT_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( MCBSP_PCR_DRSTAT_0 | /*--- MCBSP_PCR_DRSTAT_1 | ---*/ 0 ) << _MCBSP_PCR_DRSTAT_SHIFT) | /*-------------------------------------------------------------------------*\ FSX/RP = 0. Frame-sync signal is active high. \*-------------------------------------------------------------------------*/ (( MCBSP_PCR_FSXP_ACTIVEHIGH | /*--- MCBSP_PCR_FSXP_ACTIVELOW | ---*/ 0 ) << _MCBSP_PCR_FSXP_SHIFT) | (( MCBSP_PCR_FSRP_ACTIVEHIGH | /*--- MCBSP_PCR_FSRP_ACTIVELOW | ---*/ 0 ) << _MCBSP_PCR_FSRP_SHIFT) | /*-------------------------------------------------------------------------*\ CLKXP = 0. Transmit data is driven on rising edge of CLKX. \*-------------------------------------------------------------------------*/ (( MCBSP_PCR_CLKXP_RISING | /*--- MCBSP_PCR_CLKXP_FALLING | ---*/ 0 ) << _MCBSP_PCR_CLKXP_SHIFT) | /*-------------------------------------------------------------------------*\ CLKRP = 0. Receive data is sampled on falling edge of CLKR. \*-------------------------------------------------------------------------*/ (( MCBSP_PCR_CLKRP_FALLING | /*--- MCBSP_PCR_CLKRP_RISING | ---*/ 0 ) << _MCBSP_PCR_CLKRP_SHIFT) | 0); /*---------------------------------------------------------------------------------*\ As shown in Figure 4, the sample rate generator register (SRGR) is used to configure the internal McBSP frame and clock generator:[4, Chapter 8-5] \*---------------------------------------------------------------------------------*/ McBSP[IOM_McBSP]->MCBSP_SRGR_ADDR.Register = ( /*-------------------------------------------------------------------------*\ GSYNC = 1. Because DCL generates FSC and the internal sample rate generator clock signal (CLKG) is the DCL divided by two, you must synchronize CLKG with the external frame-synchronization signal input (FSR/FSX). This ensures that the McBSP and the external device have the same phase relationship. Figure 5 shows CLKG and the framing signal (FSG). In case 1, the external framesync FSC occurs at the rising edge of CLKG; thus, there is no need for resynchronization. In case 2, however, the rising edge of FSC does not coincide with the rising edge of CLKG. Therefore, resynchronization is necessary. \*-------------------------------------------------------------------------*/ (( /*--- MCBSP_SRGR_GSYNC_FREE | ---*/ MCBSP_SRGR_GSYNC_SYNC | 0 ) << _MCBSP_SRGR_GSYNC_SHIFT) | /*-------------------------------------------------------------------------*\ CLKSP = 0. The rising edge of CLKS generates CLKG and thus CLK(R/X)_int. \*-------------------------------------------------------------------------*/ (( /*--- MCBSP_SRGR_CLKSP_RISING | ---*/ MCBSP_SRGR_CLKSP_FALLING | 0 ) << _MCBSP_SRGR_CLKSP_SHIFT) | /*-------------------------------------------------------------------------*\ CLKSM = 0. The external clock (CLKS) drives the sample rate generator. \*-------------------------------------------------------------------------*/ (( MCBSP_SRGR_CLKSM_CLKS | /*--- MCBSP_SRGR_CLKSM_INTERNAL | ---*/ 0 ) << _MCBSP_SRGR_CLKSM_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( MCBSP_SRGR_FSGM_DXR2XSR | /*--- MCBSP_SRGR_FSGM_FSG | ---*/ 0 ) << _MCBSP_SRGR_FSGM_SHIFT) | /*-------------------------------------------------------------------------*\ The external frame FSC pulse dictates the arrival of a new frame; therefore, the frame period (FPER) and the frame width (FWID) are not programmed. \*-------------------------------------------------------------------------*/ (( 0 | 0 ) << _MCBSP_SRGR_FPER_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( 0 | 0 ) << _MCBSP_SRGR_FWID_SHIFT) | /*-------------------------------------------------------------------------*\ CLKGDV = 1. Divide by 2 DCL to determine the bit sample rate CLKG. \*-------------------------------------------------------------------------*/ (( 1 | 0 ) << _MCBSP_SRGR_CLKGDV_SHIFT) | 0); /*---------------------------------------------------------------------------------*\ the receive and transmit control registers (RCR and XCR) initialize various parameters for the receive and transmit operations: \*---------------------------------------------------------------------------------*/ McBSP[IOM_McBSP]->MCBSP_XCR_ADDR.Register = ( /*-------------------------------------------------------------------------*\ R/X PHASE = 0. Single-phase frame (R/X FRLEN2 and R/X WDLEN2 are not used.) \*-------------------------------------------------------------------------*/ (( MCBSP_XCR_XPHASE_SINGLE | /*--- MCBSP_XCR_XPHASE_DUAL | ---*/ 0 ) << _MCBSP_XCR_XPHASE_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( 0 | /*--- Transmit Frame Length in phase 2 ---*/ 0 ) << _MCBSP_XCR_XFRLEN2_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( MCBSP_XCR_XWDLEN2_8BIT | /*--- MCBSP_XCR_XWDLEN2_12BIT | ---*/ /*--- MCBSP_XCR_XWDLEN2_16BIT | ---*/ /*--- MCBSP_XCR_XWDLEN2_20BIT | ---*/ /*--- MCBSP_XCR_XWDLEN2_24BIT | ---*/ /*--- MCBSP_XCR_XWDLEN2_32BIT | ---*/ 0 ) << _MCBSP_XCR_XWDLEN2_SHIFT) | /*-------------------------------------------------------------------------*\ R/X COMPAND = 0. No companding \*-------------------------------------------------------------------------*/ (( MCBSP_XCR_XCOMPAND_MSB | /*--- MCBSP_XCR_XCOMPAND_8BITLSB | ---*/ /*--- MCBSP_XCR_XCOMPAND_ULAW | ---*/ /*--- MCBSP_XCR_XCOMPAND_ALAW | ---*/ 0 ) << _MCBSP_XCR_XCOMPAND_SHIFT) | /*-------------------------------------------------------------------------*\ R/X FIG = 0 (jetzt testweise 1, Unexpected receive frame synchronization pulses are ignored.) \*-------------------------------------------------------------------------*/ (( /*--- MCBSP_XCR_XFIG_NO | ---*/ MCBSP_XCR_XFIG_YES | 0 ) << _MCBSP_XCR_XFIG_SHIFT) | /*-------------------------------------------------------------------------*\ R/X DATDLY = 0. No delay between the rising edge of the frame sync and the first data. \*-------------------------------------------------------------------------*/ (( MCBSP_XCR_XDATDLY_0BIT | /*--- MCBSP_XCR_XDATDLY_1BIT | ---*/ /*--- MCBSP_XCR_XDATDLY_2BIT | ---*/ 0 ) << _MCBSP_XCR_XDATDLY_SHIFT) | /*-------------------------------------------------------------------------*\ R/X FRLEN1 = ( N - 1). Depends on which mode is used: one to eight channels when running in line-card mode; three channels when running in terminal mode. \*-------------------------------------------------------------------------*/ (( 0 | 0 ) << _MCBSP_XCR_XFRLEN1_SHIFT) | /*-------------------------------------------------------------------------*\ R/X WDLEN1 = 101b. 32-bit words \*-------------------------------------------------------------------------*/ (( /*--- MCBSP_XCR_XWDLEN1_8BIT | ---*/ /*--- MCBSP_XCR_XWDLEN1_12BIT | ---*/ /*--- MCBSP_XCR_XWDLEN1_16BIT | ---*/ /*--- MCBSP_XCR_XWDLEN1_20BIT | ---*/ /*--- MCBSP_XCR_XWDLEN1_24BIT | ---*/ /*--- MCBSP_XCR_XWDLEN1_32BIT | ---*/ (With_BKanal ? MCBSP_XCR_XWDLEN1_32BIT : MCBSP_XCR_XWDLEN1_8BIT) | 0 ) << _MCBSP_XCR_XWDLEN1_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ 0); McBSP[IOM_McBSP]->MCBSP_RCR_ADDR.Register = ( /*-------------------------------------------------------------------------*\ R/X PHASE = 0. Single-phase frame (R/X FRLEN2 and R/X WDLEN2 are not used.) \*-------------------------------------------------------------------------*/ (( MCBSP_RCR_RPHASE_SINGLE | /*--- MCBSP_RCR_RPHASE_DUAL | ---*/ 0 ) << _MCBSP_RCR_RPHASE_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( 0 | /*--- Transmit Frame Length in phase 2 ---*/ 0 ) << _MCBSP_RCR_RFRLEN2_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( MCBSP_RCR_RWDLEN2_8BIT | /*--- MCBSP_RCR_RWDLEN2_12BIT | ---*/ /*--- MCBSP_RCR_RWDLEN2_16BIT | ---*/ /*--- MCBSP_RCR_RWDLEN2_20BIT | ---*/ /*--- MCBSP_RCR_RWDLEN2_24BIT | ---*/ /*--- MCBSP_RCR_RWDLEN2_32BIT | ---*/ 0 ) << _MCBSP_RCR_RWDLEN2_SHIFT) | /*-------------------------------------------------------------------------*\ R/X COMPAND = 0. No companding \*-------------------------------------------------------------------------*/ (( MCBSP_RCR_RCOMPAND_MSB | /*--- MCBSP_RCR_RCOMPAND_8BITLSB | ---*/ /*--- MCBSP_RCR_RCOMPAND_ULAW | ---*/ /*--- MCBSP_RCR_RCOMPAND_ALAW | ---*/ 0 ) << _MCBSP_RCR_RCOMPAND_SHIFT) | /*-------------------------------------------------------------------------*\ R/X FIG = 0 (jetzt testweise 1, Unexpected receive frame synchronization pulses are ignored.) \*-------------------------------------------------------------------------*/ (( /*--- MCBSP_RCR_RFIG_NO | ---*/ MCBSP_RCR_RFIG_YES | 0 ) << _MCBSP_RCR_RFIG_SHIFT) | /*-------------------------------------------------------------------------*\ R/X DATDLY = 0. No delay between the rising edge of the frame sync and the first data. \*-------------------------------------------------------------------------*/ (( MCBSP_RCR_RDATDLY_0BIT | /*--- MCBSP_RCR_RDATDLY_1BIT | ---*/ /*--- MCBSP_RCR_RDATDLY_2BIT | ---*/ 0 ) << _MCBSP_RCR_RDATDLY_SHIFT) | /*-------------------------------------------------------------------------*\ R/X FRLEN1 = ( N - 1). Depends on which mode is used: one to eight channels when running in line-card mode; three channels when running in terminal mode. \*-------------------------------------------------------------------------*/ (( 0 | 0 ) << _MCBSP_RCR_RFRLEN1_SHIFT) | /*-------------------------------------------------------------------------*\ R/X WDLEN1 = 101b. 32-bit words \*-------------------------------------------------------------------------*/ (( /*--- MCBSP_RCR_RWDLEN1_12BIT | ---*/ /*--- MCBSP_RCR_RWDLEN1_16BIT | ---*/ /*--- MCBSP_RCR_RWDLEN1_20BIT | ---*/ /*--- MCBSP_RCR_RWDLEN1_24BIT | ---*/ /*--- MCBSP_RCR_RWDLEN1_32BIT | ---*/ (With_BKanal ? MCBSP_RCR_RWDLEN1_32BIT : MCBSP_RCR_RWDLEN1_8BIT) | 0 ) << _MCBSP_RCR_RWDLEN1_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ 0); /*---------------------------------------------------------------------------------*\ The serial port is configured and initialized via the serial-port control register (SPCR): \*---------------------------------------------------------------------------------*/ McBSP[IOM_McBSP]->MCBSP_SPCR_ADDR.Register = IOM_McBSP_Disable; /*---------------------------------------------------------------------------------*\ DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA Most applications require the DMA (direct memory access) to service the McBSP. In that case, the following order in the initialization steps must be respected. Typical settings for the DMA channel would be to use the split mode to service both receive and transmit: \*---------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------*\ Source address = address of the transmit buffer \*---------------------------------------------------------------------------------*/ if(With_BKanal) iom__memset((unsigned int *)IOM_Data[IOM_TX][0], *((unsigned int *)&IOM_Ruhe_Frame), IOM_SAMPLE_SIZE); else iom__memset((unsigned int *)IOM_Data[IOM_TX][0], *((unsigned int *)&IOM_Short_Ruhe_Frame), IOM_SAMPLE_SIZE); dma->DMA_SRC_ADDR(1) = (unsigned int)IOM_Data[IOM_TX][0]; /*---------------------------------------------------------------------------------*\ Source reload use: Global Adress Register C \*---------------------------------------------------------------------------------*/ if(With_BKanal) iom__memset((unsigned int *)IOM_Data[IOM_TX][1], *((unsigned int *)&IOM_Ruhe_Frame), IOM_SAMPLE_SIZE); else iom__memset((unsigned int *)IOM_Data[IOM_TX][1], *((unsigned int *)&IOM_Short_Ruhe_Frame), IOM_SAMPLE_SIZE); dma->DMA_GBLADDRC_ADDR = (unsigned int)IOM_Data[IOM_TX][1]; /*---------------------------------------------------------------------------------*\ Destination address = address of the receive buffer \*---------------------------------------------------------------------------------*/ dma->DMA_DST_ADDR(1) = (unsigned int)IOM_Data[IOM_RX][0]; /*---------------------------------------------------------------------------------*\ Destination reload use: Global Adress Register B \*---------------------------------------------------------------------------------*/ dma->DMA_GBLADDRB_ADDR = (unsigned int)IOM_Data[IOM_RX][1]; /*---------------------------------------------------------------------------------*\ Split-address register = address of the serial port DRR \*---------------------------------------------------------------------------------*/ dma->DMA_GBLADDRA_ADDR = (unsigned int)&(McBSP[IOM_McBSP]->MCBSP_DRR_ADDR); IOM_Data_Index = 0; /*--- aktueller Buffer ---*/ /*---------------------------------------------------------------------------------*\ Transfer counter = number of elements to be transferred \*---------------------------------------------------------------------------------*/ dma->DMA_XFRCNT_ADDR(1) = ( (( 1 | /*--- DMA_XFRCNT_FRMCNT_DEFAULT | ---*/ 0 ) << _DMA_XFRCNT_FRMCNT_SHIFT) | (( (With_BKanal ? IOM_SAMPLE_SIZE : IOM_SAMPLE_SIZE * 4) | /*--- DMA_XFRCNT_ELECNT_DEFAULT | ---*/ 0 ) << _DMA_XFRCNT_ELECNT_SHIFT) | 0); /*---------------------------------------------------------------------------------*\ Transfer counter = number of elements to be transferred (global Count reload register A) \*---------------------------------------------------------------------------------*/ dma->DMA_GBLCNTA_ADDR = ( (( 1 | /*--- DMA_XFRCNT_FRMCNT_DEFAULT | ---*/ 0 ) << _DMA_XFRCNT_FRMCNT_SHIFT) | (( (With_BKanal ? IOM_SAMPLE_SIZE : IOM_SAMPLE_SIZE * 4) | /*--- DMA_XFRCNT_ELECNT_DEFAULT | ---*/ 0 ) << _DMA_XFRCNT_ELECNT_SHIFT) | 0); /*---------------------------------------------------------------------------------*\ \*---------------------------------------------------------------------------------*/ dma->DMA_PRICTL_ADDR(1).Register = IOM_DMA_Disable; /*---------------------------------------------------------------------------------*\ \*---------------------------------------------------------------------------------*/ dma->DMA_SECCTL_ADDR(1).Register = ( (( /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ DMA_SECCTL_WSPOL_DEFAULT | /*--- DMA_SECCTL_WSPOL_NA | ---*/ /*--- DMA_SECCTL_WSPOL_ACTIVEHIGH | ---*/ /*--- DMA_SECCTL_WSPOL_ACTIVELOW | ---*/ 0 ) << _DMA_SECCTL_WSPOL_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( DMA_SECCTL_RSPOL_DEFAULT | /*--- DMA_SECCTL_RSPOL_NA | ---*/ /*--- DMA_SECCTL_RSPOL_ACTIVEHIGH | ---*/ /*--- DMA_SECCTL_RSPOL_ACTIVELOW | ---*/ 0 ) << _DMA_SECCTL_RSPOL_SHIFT) | /*-------------------------------------------------------------------------*\ FSIG Level/edge detect mode selection. FSIG must be set to “0” for non-frame-synchronized transfers (not applicable for C6201 and C6701 devices). FSIG = 0: Edge detect mode (FS = 1 or FS = 0). FSIG = 1: Level detect mode (valid only when FS = 1). In level detect mode, synchronization inputs received during a frame transfer are ignored unless still set after the frame transfer completes. \*-------------------------------------------------------------------------*/ (( /*--- DMA_SECCTL_FSIG_DEFAULT | ---*/ /*--- DMA_SECCTL_FSIG_NA | ---*/ DMA_SECCTL_FSIG_NORMAL | /*--- edge ---*/ /*--- DMA_SECCTL_FSIG_IGNORE | ---*/ 0 ) << _DMA_SECCTL_FSIG_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( DMA_SECCTL_DMACEN_DEFAULT | /*--- DMA_SECCTL_DMACEN_LOW | ---*/ /*--- DMA_SECCTL_DMACEN_HIGH | ---*/ /*--- DMA_SECCTL_DMACEN_RSYNCSTAT | ---*/ /*--- DMA_SECCTL_DMACEN_WSYNCSTAT | ---*/ /*--- DMA_SECCTL_DMACEN_FRAMECOND | ---*/ /*--- DMA_SECCTL_DMACEN_BLOCKCOND | ---*/ 0 ) << _DMA_SECCTL_DMACEN_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_SECCTL_WSYNCCLR_DEFAULT | ---*/ /*--- DMA_SECCTL_WSYNCCLR_NOTHING | ---*/ DMA_SECCTL_WSYNCCLR_CLEAR | 0 ) << _DMA_SECCTL_WSYNCCLR_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( DMA_SECCTL_WSYNCSTAT_DEFAULT | /*--- DMA_SECCTL_WSYNCSTAT_CLEAR | ---*/ /*--- DMA_SECCTL_WSYNCSTAT_SET | ---*/ 0 ) << _DMA_SECCTL_WSYNCSTAT_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_SECCTL_RSYNCCLR_DEFAULT | ---*/ /*--- DMA_SECCTL_RSYNCCLR_NOTHING | ---*/ DMA_SECCTL_RSYNCCLR_CLEAR | 0 ) << _DMA_SECCTL_RSYNCCLR_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( DMA_SECCTL_RSYNCSTAT_DEFAULT | /*--- DMA_SECCTL_RSYNCSTAT_CLEAR | ---*/ /*--- DMA_SECCTL_RSYNCSTAT_SET | ---*/ 0 ) << _DMA_SECCTL_RSYNCSTAT_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_SECCTL_WDROPIE_DEFAULT | ---*/ DMA_SECCTL_WDROPIE_DISABLE | /*--- DMA_SECCTL_WDROPIE_ENABLE | ---*/ 0 ) << _DMA_SECCTL_WDROPIE_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( DMA_SECCTL_WDROPCOND_DEFAULT | /*--- DMA_SECCTL_WDROPCOND_CLEAR | ---*/ /*--- DMA_SECCTL_WDROPCOND_SET | ---*/ 0 ) << _DMA_SECCTL_WDROPCOND_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_SECCTL_RDROPIE_DEFAULT | ---*/ DMA_SECCTL_RDROPIE_DISABLE | /*--- DMA_SECCTL_RDROPIE_ENABLE | ---*/ 0 ) << _DMA_SECCTL_RDROPIE_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( DMA_SECCTL_RDROPCOND_DEFAULT | /*--- DMA_SECCTL_RDROPCOND_CLEAR | ---*/ /*--- DMA_SECCTL_RDROPCOND_SET | ---*/ 0 ) << _DMA_SECCTL_RDROPCOND_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_SECCTL_BLOCKIE_DEFAULT | ---*/ DMA_SECCTL_BLOCKIE_DISABLE | /*--- DMA_SECCTL_BLOCKIE_ENABLE | ---*/ 0 ) << _DMA_SECCTL_BLOCKIE_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( DMA_SECCTL_BLOCKCOND_DEFAULT | /*--- DMA_SECCTL_BLOCKCOND_CLEAR | ---*/ /*--- DMA_SECCTL_BLOCKCOND_SET | ---*/ 0 ) << _DMA_SECCTL_BLOCKCOND_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_SECCTL_LASTIE_DEFAULT | ---*/ DMA_SECCTL_LASTIE_DISABLE | /*--- DMA_SECCTL_LASTIE_ENABLE | ---*/ 0 ) << _DMA_SECCTL_LASTIE_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( DMA_SECCTL_LASTCOND_DEFAULT | /*--- DMA_SECCTL_LASTCOND_CLEAR | ---*/ /*--- DMA_SECCTL_LASTCOND_SET | ---*/ 0 ) << _DMA_SECCTL_LASTCOND_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_SECCTL_FRAMEIE_DEFAULT | ---*/ /*--- DMA_SECCTL_FRAMEIE_DISABLE | ---*/ DMA_SECCTL_FRAMEIE_ENABLE | 0 ) << _DMA_SECCTL_FRAMEIE_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( DMA_SECCTL_FRAMECOND_DEFAULT | /*--- DMA_SECCTL_FRAMECOND_CLEAR | ---*/ /*--- DMA_SECCTL_FRAMECOND_SET | ---*/ 0 ) << _DMA_SECCTL_FRAMECOND_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_SECCTL_SXIE_DEFAULT | ---*/ /*--- DMA_SECCTL_SXIE_DISABLE | ---*/ DMA_SECCTL_SXIE_ENABLE | 0 ) << _DMA_SECCTL_SXIE_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( DMA_SECCTL_SXCOND_DEFAULT | /*--- DMA_SECCTL_SXCOND_CLEAR | ---*/ /*--- DMA_SECCTL_SXCOND_SET | ---*/ 0 ) << _DMA_SECCTL_SXCOND_SHIFT) | 0); /*---------------------------------------------------------------------------------*\ Take the sample rate generator out of reset by setting /GRST=1 in SPCR. \*---------------------------------------------------------------------------------*/ McBSP[IOM_McBSP]->MCBSP_SPCR_ADDR.Register = (IOM_McBSP_Disable & ~(_MCBSP_SPCR_GRST_MASK | _MCBSP_SPCR_XRST_MASK | _MCBSP_SPCR_RRST_MASK)) | (( /*--- MCBSP_SPCR_XRST_YES | ---*/ MCBSP_SPCR_XRST_NO | 0 ) << _MCBSP_SPCR_XRST_SHIFT) | (( /*--- MCBSP_SPCR_RRST_YES | ---*/ MCBSP_SPCR_RRST_NO | 0 ) << _MCBSP_SPCR_RRST_SHIFT) | (( /*--- MCBSP_SPCR_GRST_YES | ---*/ MCBSP_SPCR_GRST_NO | 0 ) << _MCBSP_SPCR_GRST_SHIFT); /*---------------------------------------------------------------------------------*\ Enable the CPU interrupt that corresponds to the DMA channel used. (You must set the global interrupt enable (GIE) and non-maskable interrupt (NMIE) bits, plus the bit corresponding to the DMA channel interrupt you want to use in the IER.) \*---------------------------------------------------------------------------------*/ IOM_BKanal_Open = With_BKanal; Irq_Delay_Enable(IOM_Irq_Handle); /*---------------------------------------------------------------------------------*\ Start the DMA. \*---------------------------------------------------------------------------------*/ dma->DMA_PRICTL_ADDR(1).Register = (IOM_DMA_Disable & ~(_DMA_PRICTL_ESIZE_MASK | _DMA_PRICTL_TCINT_MASK | _DMA_PRICTL_STATUS_MASK | _DMA_PRICTL_START_MASK)) | (( (With_BKanal ? DMA_PRICTL_ESIZE_32BIT : DMA_PRICTL_ESIZE_8BIT) | 0 ) << _DMA_PRICTL_ESIZE_SHIFT) | (( /*--- DMA_PRICTL_TCINT_DEFAULT | ---*/ /*--- DMA_PRICTL_TCINT_DISABLE | ---*/ DMA_PRICTL_TCINT_ENABLE | 0 ) << _DMA_PRICTL_TCINT_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_STATUS_DEFAULT | ---*/ /*--- DMA_PRICTL_STATUS_STOPPED | ---*/ /*--- DMA_PRICTL_STATUS_RUNNING | ---*/ /*--- DMA_PRICTL_STATUS_PAUSED | ---*/ DMA_PRICTL_STATUS_AUTORUNNING | 0 ) << _DMA_PRICTL_STATUS_SHIFT) | /*-------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------*/ (( /*--- DMA_PRICTL_START_DEFAULT | ---*/ /*--- DMA_PRICTL_START_STOP | ---*/ /*--- DMA_PRICTL_START_NORMAL | ---*/ /*--- DMA_PRICTL_START_PAUSE | ---*/ DMA_PRICTL_START_AUTOINIT | 0 ) << _DMA_PRICTL_START_SHIFT); *(IPACX_SDS1_CR(0)) = With_BKanal ? SDSx_EN_TSS : SDSx_EN_TSS3; *(IPACX_SDS_CONF(0)) = 0; if(With_BKanal) McBSP[IOM_McBSP]->MCBSP_DXR_ADDR = *((unsigned int *)&IOM_Ruhe_Frame); else McBSP[IOM_McBSP]->MCBSP_DXR_ADDR = *((unsigned int *)&IOM_Short_Ruhe_Frame); #if 0 #define _PCI_EECTL_EECNT_MASK 0x00000003u #define _PCI_EECTL_EECNT_SHIFT 0x00000000u #define PCI_EECTL_EECNT_DEFAULT 0x00000000u #define PCI_EECTL_EECNT_EWEN 0x00000000u #define PCI_EECTL_EECNT_ERAL 0x00000000u #define PCI_EECTL_EECNT_WRAL 0x00000000u #define PCI_EECTL_EECNT_EWDS 0x00000000u #define PCI_EECTL_EECNT_WRITE 0x00000001u #define PCI_EECTL_EECNT_READ 0x00000002u #define PCI_EECTL_EECNT_ERASE 0x00000003u eeprom->PCI_EEADD_ADDR = 0; eeprom->PCI_EECTL_ADDR = PCI_EECTL_EECNT_READ; #endif return _c6205_reason_success; } /*-------------------------------------------------------------------------------------*\ \*-------------------------------------------------------------------------------------*/ enum _c6205_link_prot_reason IOM_Close(void) { if(IOM_Init_Done == FALSE) return _c6205_reason_not_in_current_state; Irq_Delay_Disable(IOM_Irq_Handle); dma->DMA_PRICTL_ADDR(1).Register = IOM_DMA_Disable; McBSP[IOM_McBSP]->MCBSP_SPCR_ADDR.Register = IOM_McBSP_Disable; IOM_BKanal_Open = 0; for( ;; ) { struct _Link_FromPc_LocalBlocks *FromPc_Transfer; unsigned char *Start; unsigned int Length; FromPc_Transfer = Link_FromPc_GetBuffer(_c6205_channel_d_kanal, &Length, &Start); if(FromPc_Transfer == NULL) { FromPc_Transfer = Link_FromPc_GetBuffer(_c6205_channel_b1_kanal, &Length, &Start); if(FromPc_Transfer == NULL) { break; } } Link_FromPc_FreeBuffer(FromPc_Transfer); } return _c6205_reason_success; }