--- zzzz-none-000/linux-2.4.17/arch/mips/ite-boards/generic/irq.c 2001-09-09 17:43:01.000000000 +0000 +++ sangam-fb-322/linux-2.4.17/arch/mips/ite-boards/generic/irq.c 2004-11-24 13:22:38.000000000 +0000 @@ -72,17 +72,18 @@ #define EXT_IRQ0_TO_IP 2 /* IP 2 */ #define EXT_IRQ5_TO_IP 7 /* IP 7 */ -extern void set_debug_traps(void); -extern void mips_timer_interrupt(int irq, struct pt_regs *regs); -extern asmlinkage void it8172_IRQ(void); +#define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) + unsigned int local_bh_count[NR_CPUS]; unsigned int local_irq_count[NR_CPUS]; -unsigned long spurious_count = 0; -irq_desc_t irq_desc[NR_IRQS]; -irq_desc_t *irq_desc_base=&irq_desc[0]; void disable_it8172_irq(unsigned int irq_nr); void enable_it8172_irq(unsigned int irq_nr); +extern void set_debug_traps(void); +extern void mips_timer_interrupt(int irq, struct pt_regs *regs); +extern asmlinkage void it8172_IRQ(void); +extern void init_generic_irq(void); + struct it8172_intc_regs volatile *it8172_hw0_icregs = (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE)); @@ -105,7 +106,7 @@ modify_cp0_intmask(0, irq_nr); } -void disable_irq(unsigned int irq_nr) +void local_disable_irq(unsigned int irq_nr) { unsigned long flags; @@ -114,7 +115,7 @@ restore_flags(flags); } -void enable_irq(unsigned int irq_nr) +void local_enable_irq(unsigned int irq_nr) { unsigned long flags; @@ -130,63 +131,70 @@ if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) { /* LPC interrupt */ - DPRINTK("disable, before lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); - it8172_hw0_icregs->lpc_mask |= (1 << (irq_nr - IT8172_LPC_IRQ_BASE)); - DPRINTK("disable, after lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); + DPRINTK("DB lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); + it8172_hw0_icregs->lpc_mask |= + (1 << (irq_nr - IT8172_LPC_IRQ_BASE)); + DPRINTK("DA lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); } else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) { /* Local Bus interrupt */ - DPRINTK("before lb_mask %x\n", it8172_hw0_icregs->lb_mask); - it8172_hw0_icregs->lb_mask |= (1 << (irq_nr - IT8172_LB_IRQ_BASE)); - DPRINTK("after lb_mask %x\n", it8172_hw0_icregs->lb_mask); + DPRINTK("DB lb_mask %x\n", it8172_hw0_icregs->lb_mask); + it8172_hw0_icregs->lb_mask |= + (1 << (irq_nr - IT8172_LB_IRQ_BASE)); + DPRINTK("DA lb_mask %x\n", it8172_hw0_icregs->lb_mask); } else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) { /* PCI and other interrupts */ - DPRINTK("before pci_mask %x\n", it8172_hw0_icregs->pci_mask); - it8172_hw0_icregs->pci_mask |= (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE)); - DPRINTK("after pci_mask %x\n", it8172_hw0_icregs->pci_mask); + DPRINTK("DB pci_mask %x\n", it8172_hw0_icregs->pci_mask); + it8172_hw0_icregs->pci_mask |= + (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE)); + DPRINTK("DA pci_mask %x\n", it8172_hw0_icregs->pci_mask); } else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) { /* NMI interrupts */ - DPRINTK("before nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); - it8172_hw0_icregs->nmi_mask |= (1 << (irq_nr - IT8172_NMI_IRQ_BASE)); - DPRINTK("after nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); + DPRINTK("DB nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); + it8172_hw0_icregs->nmi_mask |= + (1 << (irq_nr - IT8172_NMI_IRQ_BASE)); + DPRINTK("DA nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); } else { - panic("disable_it8172_irq: bad irq %d\n", irq_nr); + panic("disable_it8172_irq: bad irq %d", irq_nr); } } - void enable_it8172_irq(unsigned int irq_nr) { DPRINTK("enable_it8172_irq %d\n", irq_nr); if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) { /* LPC interrupt */ - DPRINTK("enable, before lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); - it8172_hw0_icregs->lpc_mask &= ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE)); - DPRINTK("enable, after lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); + DPRINTK("EB before lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); + it8172_hw0_icregs->lpc_mask &= + ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE)); + DPRINTK("EA after lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); } else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) { /* Local Bus interrupt */ - DPRINTK("before lb_mask %x\n", it8172_hw0_icregs->lb_mask); - it8172_hw0_icregs->lb_mask &= ~(1 << (irq_nr - IT8172_LB_IRQ_BASE)); - DPRINTK("after lb_mask %x\n", it8172_hw0_icregs->lb_mask); + DPRINTK("EB lb_mask %x\n", it8172_hw0_icregs->lb_mask); + it8172_hw0_icregs->lb_mask &= + ~(1 << (irq_nr - IT8172_LB_IRQ_BASE)); + DPRINTK("EA lb_mask %x\n", it8172_hw0_icregs->lb_mask); } else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) { /* PCI and other interrupts */ - DPRINTK("before pci_mask %x\n", it8172_hw0_icregs->pci_mask); - it8172_hw0_icregs->pci_mask &= ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE)); - DPRINTK("after pci_mask %x\n", it8172_hw0_icregs->pci_mask); + DPRINTK("EB pci_mask %x\n", it8172_hw0_icregs->pci_mask); + it8172_hw0_icregs->pci_mask &= + ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE)); + DPRINTK("EA pci_mask %x\n", it8172_hw0_icregs->pci_mask); } else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) { /* NMI interrupts */ - DPRINTK("before nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); - it8172_hw0_icregs->nmi_mask &= ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE)); - DPRINTK("after nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); + DPRINTK("EB nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); + it8172_hw0_icregs->nmi_mask &= + ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE)); + DPRINTK("EA nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); } else { - panic("enable_it8172_irq: bad irq %d\n", irq_nr); + panic("enable_it8172_irq: bad irq %d", irq_nr); } } @@ -217,160 +225,25 @@ }; -int get_irq_list(char *buf) -{ - int i, len = 0, j; - struct irqaction * action; - - len += sprintf(buf+len, " "); - for (j=0; jhandler ) - continue; - len += sprintf(buf+len, "%3d: ", i); - len += sprintf(buf+len, "%10u ", kstat_irqs(i)); - if ( irq_desc[i].handler ) - len += sprintf(buf+len, " %s ", irq_desc[i].handler->typename ); - else - len += sprintf(buf+len, " None "); - len += sprintf(buf+len, " %s",action->name); - for (action=action->next; action; action = action->next) { - len += sprintf(buf+len, ", %s", action->name); - } - len += sprintf(buf+len, "\n"); - } - len += sprintf(buf+len, "BAD: %10lu\n", spurious_count); - return len; -} - -asmlinkage void do_IRQ(int irq, struct pt_regs *regs) -{ - struct irqaction *action; - int cpu; - - cpu = smp_processor_id(); - irq_enter(cpu, irq); - - kstat.irqs[cpu][irq]++; -#if 0 - if (irq_desc[irq].handler && irq_desc[irq].handler->ack) { - // printk("invoking ack handler\n"); - irq_desc[irq].handler->ack(irq); - } -#endif - - action = irq_desc[irq].action; - - if (action && action->handler) - { - //mask_irq(1<handler %x\n", action->handler); - disable_it8172_irq(irq); - //if (!(action->flags & SA_INTERRUPT)) __sti(); /* reenable ints */ - do { - action->handler(irq, action->dev_id, regs); - action = action->next; - } while ( action ); - //__cli(); /* disable ints */ - if (irq_desc[irq].handler) - { - } - //unmask_irq(1<cp0_cause); - disable_it8172_irq(irq); - } - irq_exit(cpu, irq); -} - -int request_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), - unsigned long irqflags, const char * devname, void *dev_id) -{ - struct irqaction *old, **p, *action; - unsigned long flags; +static void enable_none(unsigned int irq) { } +static unsigned int startup_none(unsigned int irq) { return 0; } +static void disable_none(unsigned int irq) { } +static void ack_none(unsigned int irq) { } + +/* startup is the same as "enable", shutdown is same as "disable" */ +#define shutdown_none disable_none +#define end_none enable_none + +static struct hw_interrupt_type cp0_irq_type = { + "CP0 Count", + startup_none, + shutdown_none, + enable_none, + disable_none, + ack_none, + end_none +}; - /* - * IP0 and IP1 are software interrupts. IP7 is typically the timer interrupt. - * - * The ITE QED-4N-S01B board has one single interrupt line going from - * the system controller to the CPU. It's connected to the CPU external - * irq pin 1, which is IP2. The interrupt numbers are listed in it8172_int.h; - * the ISA interrupts are numbered from 0 to 15, and the rest go from - * there. - */ - - //printk("request_irq: %d handler %x\n", irq, handler); - if (irq >= NR_IRQS) - return -EINVAL; - - if (!handler) - { - /* Free */ - for (p = &irq_desc[irq].action; (action = *p) != NULL; p = &action->next) - { - /* Found it - now free it */ - save_flags(flags); - cli(); - *p = action->next; - disable_it8172_irq(irq); - restore_flags(flags); - kfree(action); - return 0; - } - return -ENOENT; - } - - action = (struct irqaction *) - kmalloc(sizeof(struct irqaction), GFP_KERNEL); - if (!action) - return -ENOMEM; - memset(action, 0, sizeof(struct irqaction)); - - save_flags(flags); - cli(); - - action->handler = handler; - action->flags = irqflags; - action->mask = 0; - action->name = devname; - action->dev_id = dev_id; - action->next = NULL; - - p = &irq_desc[irq].action; - - if ((old = *p) != NULL) { - /* Can't share interrupts unless both agree to */ - if (!(old->flags & action->flags & SA_SHIRQ)) - return -EBUSY; - /* add new interrupt at end of irq queue */ - do { - p = &old->next; - old = *p; - } while (old); - } - *p = action; - enable_it8172_irq(irq); - restore_flags(flags); -#if 0 - printk("request_irq: status %x cause %x\n", - read_32bit_cp0_register(CP0_STATUS), read_32bit_cp0_register(CP0_CAUSE)); -#endif - return 0; -} - -void free_irq(unsigned int irq, void *dev_id) -{ - request_irq(irq, NULL, 0, NULL, dev_id); -} void enable_cpu_timer(void) { @@ -381,26 +254,17 @@ restore_flags(flags); } -unsigned long probe_irq_on (void) -{ - return 0; -} - -int probe_irq_off (unsigned long irqs) -{ - return 0; -} - void __init init_IRQ(void) { int i; unsigned long flags; - memset(irq_desc, 0, sizeof(irq_desc)); set_except_vector(0, it8172_IRQ); + init_generic_irq(); + /* mask all interrupts */ it8172_hw0_icregs->lb_mask = 0xffff; it8172_hw0_icregs->lpc_mask = 0xffff; @@ -431,20 +295,11 @@ ~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE)); #endif - for (i = 0; i <= IT8172_INT_END; i++) { - irq_desc[i].status = IRQ_DISABLED; - irq_desc[i].action = 0; - irq_desc[i].depth = 1; - irq_desc[i].handler = &it8172_irq_type; + for (i = 0; i <= IT8172_LAST_IRQ; i++) { + irq_desc[i].handler = &it8172_irq_type; } - - /* - * Enable external int line 2 - * All ITE interrupts are masked for now. - */ - save_and_cli(flags); - unmask_irq(1<intstatus; if (intstatus & 0x8) { - panic("Got NMI interrupt\n"); + panic("Got NMI interrupt"); } else if (intstatus & 0x4) { /* PCI interrupt */ irq = 0; - status = it8172_hw0_icregs->pci_req; + status |= it8172_hw0_icregs->pci_req; while (!(status & 0x1)) { irq++; status >>= 1; @@ -493,7 +348,7 @@ else if (intstatus & 0x1) { /* Local Bus interrupt */ irq = 0; - status = it8172_hw0_icregs->lb_req; + status |= it8172_hw0_icregs->lb_req; while (!(status & 0x1)) { irq++; status >>= 1; @@ -507,7 +362,7 @@ * we could lose an interrupt this way because * we acknowledge all ints at onces. Revisit. */ - status = it8172_hw0_icregs->lpc_req; + status |= it8172_hw0_icregs->lpc_req; it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */ irq = 0; while (!(status & 0x1)) {