--- zzzz-none-000/linux-2.4.17/include/asm-mips/au1000.h 2001-09-09 17:43:01.000000000 +0000 +++ sangam-fb-322/linux-2.4.17/include/asm-mips/au1000.h 2004-11-24 13:21:30.000000000 +0000 @@ -1,9 +1,9 @@ /* * * BRIEF MODULE DESCRIPTION - * Include file for Alchemy Semiconductor's Au1000 CPU. + * Include file for Alchemy Semiconductor's Au1k CPU. * - * Copyright 2000 MontaVista Software Inc. + * Copyright 2000,2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * @@ -28,191 +28,179 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ + /* + * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp + */ + #ifndef _AU1000_H_ #define _AU1000_H_ +#include +#include + +/* cpu pipeline flush */ +void static inline au_sync(void) +{ + __asm__ volatile ("sync"); +} + +void static inline au_sync_udelay(int us) +{ + __asm__ volatile ("sync"); + udelay(us); +} + +void static inline au_sync_delay(int ms) +{ + __asm__ volatile ("sync"); + mdelay(ms); +} + +void static inline outb_sync(u8 val, int reg) +{ + outb(val, reg); + au_sync(); +} + +void static inline outw_sync(u16 val, int reg) +{ + outw(val, reg); + au_sync(); +} + +void static inline outl_sync(u32 val, int reg) +{ + outl(val, reg); + au_sync(); +} + +/* arch/mips/au1000/common/clocks.c */ +extern void set_au1000_speed(unsigned int new_freq); +extern unsigned int get_au1000_speed(void); +extern void set_au1000_uart_baud_base(unsigned long new_baud_base); +extern unsigned long get_au1000_uart_baud_base(void); +extern void set_au1000_lcd_clock(void); +extern unsigned int get_au1000_lcd_clock(void); + +#ifdef CONFIG_PM +/* no CP0 timer irq */ +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) +#else +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) +#endif + /* SDRAM Controller */ -#define CS_MODE_0 0x14000000 -#define CS_MODE_1 0x14000004 -#define CS_MODE_2 0x14000008 - -#define CS_CONFIG_0 0x1400000C -#define CS_CONFIG_1 0x14000010 -#define CS_CONFIG_2 0x14000014 - -#define REFRESH_CONFIG 0x14000018 -#define PRECHARGE_CMD 0x1400001C -#define AUTO_REFRESH_CMD 0x14000020 - -#define WRITE_EXTERN_0 0x14000024 -#define WRITE_EXTERN_1 0x14000028 -#define WRITE_EXTERN_2 0x1400002C +#define MEM_SDMODE0 0xB4000000 +#define MEM_SDMODE1 0xB4000004 +#define MEM_SDMODE2 0xB4000008 + +#define MEM_SDADDR0 0xB400000C +#define MEM_SDADDR1 0xB4000010 +#define MEM_SDADDR2 0xB4000014 + +#define MEM_SDREFCFG 0xB4000018 +#define MEM_SDPRECMD 0xB400001C +#define MEM_SDAUTOREF 0xB4000020 + +#define MEM_SDWRMD0 0xB4000024 +#define MEM_SDWRMD1 0xB4000028 +#define MEM_SDWRMD2 0xB400002C -#define SDRAM_SLEEP 0x14000030 -#define TOGGLE_CKE 0x14000034 +#define MEM_SDSLEEP 0xB4000030 +#define MEM_SDSMCKE 0xB4000034 /* Static Bus Controller */ -#define STATIC_CONFIG_0 0x14001000 -#define STATIC_TIMING_0 0x14001004 -#define STATIC_ADDRESS_0 0x14001008 - -#define STATIC_CONFIG_1 0x14001010 -#define STATIC_TIMING_1 0x14001014 -#define STATIC_ADDRESS_1 0x14001018 - -#define STATIC_CONFIG_2 0x14001020 -#define STATIC_TIMING_2 0x14001024 -#define STATIC_ADDRESS_2 0x14001028 - -#define STATIC_CONFIG_3 0x14001030 -#define STATIC_TIMING_3 0x14001034 -#define STATIC_ADDRESS_3 0x14001038 - -/* DMA Controller 0 */ -#define DMA0_MODE_SET 0x14002000 -#define DMA0_MODE_CLEAR 0x14002004 -#define DMA0_PERIPHERAL_ADDR 0x14002008 -#define DMA0_BUFFER0_START 0x1400200C -#define DMA0_BUFFER0_COUNT 0x14002010 -#define DMA0_BUFFER1_START 0x14002014 -#define DMA0_BUFFER1_COUNT 0x14002018 - -/* DMA Controller 1 */ -#define DMA1_MODE_SET 0x14002100 -#define DMA1_MODE_CLEAR 0x14002104 -#define DMA1_PERIPHERAL_ADDR 0x14002108 -#define DMA1_BUFFER0_START 0x1400210C -#define DMA1_BUFFER0_COUNT 0x14002110 -#define DMA1_BUFFER1_START 0x14002114 -#define DMA1_BUFFER1_COUNT 0x14002118 - -/* DMA Controller 2 */ -#define DMA2_MODE_SET 0x14002200 -#define DMA2_MODE_CLEAR 0x14002204 -#define DMA2_PERIPHERAL_ADDR 0x14002208 -#define DMA2_BUFFER0_START 0x1400220C -#define DMA2_BUFFER0_COUNT 0x14002210 -#define DMA2_BUFFER1_START 0x14002214 -#define DMA2_BUFFER1_COUNT 0x14002218 - -/* DMA Controller 3 */ -#define DMA3_MODE_SET 0x14002300 -#define DMA3_MODE_CLEAR 0x14002304 -#define DMA3_PERIPHERAL_ADDR 0x14002308 -#define DMA3_BUFFER0_START 0x1400230C -#define DMA3_BUFFER0_COUNT 0x14002310 -#define DMA3_BUFFER1_START 0x14002314 -#define DMA3_BUFFER1_COUNT 0x14002318 - -/* DMA Controller 4 */ -#define DMA4_MODE_SET 0x14002400 -#define DMA4_MODE_CLEAR 0x14002404 -#define DMA4_PERIPHERAL_ADDR 0x14002408 -#define DMA4_BUFFER0_START 0x1400240C -#define DMA4_BUFFER0_COUNT 0x14002410 -#define DMA4_BUFFER1_START 0x14002414 -#define DMA4_BUFFER1_COUNT 0x14002418 - -/* DMA Controller 5 */ -#define DMA5_MODE_SET 0x14002500 -#define DMA5_MODE_CLEAR 0x14002504 -#define DMA5_PERIPHERAL_ADDR 0x14002508 -#define DMA5_BUFFER0_START 0x1400250C -#define DMA5_BUFFER0_COUNT 0x14002510 -#define DMA5_BUFFER1_START 0x14002514 -#define DMA5_BUFFER1_COUNT 0x14002518 - -/* DMA Controller 6 */ -#define DMA6_MODE_SET 0x14002600 -#define DMA6_MODE_CLEAR 0x14002604 -#define DMA6_PERIPHERAL_ADDR 0x14002608 -#define DMA6_BUFFER0_START 0x1400260C -#define DMA6_BUFFER0_COUNT 0x14002610 -#define DMA6_BUFFER1_START 0x14002614 -#define DMA6_BUFFER1_COUNT 0x14002618 - -/* DMA Controller 7 */ -#define DMA7_MODE_SET 0x14002700 -#define DMA7_MODE_CLEAR 0x14002704 -#define DMA7_PERIPHERAL_ADDR 0x14002708 -#define DMA7_BUFFER0_START 0x1400270C -#define DMA7_BUFFER0_COUNT 0x14002710 -#define DMA7_BUFFER1_START 0x14002714 -#define DMA7_BUFFER1_COUNT 0x14002718 +#define MEM_STCFG0 0xB4001000 +#define MEM_STTIME0 0xB4001004 +#define MEM_STADDR0 0xB4001008 + +#define MEM_STCFG1 0xB4001010 +#define MEM_STTIME1 0xB4001014 +#define MEM_STADDR1 0xB4001018 + +#define MEM_STCFG2 0xB4001020 +#define MEM_STTIME2 0xB4001024 +#define MEM_STADDR2 0xB4001028 + +#define MEM_STCFG3 0xB4001030 +#define MEM_STTIME3 0xB4001034 +#define MEM_STADDR3 0xB4001038 /* Interrupt Controller 0 */ -#define INTC0_CONFIG0_READ 0x10400040 -#define INTC0_CONFIG0_SET 0x10400040 -#define INTC0_CONFIG0_CLEAR 0x10400044 - -#define INTC0_CONFIG1_READ 0x10400048 -#define INTC0_CONFIG1_SET 0x10400048 -#define INTC0_CONFIG1_CLEAR 0x1040004C - -#define INTC0_CONFIG2_READ 0x10400050 -#define INTC0_CONFIG2_SET 0x10400050 -#define INTC0_CONFIG2_CLEAR 0x10400054 - -#define INTC0_REQ0_INT 0x10400054 -#define INTC0_SOURCE_READ 0x10400058 -#define INTC0_SOURCE_SET 0x10400058 -#define INTC0_SOURCE_CLEAR 0x1040005C -#define INTC0_REQ1_INT 0x1040005C - -#define INTC0_ASSIGN_REQ_READ 0x10400060 -#define INTC0_ASSIGN_REQ_SET 0x10400060 -#define INTC0_ASSIGN_REQ_CLEAR 0x10400064 - -#define INTC0_WAKEUP_READ 0x10400068 -#define INTC0_WAKEUP_SET 0x10400068 -#define INTC0_WAKEUP_CLEAR 0x1040006C - -#define INTC0_MASK_READ 0x10400070 -#define INTC0_MASK_SET 0x10400070 -#define INTC0_MASK_CLEAR 0x10400074 - -#define INTC0_R_EDGE_DETECT 0x10400078 -#define INTC0_R_EDGE_DETECT_CLEAR 0x10400078 -#define INTC0_F_EDGE_DETECT_CLEAR 0x1040007C +#define IC0_CFG0RD 0xB0400040 +#define IC0_CFG0SET 0xB0400040 +#define IC0_CFG0CLR 0xB0400044 + +#define IC0_CFG1RD 0xB0400048 +#define IC0_CFG1SET 0xB0400048 +#define IC0_CFG1CLR 0xB040004C + +#define IC0_CFG2RD 0xB0400050 +#define IC0_CFG2SET 0xB0400050 +#define IC0_CFG2CLR 0xB0400054 + +#define IC0_REQ0INT 0xB0400054 +#define IC0_SRCRD 0xB0400058 +#define IC0_SRCSET 0xB0400058 +#define IC0_SRCCLR 0xB040005C +#define IC0_REQ1INT 0xB040005C + +#define IC0_ASSIGNRD 0xB0400060 +#define IC0_ASSIGNSET 0xB0400060 +#define IC0_ASSIGNCLR 0xB0400064 + +#define IC0_WAKERD 0xB0400068 +#define IC0_WAKESET 0xB0400068 +#define IC0_WAKECLR 0xB040006C + +#define IC0_MASKRD 0xB0400070 +#define IC0_MASKSET 0xB0400070 +#define IC0_MASKCLR 0xB0400074 + +#define IC0_RISINGRD 0xB0400078 +#define IC0_RISINGCLR 0xB0400078 +#define IC0_FALLINGRD 0xB040007C +#define IC0_FALLINGCLR 0xB040007C -#define INTC0_TEST_BIT 0x10400080 +#define IC0_TESTBIT 0xB0400080 /* Interrupt Controller 1 */ -#define INTC1_CONFIG0_READ 0x11800040 -#define INTC1_CONFIG0_SET 0x11800040 -#define INTC1_CONFIG0_CLEAR 0x11800044 - -#define INTC1_CONFIG1_READ 0x11800048 -#define INTC1_CONFIG1_SET 0x11800048 -#define INTC1_CONFIG1_CLEAR 0x1180004C - -#define INTC1_CONFIG2_READ 0x11800050 -#define INTC1_CONFIG2_SET 0x11800050 -#define INTC1_CONFIG2_CLEAR 0x11800054 - -#define INTC1_REQ0_INT 0x11800054 -#define INTC1_SOURCE_READ 0x11800058 -#define INTC1_SOURCE_SET 0x11800058 -#define INTC1_SOURCE_CLEAR 0x1180005C -#define INTC1_REQ1_INT 0x1180005C - -#define INTC1_ASSIGN_REQ_READ 0x11800060 -#define INTC1_ASSIGN_REQ_SET 0x11800060 -#define INTC1_ASSIGN_REQ_CLEAR 0x11800064 - -#define INTC1_WAKEUP_READ 0x11800068 -#define INTC1_WAKEUP_SET 0x11800068 -#define INTC1_WAKEUP_CLEAR 0x1180006C - -#define INTC1_MASK_READ 0x11800070 -#define INTC1_MASK_SET 0x11800070 -#define INTC1_MASK_CLEAR 0x11800074 - -#define INTC1_R_EDGE_DETECT 0x11800078 -#define INTC1_R_EDGE_DETECT_CLEAR 0x11800078 -#define INTC1_F_EDGE_DETECT_CLEAR 0x1180007C +#define IC1_CFG0RD 0xB1800040 +#define IC1_CFG0SET 0xB1800040 +#define IC1_CFG0CLR 0xB1800044 + +#define IC1_CFG1RD 0xB1800048 +#define IC1_CFG1SET 0xB1800048 +#define IC1_CFG1CLR 0xB180004C + +#define IC1_CFG2RD 0xB1800050 +#define IC1_CFG2SET 0xB1800050 +#define IC1_CFG2CLR 0xB1800054 + +#define IC1_REQ0INT 0xB1800054 +#define IC1_SRCRD 0xB1800058 +#define IC1_SRCSET 0xB1800058 +#define IC1_SRCCLR 0xB180005C +#define IC1_REQ1INT 0xB180005C + +#define IC1_ASSIGNRD 0xB1800060 +#define IC1_ASSIGNSET 0xB1800060 +#define IC1_ASSIGNCLR 0xB1800064 + +#define IC1_WAKERD 0xB1800068 +#define IC1_WAKESET 0xB1800068 +#define IC1_WAKECLR 0xB180006C + +#define IC1_MASKRD 0xB1800070 +#define IC1_MASKSET 0xB1800070 +#define IC1_MASKCLR 0xB1800074 + +#define IC1_RISINGRD 0xB1800078 +#define IC1_RISINGCLR 0xB1800078 +#define IC1_FALLINGRD 0xB180007C +#define IC1_FALLINGCLR 0xB180007C -#define INTC1_TEST_BIT 0x11800080 +#define IC1_TESTBIT 0xB1800080 /* Interrupt Configuration Modes */ #define INTC_INT_DISABLED 0 @@ -225,29 +213,31 @@ /* Interrupt Numbers */ #define AU1000_UART0_INT 0 -#define AU1000_UART1_INT 1 -#define AU1000_UART2_INT 2 +#define AU1000_UART1_INT 1 /* au1000 */ +#define AU1000_UART2_INT 2 /* au1000 */ + +#define AU1000_PCI_INTA 1 /* au1500 */ +#define AU1000_PCI_INTB 2 /* au1500 */ + #define AU1000_UART3_INT 3 -#define AU1000_SSI0_INT 4 -#define AU1000_SSI1_INT 5 -#define AU1000_DMA0_INT 6 -#define AU1000_DMA1_INT 7 -#define AU1000_DMA2_INT 8 -#define AU1000_DMA3_INT 9 -#define AU1000_DMA4_INT 10 -#define AU1000_DMA5_INT 11 -#define AU1000_DMA6_INT 12 -#define AU1000_DMA7_INT 13 -#define AU1000_PC0_INT 14 -#define AU1000_PC0_MATCH0_INT 15 -#define AU1000_PC0_MATCH1_INT 16 -#define AU1000_PC0_MATCH2_INT 17 -#define AU1000_PC1_INT 18 -#define AU1000_PC1_MATCH0_INT 19 -#define AU1000_PC1_MATCH1_INT 20 -#define AU1000_PC1_MATCH2_INT 21 -#define AU1000_IRDA_TX_INT 22 -#define AU1000_IRDA_RX_INT 23 + +#define AU1000_SSI0_INT 4 /* au1000 */ +#define AU1000_SSI1_INT 5 /* au1000 */ + +#define AU1000_PCI_INTC 4 /* au1500 */ +#define AU1000_PCI_INTD 5 /* au1500 */ + +#define AU1000_DMA_INT_BASE 6 +#define AU1000_TOY_INT 14 +#define AU1000_TOY_MATCH0_INT 15 +#define AU1000_TOY_MATCH1_INT 16 +#define AU1000_TOY_MATCH2_INT 17 +#define AU1000_RTC_INT 18 +#define AU1000_RTC_MATCH0_INT 19 +#define AU1000_RTC_MATCH1_INT 20 +#define AU1000_RTC_MATCH2_INT 21 +#define AU1000_IRDA_TX_INT 22 /* au1000 */ +#define AU1000_IRDA_RX_INT 23 /* au1000 */ #define AU1000_USB_DEV_REQ_INT 24 #define AU1000_USB_DEV_SUS_INT 25 #define AU1000_USB_HOST_INT 26 @@ -256,9 +246,9 @@ #define AU1000_MAC1_DMA_INT 29 #define AU1000_ETH0_IRQ AU1000_MAC0_DMA_INT #define AU1000_ETH1_IRQ AU1000_MAC1_DMA_INT -#define AU1000_I2S_UO_INT 30 -#define AU1000_AC97_INT 31 -#define AU1000_LAST_INTC0_INT AU1000_AC97_INT +#define AU1000_I2S_UO_INT 30 /* au1000 */ +#define AU1000_AC97C_INT 31 +#define AU1000_LAST_INTC0_INT AU1000_AC97C_INT #define AU1000_GPIO_0 32 #define AU1000_GPIO_1 33 #define AU1000_GPIO_2 34 @@ -275,6 +265,8 @@ #define AU1000_GPIO_13 45 #define AU1000_GPIO_14 46 #define AU1000_GPIO_15 47 + +/* Au1000 only */ #define AU1000_GPIO_16 48 #define AU1000_GPIO_17 49 #define AU1000_GPIO_18 50 @@ -292,54 +284,149 @@ #define AU1000_GPIO_30 62 #define AU1000_GPIO_31 63 +/* Au1500 only */ +#define AU1500_GPIO_200 48 +#define AU1500_GPIO_201 49 +#define AU1500_GPIO_202 50 +#define AU1500_GPIO_203 51 +#define AU1500_GPIO_20 52 +#define AU1500_GPIO_204 53 +#define AU1500_GPIO_205 54 +#define AU1500_GPIO_23 55 +#define AU1500_GPIO_24 56 +#define AU1500_GPIO_25 57 +#define AU1500_GPIO_26 58 +#define AU1500_GPIO_27 59 +#define AU1500_GPIO_28 60 +#define AU1500_GPIO_206 61 +#define AU1500_GPIO_207 62 +#define AU1500_GPIO_208_215 63 + +#define AU1000_MAX_INTR 63 + /* Programmable Counters 0 and 1 */ -#define PC_BASE 0x11900000 -#define PC_COUNTER_CNTRL (PC_BASE + 0x14) - #define PC_CNTRL_E1S (1<<23) - #define PC_CNTRL_T1S (1<<20) - #define PC_CNTRL_M21 (1<<19) - #define PC_CNTRL_M11 (1<<18) - #define PC_CNTRL_M01 (1<<17) - #define PC_CNTRL_C1S (1<<16) - #define PC_CNTRL_BP (1<<14) - #define PC_CNTRL_EN1 (1<<13) - #define PC_CNTRL_BT1 (1<<12) - #define PC_CNTRL_EN0 (1<<11) - #define PC_CNTRL_BT0 (1<<10) - #define PC_CNTRL_E0 (1<<8) - #define PC_CNTRL_E0S (1<<7) - #define PC_CNTRL_32S (1<<5) - #define PC_CNTRL_T0S (1<<4) - #define PC_CNTRL_M20 (1<<3) - #define PC_CNTRL_M10 (1<<2) - #define PC_CNTRL_M00 (1<<1) - #define PC_CNTRL_C0S (1<<0) +#define SYS_BASE 0xB1900000 +#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) + #define SYS_CNTRL_E1S (1<<23) + #define SYS_CNTRL_T1S (1<<20) + #define SYS_CNTRL_M21 (1<<19) + #define SYS_CNTRL_M11 (1<<18) + #define SYS_CNTRL_M01 (1<<17) + #define SYS_CNTRL_C1S (1<<16) + #define SYS_CNTRL_BP (1<<14) + #define SYS_CNTRL_EN1 (1<<13) + #define SYS_CNTRL_BT1 (1<<12) + #define SYS_CNTRL_EN0 (1<<11) + #define SYS_CNTRL_BT0 (1<<10) + #define SYS_CNTRL_E0 (1<<8) + #define SYS_CNTRL_E0S (1<<7) + #define SYS_CNTRL_32S (1<<5) + #define SYS_CNTRL_T0S (1<<4) + #define SYS_CNTRL_M20 (1<<3) + #define SYS_CNTRL_M10 (1<<2) + #define SYS_CNTRL_M00 (1<<1) + #define SYS_CNTRL_C0S (1<<0) /* Programmable Counter 0 Registers */ -#define PC0_TRIM (PC_BASE + 0) -#define PC0_COUNTER_WRITE (PC_BASE + 4) -#define PC0_MATCH0 (PC_BASE + 8) -#define PC0_MATCH1 (PC_BASE + 0xC) -#define PC0_MATCH2 (PC_BASE + 0x10) -#define PC0_COUNTER_READ (PC_BASE + 0x40) +#define SYS_TOYTRIM (SYS_BASE + 0) +#define SYS_TOYWRITE (SYS_BASE + 4) +#define SYS_TOYMATCH0 (SYS_BASE + 8) +#define SYS_TOYMATCH1 (SYS_BASE + 0xC) +#define SYS_TOYMATCH2 (SYS_BASE + 0x10) +#define SYS_TOYREAD (SYS_BASE + 0x40) /* Programmable Counter 1 Registers */ -#define PC1_TRIM (PC_BASE + 0x44) -#define PC1_COUNTER_WRITE (PC_BASE + 0x48) -#define PC1_MATCH0 (PC_BASE + 0x4C) -#define PC1_MATCH1 (PC_BASE + 0x50) -#define PC1_MATCH2 (PC_BASE + 0x54) -#define PC1_COUNTER_READ (PC_BASE + 0x58) - +#define SYS_RTCTRIM (SYS_BASE + 0x44) +#define SYS_RTCWRITE (SYS_BASE + 0x48) +#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) +#define SYS_RTCMATCH1 (SYS_BASE + 0x50) +#define SYS_RTCMATCH2 (SYS_BASE + 0x54) +#define SYS_RTCREAD (SYS_BASE + 0x58) /* I2S Controller */ -#define I2S_DATA 0x11000000 -#define I2S_CONFIG_STATUS 0x11000001 -#define I2S_CONTROL 0x11000002 +#define I2S_DATA 0xB1000000 + #define I2S_DATA_MASK (0xffffff) +#define I2S_CONFIG 0xB1000004 + #define I2S_CONFIG_XU (1<<25) + #define I2S_CONFIG_XO (1<<24) + #define I2S_CONFIG_RU (1<<23) + #define I2S_CONFIG_RO (1<<22) + #define I2S_CONFIG_TR (1<<21) + #define I2S_CONFIG_TE (1<<20) + #define I2S_CONFIG_TF (1<<19) + #define I2S_CONFIG_RR (1<<18) + #define I2S_CONFIG_RE (1<<17) + #define I2S_CONFIG_RF (1<<16) + #define I2S_CONFIG_PD (1<<11) + #define I2S_CONFIG_LB (1<<10) + #define I2S_CONFIG_IC (1<<9) + #define I2S_CONFIG_FM_BIT 7 + #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) + #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) + #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) + #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) + #define I2S_CONFIG_TN (1<<6) + #define I2S_CONFIG_RN (1<<5) + #define I2S_CONFIG_SZ_BIT 0 + #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) + +#define I2S_CONTROL 0xB1000008 + #define I2S_CONTROL_D (1<<1) + #define I2S_CONTROL_CE (1<<0) + +/* USB Host Controller */ +// We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address +#define USB_OHCI_BASE 0x10100000 +#define USB_OHCI_LEN 0x00100000 +#define USB_HOST_CONFIG 0xB017fffc + +/* USB Device Controller */ +#define USBD_EP0RD 0xB0200000 +#define USBD_EP0WR 0xB0200004 +#define USBD_EP2WR 0xB0200008 +#define USBD_EP3WR 0xB020000C +#define USBD_EP4RD 0xB0200010 +#define USBD_EP5RD 0xB0200014 +#define USBD_INTEN 0xB0200018 +#define USBD_INTSTAT 0xB020001C + #define USBDEV_INT_SOF (1<<12) + #define USBDEV_INT_HF_BIT 6 + #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) + #define USBDEV_INT_CMPLT_BIT 0 + #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) +#define USBD_CONFIG 0xB0200020 +#define USBD_EP0CS 0xB0200024 +#define USBD_EP2CS 0xB0200028 +#define USBD_EP3CS 0xB020002C +#define USBD_EP4CS 0xB0200030 +#define USBD_EP5CS 0xB0200034 + #define USBDEV_CS_SU (1<<14) + #define USBDEV_CS_NAK (1<<13) + #define USBDEV_CS_ACK (1<<12) + #define USBDEV_CS_BUSY (1<<11) + #define USBDEV_CS_TSIZE_BIT 1 + #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) + #define USBDEV_CS_STALL (1<<0) +#define USBD_EP0RDSTAT 0xB0200040 +#define USBD_EP0WRSTAT 0xB0200044 +#define USBD_EP2WRSTAT 0xB0200048 +#define USBD_EP3WRSTAT 0xB020004C +#define USBD_EP4RDSTAT 0xB0200050 +#define USBD_EP5RDSTAT 0xB0200054 + #define USBDEV_FSTAT_FLUSH (1<<6) + #define USBDEV_FSTAT_UF (1<<5) + #define USBDEV_FSTAT_OF (1<<4) + #define USBDEV_FSTAT_FCNT_BIT 0 + #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) +#define USBD_ENABLE 0xB0200058 + #define USBDEV_ENABLE (1<<1) + #define USBDEV_CE (1<<0) /* Ethernet Controllers */ -#define AU1000_ETH0_BASE 0x10500000 -#define AU1000_ETH1_BASE 0x10510000 +#define AU1000_ETH0_BASE 0xB0500000 +#define AU1000_ETH1_BASE 0xB0510000 +#define AU1500_ETH0_BASE 0xB1500000 +#define AU1500_ETH1_BASE 0xB1510000 /* 4 byte offsets from AU1000_ETH_BASE */ #define MAC_CONTROL 0x0 @@ -384,11 +471,13 @@ #define MAC_VLAN2_TAG 0x24 /* Ethernet Controller Enable */ -#define MAC0_ENABLE 0x10520000 -#define MAC1_ENABLE 0x10520004 +#define AU1000_MAC0_ENABLE 0xB0520000 +#define AU1000_MAC1_ENABLE 0xB0520004 +#define AU1500_MAC0_ENABLE 0xB1520000 +#define AU1500_MAC1_ENABLE 0xB1520004 #define MAC_EN_CLOCK_ENABLE (1<<0) #define MAC_EN_RESET0 (1<<1) - #define MAC_EN_TOSS (1<<2) + #define MAC_EN_TOSS (0<<2) #define MAC_EN_CACHEABLE (1<<3) #define MAC_EN_RESET1 (1<<4) #define MAC_EN_RESET2 (1<<5) @@ -396,8 +485,8 @@ /* Ethernet Controller DMA Channels */ -#define MAC0_TX_DMA_ADDR 0x14004000 -#define MAC1_TX_DMA_ADDR 0x14004200 +#define MAC0_TX_DMA_ADDR 0xB4004000 +#define MAC1_TX_DMA_ADDR 0xB4004200 /* offsets from MAC_TX_RING_ADDR address */ #define MAC_TX_BUFF0_STATUS 0x0 #define TX_FRAME_ABORTED (1<<0) @@ -427,8 +516,8 @@ #define MAC_TX_BUFF3_ADDR 0x34 #define MAC_TX_BUFF3_LEN 0x38 -#define MAC0_RX_DMA_ADDR 0x14004100 -#define MAC1_RX_DMA_ADDR 0x14004300 +#define MAC0_RX_DMA_ADDR 0xB4004100 +#define MAC1_RX_DMA_ADDR 0xB4004300 /* offsets from MAC_RX_RING_ADDR */ #define MAC_RX_BUFF0_STATUS 0x0 #define RX_FRAME_LEN_MASK 0x3fff @@ -468,10 +557,11 @@ /* UARTS 0-3 */ -#define UART0_ADDR 0x11100000 -#define UART1_ADDR 0x11200000 -#define UART2_ADDR 0x11300000 -#define UART3_ADDR 0x11400000 +#define UART_BASE 0xB1100000 +#define UART0_ADDR 0xB1100000 +#define UART1_ADDR 0xB1200000 +#define UART2_ADDR 0xB1300000 +#define UART3_ADDR 0xB1400000 #define UART_RX 0 /* Receive buffer */ #define UART_TX 4 /* Transmit buffer */ @@ -482,7 +572,7 @@ #define UART_MCR 0x18 /* Modem Control Register */ #define UART_LSR 0x1C /* Line Status Register */ #define UART_MSR 0x20 /* Modem Status Register */ -#define UART_CLK 0x28 /* Baud Rat4e Clock Divider */ +#define UART_CLK 0x28 /* Baud Rate Clock Divider */ #define UART_MOD_CNTRL 0x100 /* Module Control */ #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ @@ -566,70 +656,256 @@ /* SSIO */ -#define SSI0_STATUS 0x11600000 -#define SSI0_INT 0x11600004 -#define SSI0_INT_ENABLE 0x11600008 -#define SSI0_CONFIG 0x11600020 -#define SSI0_ADATA 0x11600024 -#define SSI0_CLKDIV 0x11600028 -#define SSI0_CONTROL 0x11600100 +#define SSI0_STATUS 0xB1600000 + #define SSI_STATUS_BF (1<<4) + #define SSI_STATUS_OF (1<<3) + #define SSI_STATUS_UF (1<<2) + #define SSI_STATUS_D (1<<1) + #define SSI_STATUS_B (1<<0) +#define SSI0_INT 0xB1600004 + #define SSI_INT_OI (1<<3) + #define SSI_INT_UI (1<<2) + #define SSI_INT_DI (1<<1) +#define SSI0_INT_ENABLE 0xB1600008 + #define SSI_INTE_OIE (1<<3) + #define SSI_INTE_UIE (1<<2) + #define SSI_INTE_DIE (1<<1) +#define SSI0_CONFIG 0xB1600020 + #define SSI_CONFIG_AO (1<<24) + #define SSI_CONFIG_DO (1<<23) + #define SSI_CONFIG_ALEN_BIT 20 + #define SSI_CONFIG_ALEN_MASK (0x7<<20) + #define SSI_CONFIG_DLEN_BIT 16 + #define SSI_CONFIG_DLEN_MASK (0x7<<16) + #define SSI_CONFIG_DD (1<<11) + #define SSI_CONFIG_AD (1<<10) + #define SSI_CONFIG_BM_BIT 8 + #define SSI_CONFIG_BM_MASK (0x3<<8) + #define SSI_CONFIG_CE (1<<7) + #define SSI_CONFIG_DP (1<<6) + #define SSI_CONFIG_DL (1<<5) + #define SSI_CONFIG_EP (1<<4) +#define SSI0_ADATA 0xB1600024 + #define SSI_AD_D (1<<24) + #define SSI_AD_ADDR_BIT 16 + #define SSI_AD_ADDR_MASK (0xff<<16) + #define SSI_AD_DATA_BIT 0 + #define SSI_AD_DATA_MASK (0xfff<<0) +#define SSI0_CLKDIV 0xB1600028 +#define SSI0_CONTROL 0xB1600100 + #define SSI_CONTROL_CD (1<<1) + #define SSI_CONTROL_E (1<<0) /* SSI1 */ -#define SSI1_STATUS 0x11680000 -#define SSI1_INT 0x11680004 -#define SSI1_INT_ENABLE 0x11680008 -#define SSI1_CONFIG 0x11680020 -#define SSI1_ADATA 0x11680024 -#define SSI1_CLKDIV 0x11680028 -#define SSI1_CONTROL 0x11680100 +#define SSI1_STATUS 0xB1680000 +#define SSI1_INT 0xB1680004 +#define SSI1_INT_ENABLE 0xB1680008 +#define SSI1_CONFIG 0xB1680020 +#define SSI1_ADATA 0xB1680024 +#define SSI1_CLKDIV 0xB1680028 +#define SSI1_CONTROL 0xB1680100 /* IrDA Controller */ -#define IR_RING_PTR_STATUS 0x11500000 -#define IR_RING_BASE_ADDR_H 0x11500004 -#define IR_RING_BASE_ADDR_L 0x11500008 -#define IR_RING_SIZE 0x1150000C -#define IR_RING_PROMPT 0x11500010 -#define IR_RING_ADDR_CMPR 0x11500014 -#define IR_CONFIG_1 0x11500020 -#define IR_SIR_FLAGS 0x11500024 -#define IR_ENABLE 0x11500028 -#define IR_READ_PHY_CONFIG 0x1150002C -#define IR_WRITE_PHY_CONFIG 0x11500030 -#define IR_MAX_PKT_LEN 0x11500034 -#define IR_RX_BYTE_CNT 0x11500038 -#define IR_CONFIG_2 0x1150003C -#define IR_INTERFACE_CONFIG 0x11500040 +#define IRDA_BASE 0xB0300000 +#define IR_RING_PTR_STATUS (IRDA_BASE+0x00) +#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) +#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) +#define IR_RING_SIZE (IRDA_BASE+0x0C) +#define IR_RING_PROMPT (IRDA_BASE+0x10) +#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) +#define IR_INT_CLEAR (IRDA_BASE+0x18) +#define IR_CONFIG_1 (IRDA_BASE+0x20) + #define IR_RX_INVERT_LED (1<<0) + #define IR_TX_INVERT_LED (1<<1) + #define IR_ST (1<<2) + #define IR_SF (1<<3) + #define IR_SIR (1<<4) + #define IR_MIR (1<<5) + #define IR_FIR (1<<6) + #define IR_16CRC (1<<7) + #define IR_TD (1<<8) + #define IR_RX_ALL (1<<9) + #define IR_DMA_ENABLE (1<<10) + #define IR_RX_ENABLE (1<<11) + #define IR_TX_ENABLE (1<<12) + #define IR_LOOPBACK (1<<14) + #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ + IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) +#define IR_SIR_FLAGS (IRDA_BASE+0x24) +#define IR_ENABLE (IRDA_BASE+0x28) + #define IR_RX_STATUS (1<<9) + #define IR_TX_STATUS (1<<10) +#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) +#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) +#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) +#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) +#define IR_CONFIG_2 (IRDA_BASE+0x3C) + #define IR_MODE_INV (1<<0) + #define IR_ONE_PIN (1<<1) +#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) /* GPIO */ -#define TSTATE_STATE_READ 0x11900100 -#define TSTATE_STATE_SET 0x11900100 -#define OUTPUT_STATE_READ 0x11900108 -#define OUTPUT_STATE_SET 0x11900108 -#define OUTPUT_STATE_CLEAR 0x1190010C -#define PIN_STATE 0x11900110 +#define SYS_PINFUNC 0xB190002C + #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ + #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ + #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ + #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ + #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ + #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ + #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ + #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ + #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ + #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ + #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ + #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ + #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ + #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ + #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ + #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ +#define SYS_TRIOUTRD 0xB1900100 +#define SYS_TRIOUTCLR 0xB1900100 +#define SYS_OUTPUTRD 0xB1900108 +#define SYS_OUTPUTSET 0xB1900108 +#define SYS_OUTPUTCLR 0xB190010C +#define SYS_PINSTATERD 0xB1900110 + +/* GPIO2, Au1500 only */ +#define GPIO2_BASE 0xB1700000 +#define GPIO2_DIR (GPIO2_BASE + 0) +#define GPIO2_DATA_EN (GPIO2_BASE + 8) +#define GPIO2_PIN_STATE (GPIO2_BASE + 0xC) +#define GPIO2_INT_MASK (GPIO2_BASE + 0x10) +#define GPIO2_CONTROL (GPIO2_BASE + 0x14) /* Power Management */ -#define PM_SCRATCH_0 0x11900018 -#define PM_SCRATCH_1 0x1190001C -#define PM_WAKEUP_SOURCE_MASK 0x11900034 -#define PM_ENDIANESS 0x11900038 -#define PM_POWERUP_CONTROL 0x1190003C -#define PM_WAKEUP_CAUSE 0x1190005C -#define PM_SLEEP_POWER 0x11900078 -#define PM_SLEEP 0x1190007C +#define SYS_SCRATCH0 0xB1900018 +#define SYS_SCRATCH1 0xB190001C +#define SYS_WAKEMSK 0xB1900034 +#define SYS_ENDIAN 0xB1900038 +#define SYS_POWERCTRL 0xB190003C +#define SYS_WAKESRC 0xB190005C +#define SYS_SLPPWR 0xB1900078 +#define SYS_SLEEP 0xB190007C /* Clock Controller */ -#define FQ_CNTRL_1 0x11900020 -#define FQ_CNTRL_2 0x11900024 -#define CLOCK_SOURCE_CNTRL 0x11900028 -#define CPU_PLL_CNTRL 0x11900060 -#define AUX_PLL_CNTRL 0x11900064 +#define SYS_FREQCTRL0 0xB1900020 + #define SYS_FC_FRDIV2_BIT 22 + #define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT) + #define SYS_FC_FE2 (1<<21) + #define SYS_FC_FS2 (1<<20) + #define SYS_FC_FRDIV1_BIT 12 + #define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT) + #define SYS_FC_FE1 (1<<11) + #define SYS_FC_FS1 (1<<10) + #define SYS_FC_FRDIV0_BIT 2 + #define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT) + #define SYS_FC_FE0 (1<<1) + #define SYS_FC_FS0 (1<<0) +#define SYS_FREQCTRL1 0xB1900024 + #define SYS_FC_FRDIV5_BIT 22 + #define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT) + #define SYS_FC_FE5 (1<<21) + #define SYS_FC_FS5 (1<<20) + #define SYS_FC_FRDIV4_BIT 12 + #define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT) + #define SYS_FC_FE4 (1<<11) + #define SYS_FC_FS4 (1<<10) + #define SYS_FC_FRDIV3_BIT 2 + #define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT) + #define SYS_FC_FE3 (1<<1) + #define SYS_FC_FS3 (1<<0) +#define SYS_CLKSRC 0xB1900028 + #define SYS_CS_ME1_BIT 27 + #define SYS_CS_ME1_MASK (0x7<