--- zzzz-none-000/linux-2.4.17/include/asm-mips/bcache.h	2001-07-02 20:56:40.000000000 +0000
+++ sangam-fb-322/linux-2.4.17/include/asm-mips/bcache.h	2004-11-24 13:21:30.000000000 +0000
@@ -3,8 +3,8 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 1997, 1999, 2000 by Ralf Baechle
- * Copyright (c) 2000 by Silicon Graphics, Inc.
+ * Copyright (c) 1997, 1999 by Ralf Baechle
+ * Copyright (c) 1999 Silicon Graphics, Inc.
  */
 #ifndef _ASM_BCACHE_H
 #define _ASM_BCACHE_H
@@ -12,7 +12,7 @@
 #include <linux/config.h>
 
 /* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
-   chipset implemented caches.  On machines with other CPUs the CPU does the
+   chipset implemented caches.  On machines with other CPUs the CPU does the 
    cache thing itself. */
 struct bcache_ops {
 	void (*bc_enable)(void);
@@ -28,22 +28,22 @@
 
 extern struct bcache_ops *bcops;
 
-extern inline void bc_enable(void)
+static inline void bc_enable(void)
 {
 	bcops->bc_enable();
 }
 
-extern inline void bc_disable(void)
+static inline void bc_disable(void)
 {
 	bcops->bc_disable();
 }
 
-extern inline void bc_wback_inv(unsigned long page, unsigned long size)
+static inline void bc_wback_inv(unsigned long page, unsigned long size)
 {
 	bcops->bc_wback_inv(page, size);
 }
 
-extern inline void bc_inv(unsigned long page, unsigned long size)
+static inline void bc_inv(unsigned long page, unsigned long size)
 {
 	bcops->bc_inv(page, size);
 }