--- zzzz-none-000/linux-2.4.17/include/asm-mips/io.h 2001-09-09 17:43:01.000000000 +0000 +++ sangam-fb-322/linux-2.4.17/include/asm-mips/io.h 2004-11-24 13:21:31.000000000 +0000 @@ -13,8 +13,12 @@ #include #include +#include #include #include +#ifdef CONFIG_TOSHIBA_JMR3927 +#include +#endif /* * Slowdown I/O port space accesses for antique hardware. @@ -40,27 +44,17 @@ #endif /* - * This file contains the definitions for the MIPS counterpart of the - * x86 in/out instructions. This heap of macros and C results in much - * better code than the approach of doing it in plain C. The macros - * result in code that is to fast for certain hardware. On the other - * side the performance of the string functions should be improved for - * sake of certain devices like EIDE disks that do highspeed polled I/O. - * - * Ralf - * - * This file contains the definitions for the x86 IO instructions - * inb/inw/inl/outb/outw/outl and the "string versions" of the same - * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" - * versions of the single-IO instructions (inb_p/inw_p/..). + * Historically I wrote this stuff the same way as Linus did + * because I was young and clueless. And now it's so jucky that I + * don't want to put my eyes on it again to get rid of it :-) * - * This file is not meant to be obfuscating: it's just complicated - * to (a) handle it all in a way that makes gcc able to optimize it - * as well as possible and (b) trying to avoid writing the same thing - * over and over again with slight variations and possibly making a - * mistake somewhere. + * I'll do it then, because this code offends both me and my compiler + * - particularly the bits of inline asm which end up doing crap like + * 'lb $2,$2($5)' -- dwmw2 */ +#define IO_SPACE_LIMIT 0xffff + /* * On MIPS I/O ports are memory mapped, so we access them using normal * load/store instructions. mips_io_port_base is the virtual address to @@ -69,7 +63,10 @@ * instruction, so the lower 16 bits must be zero. Should be true on * on any sane architecture; generic code does not use this assumption. */ -extern unsigned long mips_io_port_base; +extern const unsigned long mips_io_port_base; + +#define set_io_port_base(base) \ + do { * (unsigned long *) &mips_io_port_base = (base); } while (0) /* * Thanks to James van Artsdalen for a better timing-fix than @@ -102,12 +99,12 @@ * Change virtual addresses to physical addresses and vv. * These are trivial on the 1:1 Linux/MIPS mapping */ -extern inline unsigned long virt_to_phys(volatile void * address) +static inline unsigned long virt_to_phys(volatile void * address) { return PHYSADDR(address); } -extern inline void * phys_to_virt(unsigned long address) +static inline void * phys_to_virt(unsigned long address) { return (void *)KSEG0ADDR(address); } @@ -115,30 +112,43 @@ /* * IO bus memory addresses are also 1:1 with the physical address */ -extern inline unsigned long virt_to_bus(volatile void * address) +static inline unsigned long virt_to_bus(volatile void * address) { return PHYSADDR(address); } -extern inline void * bus_to_virt(unsigned long address) +static inline void * bus_to_virt(unsigned long address) { return (void *)KSEG0ADDR(address); } +#define page_to_bus page_to_phys + /* * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped * for the processor. */ extern unsigned long isa_slot_offset; +/* + * Change "struct page" to physical address. + */ +#if defined(CONFIG_MIPS_AVALANCHE_PAGING) +#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) + __MEMORY_START) + /* phys_to_page(phys) is located in pgtable.h */ +#else +#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) +#endif /* CONFIG_MIPS_AVALANCHE_PAGING */ + + extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags); -extern inline void *ioremap(unsigned long offset, unsigned long size) +static inline void *ioremap(unsigned long offset, unsigned long size) { return __ioremap(offset, size, _CACHE_UNCACHED); } -extern inline void *ioremap_nocache(unsigned long offset, unsigned long size) +static inline void *ioremap_nocache(unsigned long offset, unsigned long size) { return __ioremap(offset, size, _CACHE_UNCACHED); } @@ -150,6 +160,50 @@ * 24-31 on SNI. * XXX more SNI hacks. */ +#ifdef JMR3927_INIT_INDIRECT_PCI +unsigned char tx_ioinb(unsigned char *addr); +void tx_iooutb(unsigned long data, unsigned char *addr); +unsigned short tx_ioinw(unsigned short *addr); +void tx_iooutw(unsigned long data, unsigned short *addr); +unsigned long tx_ioinl(unsigned int *addr); +void tx_iooutl(unsigned long data, unsigned int *addr); +void tx_insbyte(unsigned char *addr,void *buffer,unsigned int count); +void tx_insword(unsigned short *addr,void *buffer,unsigned int count); +void tx_inslong(unsigned int *addr,void *buffer,unsigned int count); +void tx_outsbyte(unsigned char *addr,void *buffer,unsigned int count); +void tx_outsword(unsigned short *addr,void *buffer,unsigned int count); +void tx_outslong(unsigned int *addr,void *buffer,unsigned int count); + +unsigned char tx_readb(unsigned char *addr); +void tx_writeb(unsigned long data, unsigned char *addr); +unsigned short tx_readw(unsigned short *addr); +void tx_writew(unsigned long data, unsigned short *addr); +unsigned long tx_readl(unsigned int *addr); +void tx_writel(unsigned long data, unsigned int *addr); + +#define readb(addr) (unsigned char)tx_readb((unsigned char *)(addr)) +#define readw(addr) (unsigned short)tx_readw((unsigned short *)(addr)) +#define readl(addr) (unsigned long)tx_readl((unsigned int *)(addr)) +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl + +#define writeb(b,addr) tx_writeb((b),(unsigned char *)(addr)) +#define writew(b,addr) tx_writew((b),(unsigned short *)(addr)) +#define writel(b,addr) tx_writel((b),(unsigned int *)(addr)) +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +#define std_readb(addr) (*(volatile unsigned char *)(addr)) +#define std_readw(addr) __ioswab16((*(volatile unsigned short *)(addr))) +#define std_readl(addr) __ioswab32((*(volatile unsigned int *)(addr))) +#define std_writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b) +#define std_writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b)) +#define std_writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b)) + +#else /* JMR3927_INIT_INDIRECT_PCI */ + #define readb(addr) (*(volatile unsigned char *)(addr)) #define readw(addr) __ioswab16((*(volatile unsigned short *)(addr))) #define readl(addr) __ioswab32((*(volatile unsigned int *)(addr))) @@ -157,19 +211,18 @@ #define __raw_readw readw #define __raw_readl readl -#define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b) +#define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (__ioswab8(b)) #define writew(b,addr) (*(volatile unsigned short *)(addr)) = (__ioswab16(b)) #define writel(b,addr) (*(volatile unsigned int *)(addr)) = (__ioswab32(b)) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel +#endif /* JMR3927_INIT_INDIRECT_PCI */ #define memset_io(a,b,c) memset((void *)(a),(b),(c)) #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) -/* END SNI HACKS ... */ - /* * ISA space is 'always mapped' on currently supported MIPS systems, no need * to explicitly ioremap() it. The fact that the ISA IO space is mapped @@ -178,18 +231,17 @@ * used as the IO-area pointer (it can be iounmapped as well, so the * analogy with PCI is quite large): */ -#define __ISA_IO_base ((char *)(PAGE_OFFSET)) +#define __ISA_IO_base ((char *)(isa_slot_offset)) -#define isa_readb(a) readb(a) -#define isa_readw(a) readw(a) -#define isa_readl(a) readl(a) -#define isa_writeb(b,a) writeb(b,a) -#define isa_writew(w,a) writew(w,a) -#define isa_writel(l,a) writel(l,a) - -#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) -#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) +#define isa_readb(a) readb(__ISA_IO_base + (a)) +#define isa_readw(a) readw(__ISA_IO_base + (a)) +#define isa_readl(a) readl(__ISA_IO_base + (a)) +#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a)) +#define isa_writew(w,a) writew(w,__ISA_IO_base + (a)) +#define isa_writel(l,a) writel(l,__ISA_IO_base + (a)) +#define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c)) +#define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c)) /* * We don't have csum_partial_copy_fromio() yet, so we cheat here and @@ -215,207 +267,208 @@ } #define isa_check_signature(io, s, l) check_signature(i,s,l) -/* - * Talk about misusing macros.. - */ -#define __OUT1(s) \ -extern inline void __out##s(unsigned int value, unsigned int port) { +#ifdef JMR3927_INIT_INDIRECT_PCI -#define __OUT2(m) \ -__asm__ __volatile__ ("s" #m "\t%0,%1(%2)" +#define outb(val,port) tx_iooutb((val),(unsigned char *)(port)) +#define inb(port) (unsigned char)tx_ioinb((unsigned char *)(port)) +#define outb_p(val,port) tx_iooutb((val),(unsigned char *)(port)) +#define inb_p(port) (unsigned char)tx_ioinb((unsigned char *)(port)) +#define outw(val,port) tx_iooutw((val),(unsigned short *)(port)) +#define inw(port) (unsigned short)tx_ioinw((unsigned short *)(port)) +#define outw_p(val,port) tx_iooutw((val),(unsigned short *)(port)) +#define inw_p(port) (unsigned short)tx_ioinw((unsigned short *)(port)) +#define outl(val,port) tx_iooutl((val),(unsigned int *)(port)) +#define inl(port) (unsigned long)tx_ioinl((unsigned int *)(port)) +#define outl_p(val,port) tx_iooutl((val),(unsigned int *)(port)) +#define inl_p(port) (unsigned long)tx_ioinl((unsigned int *)(port)) +#define outsb(port,addr,count) tx_outsbyte((unsigned char *)(port),addr,count) +#define insb(port,addr,count) tx_insbyte((unsigned char *)(port),addr,count) +#define outsw(port,addr,count) tx_outsword((unsigned short *)(port),addr,count) +#define insw(port,addr,count) tx_insword((unsigned short *)(port),addr,count) +#define outsl(port,addr,count) tx_outslong((unsigned short *)(port),addr,count) +#define insl(port,addr,count) tx_inslong((unsigned short *)(port),addr,count) + +#define std_outb(val,port) \ +do { \ + *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \ +} while(0) + +#define std_outw(val,port) \ +do { \ + *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val); \ +} while(0) + +#define std_outl(val,port) \ +do { \ + *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\ +} while(0) + +#define std_outb_p(val,port) \ +do { \ + *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \ + SLOW_DOWN_IO; \ +} while(0) + +#define std_outw_p(val,port) \ +do { \ + *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\ + SLOW_DOWN_IO; \ +} while(0) + +#define std_outl_p(val,port) \ +do { \ + *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\ + SLOW_DOWN_IO; \ +} while(0) + +#define std_inb(port) (__ioswab8(*(volatile u8 *)(mips_io_port_base + (port)))) +#define std_inw(port) (__ioswab16(*(volatile u16 *)(mips_io_port_base + (port)))) +#define std_inl(port) (__ioswab32(*(volatile u32 *)(mips_io_port_base + (port)))) + +#define std_inb_p(port) \ +({ \ + u8 __val; \ + \ + __val = *(volatile u8 *)(mips_io_port_base + (port)); \ + SLOW_DOWN_IO; \ + __ioswab8(__val); \ +}) + +#define std_inw_p(port) \ +({ \ + u16 __val; \ + \ + __val = *(volatile u16 *)(mips_io_port_base + (port)); \ + SLOW_DOWN_IO; \ + __ioswab16(__val); \ +}) + +#define std_inl_p(port) \ +({ \ + u32 __val; \ + \ + __val = *(volatile u32 *)(mips_io_port_base + (port)); \ + SLOW_DOWN_IO; \ + __ioswab32(__val); \ +}) + +#else /* JMR3927_INIT_INDIRECT_PCI */ + + +#define outb(val,port) \ +do { \ + *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \ +} while(0) + +#define outw(val,port) \ +do { \ + *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val); \ +} while(0) + +#define outl(val,port) \ +do { \ + *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\ +} while(0) + +#define outb_p(val,port) \ +do { \ + *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \ + SLOW_DOWN_IO; \ +} while(0) + +#define outw_p(val,port) \ +do { \ + *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\ + SLOW_DOWN_IO; \ +} while(0) + +#define outl_p(val,port) \ +do { \ + *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\ + SLOW_DOWN_IO; \ +} while(0) + +#define inb(port) (__ioswab8(*(volatile u8 *)(mips_io_port_base + (port)))) +#define inw(port) (__ioswab16(*(volatile u16 *)(mips_io_port_base + (port)))) +#define inl(port) (__ioswab32(*(volatile u32 *)(mips_io_port_base + (port)))) + +#define inb_p(port) \ +({ \ + u8 __val; \ + \ + __val = *(volatile u8 *)(mips_io_port_base + (port)); \ + SLOW_DOWN_IO; \ + __ioswab8(__val); \ +}) + +#define inw_p(port) \ +({ \ + u16 __val; \ + \ + __val = *(volatile u16 *)(mips_io_port_base + (port)); \ + SLOW_DOWN_IO; \ + __ioswab16(__val); \ +}) + +#define inl_p(port) \ +({ \ + u32 __val; \ + \ + __val = *(volatile u32 *)(mips_io_port_base + (port)); \ + SLOW_DOWN_IO; \ + __ioswab32(__val); \ +}) -#define __OUT(m,s,w) \ -__OUT1(s) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); } \ -__OUT1(s##c) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); } \ -__OUT1(s##_p) __OUT2(m) : : "r" (__ioswab##w(value)), "i" (0), "r" (mips_io_port_base+port)); \ - SLOW_DOWN_IO; } \ -__OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io_port_base)); \ - SLOW_DOWN_IO; } - -#define __IN1(t,s) \ -extern __inline__ t __in##s(unsigned int port) { t _v; - -/* - * Required nops will be inserted by the assembler - */ -#define __IN2(m) \ -__asm__ __volatile__ ("l" #m "\t%0,%1(%2)" - -#define __IN(t,m,s,w) \ -__IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return __ioswab##w(_v); } \ -__IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return __ioswab##w(_v); } \ -__IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return __ioswab##w(_v); } \ -__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); } - -#define __INS1(s) \ -extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) { - -#define __INS2(m) \ -if (count) \ -__asm__ __volatile__ ( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n" \ - "1:\tl" #m "\t$1,%4(%5)\n\t" \ - "subu\t%1,1\n\t" \ - "s" #m "\t$1,(%0)\n\t" \ - "bne\t$0,%1,1b\n\t" \ - "addiu\t%0,%6\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" - -#define __INS(m,s,i) \ -__INS1(s) __INS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (0), \ - "r" (mips_io_port_base+port), "I" (i) \ - : "$1");} \ -__INS1(s##c) __INS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "ir" (port), \ - "r" (mips_io_port_base), "I" (i) \ - : "$1");} - -#define __OUTS1(s) \ -extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) { - -#define __OUTS2(m) \ -if (count) \ -__asm__ __volatile__ ( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n" \ - "1:\tl" #m "\t$1,(%0)\n\t" \ - "subu\t%1,1\n\t" \ - "s" #m "\t$1,%4(%5)\n\t" \ - "bne\t$0,%1,1b\n\t" \ - "addiu\t%0,%6\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" - -#define __OUTS(m,s,i) \ -__OUTS1(s) __OUTS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \ - : "$1");} \ -__OUTS1(s##c) __OUTS2(m) \ - : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \ - : "$1");} - -__IN(unsigned char,b,b,8) -__IN(unsigned short,h,w,16) -__IN(unsigned int,w,l,32) - -__OUT(b,b,8) -__OUT(h,w,16) -__OUT(w,l,32) - -__INS(b,b,1) -__INS(h,w,2) -__INS(w,l,4) - -__OUTS(b,b,1) -__OUTS(h,w,2) -__OUTS(w,l,4) - - -/* - * Note that due to the way __builtin_constant_p() works, you - * - can't use it inside an inline function (it will never be true) - * - you don't have to worry about side effects within the __builtin.. - */ -#define outb(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outbc((val),(port)) : \ - __outb((val),(port))) - -#define inb(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inbc(port) : \ - __inb(port)) - -#define outb_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outbc_p((val),(port)) : \ - __outb_p((val),(port))) - -#define inb_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inbc_p(port) : \ - __inb_p(port)) - -#define outw(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outwc((val),(port)) : \ - __outw((val),(port))) - -#define inw(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inwc(port) : \ - __inw(port)) - -#define outw_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outwc_p((val),(port)) : \ - __outw_p((val),(port))) - -#define inw_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inwc_p(port) : \ - __inw_p(port)) - -#define outl(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outlc((val),(port)) : \ - __outl((val),(port))) - -#define inl(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inlc(port) : \ - __inl(port)) - -#define outl_p(val,port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outlc_p((val),(port)) : \ - __outl_p((val),(port))) - -#define inl_p(port) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inlc_p(port) : \ - __inl_p(port)) - - -#define outsb(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outsbc((port),(addr),(count)) : \ - __outsb ((port),(addr),(count))) - -#define insb(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __insbc((port),(addr),(count)) : \ - __insb((port),(addr),(count))) - -#define outsw(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outswc((port),(addr),(count)) : \ - __outsw ((port),(addr),(count))) - -#define insw(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inswc((port),(addr),(count)) : \ - __insw((port),(addr),(count))) - -#define outsl(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __outslc((port),(addr),(count)) : \ - __outsl ((port),(addr),(count))) - -#define insl(port,addr,count) \ -((__builtin_constant_p((port)) && (port) < 32768) ? \ - __inslc((port),(addr),(count)) : \ - __insl((port),(addr),(count))) +static inline void outsb(unsigned long port, void *addr, unsigned int count) +{ + while (count--) { + outb(*(u8 *)addr, port); + addr++; + } +} -#define IO_SPACE_LIMIT 0xffff +static inline void insb(unsigned long port, void *addr, unsigned int count) +{ + while (count--) { + *(u8 *)addr = inb(port); + addr++; + } +} + +static inline void outsw(unsigned long port, void *addr, unsigned int count) +{ + while (count--) { + outw(*(u16 *)addr, port); + addr += 2; + } +} + +static inline void insw(unsigned long port, void *addr, unsigned int count) +{ + while (count--) { + *(u16 *)addr = inw(port); + addr += 2; + } +} + +static inline void outsl(unsigned long port, void *addr, unsigned int count) +{ + while (count--) { + outl(*(u32 *)addr, port); + addr += 4; + } +} + +static inline void insl(unsigned long port, void *addr, unsigned int count) +{ + while (count--) { + *(u32 *)addr = inl(port); + addr += 4; + } +} + +#endif /* JMR3927_INIT_INDIRECT_PCI */ /* * The caches on some architectures aren't dma-coherent and have need to @@ -435,6 +488,8 @@ * be discarded. This operation is necessary before dma operations * to the memory. */ +#ifdef CONFIG_NONCOHERENT_IO + extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); @@ -443,4 +498,12 @@ #define dma_cache_wback(start,size) _dma_cache_wback(start,size) #define dma_cache_inv(start,size) _dma_cache_inv(start,size) +#else /* Sane hardware */ + +#define dma_cache_wback_inv(start,size) do { (start); (size); } while (0) +#define dma_cache_wback(start,size) do { (start); (size); } while (0) +#define dma_cache_inv(start,size) do { (start); (size); } while (0) + +#endif /* CONFIG_NONCOHERENT_IO */ + #endif /* _ASM_IO_H */