--- zzzz-none-000/linux-2.4.17/include/asm-mips/mipsregs.h 2001-09-09 17:43:01.000000000 +0000 +++ sangam-fb-322/linux-2.4.17/include/asm-mips/mipsregs.h 2004-11-24 13:21:33.000000000 +0000 @@ -59,6 +59,20 @@ #define CP0_TAGHI $29 #define CP0_ERROREPC $30 +#ifdef CONFIG_CPU_LX45XXX +#define CP0_CCTL $20 /* Lexra Cache Control Register */ + +/* + * Lexra Cache Control Register fields + */ +#define CCTL_DINVAL 0x00000001 +#define CCTL_IINVAL 0x00000002 +#define CCTL_ILOCK 0x0000000c +#define CCTL_IRAMFILL4 0x00000010 +#define CCTL_IRAMOFF 0x00000020 + +#endif /* CPU_LX45XXX */ + /* * R4640/R4650 cp0 register names. These registers are listed * here only for completeness; without MMU these CPUs are not useable @@ -79,6 +93,12 @@ #define CP0_S1_DERRADDR0 $26 #define CP0_S1_DERRADDR1 $27 #define CP0_S1_INTCONTROL $20 + +/* + * TX39 Series + */ +#define CP0_TX39_CACHE $7 + /* * Coprocessor 1 (FPU) register names */ @@ -142,12 +162,15 @@ */ #include #ifdef CONFIG_CPU_VR41XX + #define PM_1K 0x00000000 #define PM_4K 0x00001800 #define PM_16K 0x00007800 #define PM_64K 0x0001f800 #define PM_256K 0x0007f800 + #else + #define PM_4K 0x00000000 #define PM_16K 0x00006000 #define PM_64K 0x0001e000 @@ -155,6 +178,7 @@ #define PM_1M 0x001fe000 #define PM_4M 0x007fe000 #define PM_16M 0x01ffe000 + #endif /* @@ -169,75 +193,6 @@ #define PL_16M 24 /* - * Macros to access the system control coprocessor - */ -#define read_32bit_cp0_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "mfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) - -#define read_32bit_cp0_set1_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ - "cfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ - : "=r" (__res)); \ - __res;}) - -/* - * For now use this only with interrupts disabled! - */ -#define read_64bit_cp0_register(source) \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0,"STR(source)"\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res;}) - -#define write_32bit_cp0_register(register,value) \ - __asm__ __volatile__( \ - "mtc0\t%0,"STR(register)"\n\t" \ - "nop" \ - : : "r" (value)); - -#define write_32bit_cp0_set1_register(register,value) \ - __asm__ __volatile__( \ - "ctc0\t%0,"STR(register)"\n\t" \ - "nop" \ - : : "r" (value)); - -#define write_64bit_cp0_register(register,value) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%0,"STR(register)"\n\t" \ - ".set\tmips0" \ - : : "r" (value)) - -/* - * This should be changed when we get a compiler that support the MIPS32 ISA. - */ -#define read_mips32_cp0_config1() \ -({ int __res; \ - __asm__ __volatile__( \ - ".set\tnoreorder\n\t" \ - ".set\tnoat\n\t" \ - ".word\t0x40018001\n\t" \ - "move\t%0,$1\n\t" \ - ".set\tat\n\t" \ - ".set\treorder" \ - :"=r" (__res)); \ - __res;}) - -/* * R4x00 interrupt enable / cause bits */ #define IE_SW0 (1<< 8) @@ -261,56 +216,6 @@ #define C_IRQ4 (1<<14) #define C_IRQ5 (1<<15) -#ifndef _LANGUAGE_ASSEMBLY -/* - * Manipulate the status register. - * Mostly used to access the interrupt bits. - */ -#define __BUILD_SET_CP0(name,register) \ -extern __inline__ unsigned int \ -set_cp0_##name(unsigned int set) \ -{ \ - unsigned int res; \ - \ - res = read_32bit_cp0_register(register); \ - res |= set; \ - write_32bit_cp0_register(register, res); \ - \ - return res; \ -} \ - \ -extern __inline__ unsigned int \ -clear_cp0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ - \ - res = read_32bit_cp0_register(register); \ - res &= ~clear; \ - write_32bit_cp0_register(register, res); \ - \ - return res; \ -} \ - \ -extern __inline__ unsigned int \ -change_cp0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ - \ - res = read_32bit_cp0_register(register); \ - res &= ~change; \ - res |= (new & change); \ - if(change) \ - write_32bit_cp0_register(register, res); \ - \ - return res; \ -} - -__BUILD_SET_CP0(status,CP0_STATUS) -__BUILD_SET_CP0(cause,CP0_CAUSE) -__BUILD_SET_CP0(config,CP0_CONFIG) - -#endif /* defined (_LANGUAGE_ASSEMBLY) */ - /* * Bitfields in the R4xx0 cp0 status register */ @@ -419,6 +324,7 @@ #define STATUSF_IP15 (1 << 7) #define ST0_CH 0x00040000 #define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 #define ST0_BEV 0x00400000 #define ST0_RE 0x02000000 #define ST0_FR 0x04000000 @@ -480,6 +386,14 @@ #define CONF_HALT (1 << 25) /* + * Bits in the TX49 coprozessor 0 config register. + */ +#define TX49_CONF_DC (1 << 16) +#define TX49_CONF_IC (1 << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (1 << 18) +#define TX49_CONF_CWFON (1 << 27) + +/* * R10000 performance counter definitions. * * FIXME: The R10000 performance counter opens a nice way to implement CPU @@ -535,4 +449,455 @@ #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ +#ifndef _LANGUAGE_ASSEMBLY + +/* + * Macros to access the system control coprocessor + */ +#define read_32bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "mfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +#define read_32bit_cp0_set1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc0\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +/* + * For now use this only with interrupts disabled! + */ +#define read_64bit_cp0_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0,"STR(source)"\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res;}) + +#define write_32bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + "mtc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_32bit_cp0_set1_register(register,value) \ + __asm__ __volatile__( \ + "ctc0\t%0,"STR(register)"\n\t" \ + "nop" \ + : : "r" (value)); + +#define write_64bit_cp0_register(register,value) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%0,"STR(register)"\n\t" \ + ".set\tmips0" \ + : : "r" (value)) + +/* + * This should be changed when we get a compiler that support the MIPS32 ISA. + */ +#define read_mips32_cp0_config1() \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tnoreorder\n\t" \ + ".set\tnoat\n\t" \ + "#.set\tmips64\n\t" \ + "#mfc0\t$1, $16, 1\n\t" \ + "#.set\tmips0\n\t" \ + ".word\t0x40018001\n\t" \ + "move\t%0,$1\n\t" \ + ".set\tat\n\t" \ + ".set\treorder" \ + :"=r" (__res)); \ + __res;}) + +/* + * Macros to access the floating point coprocessor control registers + */ +#define read_32bit_cp1_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ + "cfc1\t%0,"STR(source)"\n\t" \ + ".set\tpop" \ + : "=r" (__res)); \ + __res;}) + +/* TLB operations. */ +static inline void tlb_probe(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "tlbp\n\t" + ".set pop"); +} + +static inline void tlb_read(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "tlbr\n\t" + ".set pop"); +} + +static inline void tlb_write_indexed(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "tlbwi\n\t" + ".set pop"); +} + +static inline void tlb_write_random(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "tlbwr\n\t" + ".set pop"); +} + +/* Dealing with various CP0 mmu/cache related registers. */ + + +static inline unsigned long get_pagemask(void) +{ + unsigned long val; + + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $5\n\t" + ".set pop" + : "=r" (val)); + return val; +} + +static inline void set_pagemask(unsigned long val) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mtc0 %z0, $5\n\t" + ".set pop" + : : "Jr" (val)); +} + +/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */ +static inline unsigned long get_entrylo0(void) +{ + unsigned long val; + + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $2\n\t" + ".set pop" + : "=r" (val)); + return val; +} + +static inline void set_entrylo0(unsigned long val) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mtc0 %z0, $2\n\t" + ".set pop" + : : "Jr" (val)); +} + +static inline unsigned long get_entrylo1(void) +{ + unsigned long val; + + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $3\n\t" + ".set pop" : "=r" (val)); + + return val; +} + +static inline void set_entrylo1(unsigned long val) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mtc0 %z0, $3\n\t" + ".set pop" + : : "Jr" (val)); +} + +/* CP0_ENTRYHI register */ +static inline unsigned long get_entryhi(void) +{ + unsigned long val; + + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $10\n\t" + ".set pop" + : "=r" (val)); + + return val; +} + +static inline void set_entryhi(unsigned long val) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mtc0 %z0, $10\n\t" + ".set pop" + : : "Jr" (val)); +} + +/* CP0_INDEX register */ +static inline unsigned long get_index(void) +{ + unsigned long val; + + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $0\n\t" + ".set pop" + : "=r" (val)); + return val; +} + +static inline void set_index(unsigned long val) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mtc0 %z0, $0\n\t" + ".set pop" + : : "Jr" (val)); +} + +/* CP0_WIRED register */ +static inline unsigned long get_wired(void) +{ + unsigned long val; + + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $6\n\t" + ".set pop" + : "=r" (val)); + return val; +} + +static inline void set_wired(unsigned long val) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mtc0 %z0, $6\n\t" + ".set pop" + : : "Jr" (val)); +} + +/* CP0_STATUS register */ +static inline unsigned int get_status(void) +{ + unsigned long val; + + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $12\n\t" + ".set pop" + : "=r" (val)); + return val; +} + +static inline void set_status(unsigned long val) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mtc0 %z0, $12\n\t" + ".set pop" + : : "Jr" (val)); +} + +static inline unsigned long get_info(void) +{ + unsigned long val; + + __asm__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $7\n\t" + ".set pop" + : "=r" (val)); + return val; +} + +/* CP0_TAGLO and CP0_TAGHI registers */ +static inline unsigned long get_taglo(void) +{ + unsigned long val; + + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $28\n\t" + ".set pop" + : "=r" (val)); + return val; +} + +static inline void set_taglo(unsigned long val) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mtc0 %z0, $28\n\t" + ".set pop" + : : "Jr" (val)); +} + +static inline unsigned long get_taghi(void) +{ + unsigned long val; + + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $29\n\t" + ".set pop" + : "=r" (val)); + return val; +} + +static inline void set_taghi(unsigned long val) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mtc0 %z0, $29\n\t" + ".set pop" + : : "Jr" (val)); +} + +/* CP0_CONTEXT register */ +static inline unsigned long get_context(void) +{ + unsigned long val; + + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mfc0 %0, $4\n\t" + ".set pop" + : "=r" (val)); + + return val; +} + +static inline void set_context(unsigned long val) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set reorder\n\t" + "mtc0 %z0, $4\n\t" + ".set pop" + : : "Jr" (val)); +} + +/* + * Manipulate the status register. + * Mostly used to access the interrupt bits. + */ +#define __BUILD_SET_CP0(name,register) \ +static inline unsigned int \ +set_cp0_##name(unsigned int set) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res |= set; \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +clear_cp0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res &= ~clear; \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} \ + \ +static inline unsigned int \ +change_cp0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ + \ + res = read_32bit_cp0_register(register); \ + res &= ~change; \ + res |= (new & change); \ + write_32bit_cp0_register(register, res); \ + \ + return res; \ +} + +__BUILD_SET_CP0(status,CP0_STATUS) +__BUILD_SET_CP0(cause,CP0_CAUSE) +__BUILD_SET_CP0(config,CP0_CONFIG) + +#define __enable_fpu() \ +do { \ + set_cp0_status(ST0_CU1); \ + asm("nop;nop;nop;nop"); /* max. hazard */ \ +} while (0) + +#define __disable_fpu() \ +do { \ + clear_cp0_status(ST0_CU1); \ + /* We don't care about the cp0 hazard here */ \ +} while (0) + +#define enable_fpu() \ +do { \ + if (mips_cpu.options & MIPS_CPU_FPU) \ + __enable_fpu(); \ +} while (0) + +#define disable_fpu() \ +do { \ + if (mips_cpu.options & MIPS_CPU_FPU) \ + __disable_fpu(); \ +} while (0) + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + #endif /* _ASM_MIPSREGS_H */