--- zzzz-none-000/linux-2.4.17/include/asm-mips/tx3912.h 2001-09-09 17:43:01.000000000 +0000 +++ sangam-fb-322/linux-2.4.17/include/asm-mips/tx3912.h 2004-11-24 13:21:33.000000000 +0000 @@ -1,5 +1,5 @@ /* - * linux/include/asm-mips/tx3912.h + * include/asm-mips/tx3912.h * * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com) * @@ -7,562 +7,355 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Register includes for TMPR3912/05 and PR31700 processors + * Registers for TMPR3912/05 and PR31700 processors */ -#ifndef __TX3912_H__ -#define __TX3912_H__ +#ifndef _TX3912_H_ +#define _TX3912_H_ -#include +/***************************************************************************** + * Clock Subsystem * + * --------------- * + * Chapter 6 in Philips PR31700 and Toshiba TMPR3905/12 User Manuals * + *****************************************************************************/ +#define TX3912_CLK_CTRL 0x01c0 -/****************************************************************************** -* -* 01 General macro definitions -* -******************************************************************************/ - -#define REGISTER_BASE 0xb0c00000 - -#ifndef _LANGUAGE_ASSEMBLY - - #define REG_AT(x) (*((volatile unsigned long *)(REGISTER_BASE + x))) - -#else - - #define REG_AT(x) (REGISTER_BASE + x) - -#endif - -#define BIT(x) (1 << x) - -/****************************************************************************** -* -* 02 Bus Interface Unit -* -******************************************************************************/ - -#define MemConfig0 REG_AT(0x000) -#define MemConfig1 REG_AT(0x004) -#define MemConfig2 REG_AT(0x008) -#define MemConfig3 REG_AT(0x00c) -#define MemConfig4 REG_AT(0x010) -#define MemConfig5 REG_AT(0x014) -#define MemConfig6 REG_AT(0x018) -#define MemConfig7 REG_AT(0x01c) -#define MemConfig8 REG_AT(0x020) - -/* Memory config register 1 */ -#define MEM1_ENCS1USER BIT(21) - -/* Memory config register 3 */ -#define MEM3_CARD1ACCVAL_MASK (BIT(24) | BIT(25) | BIT(26) | BIT(27)) -#define MEM3_CARD1IOEN BIT(4) - -/* Memory config register 4 */ -#define MEM4_ARBITRATIONEN BIT(29) -#define MEM4_MEMPOWERDOWN BIT(16) -#define MEM4_ENREFRESH1 BIT(15) -#define MEM4_ENREFRESH0 BIT(14) -#define MEM4_ENWATCH BIT(24) -#define MEM4_WATCHTIMEVAL_MASK (0xf) -#define MEM4_WATCHTIMEVAL_SHIFT (20) -#define MEM4_WATCHTIME_VALUE (0xf) - -/* - *********************************************************************** - * * - * 06 Clock Module * - * * - *********************************************************************** - */ -#define TX3912_CLK_CTRL_BASE (REGISTER_BASE + 0x1c0) - -#define TX3912_CLK_CTRL_CHICLKDIV_MASK 0xff000000 -#define TX3912_CLK_CTRL_CHICLKDIV_SHIFT 24 -#define TX3912_CLK_CTRL_ENCLKTEST 0x00800000 -#define TX3912_CLK_CTRL_CLKTESTSELSIB 0x00400000 -#define TX3912_CLK_CTRL_CHIMCLKSEL 0x00200000 -#define TX3912_CLK_CTRL_CHICLKDIR 0x00100000 -#define TX3912_CLK_CTRL_ENCHIMCLK 0x00080000 -#define TX3912_CLK_CTRL_ENVIDCLK 0x00040000 -#define TX3912_CLK_CTRL_ENMBUSCLK 0x00020000 -#define TX3912_CLK_CTRL_ENSPICLK 0x00010000 -#define TX3912_CLK_CTRL_ENTIMERCLK 0x00008000 -#define TX3912_CLK_CTRL_ENFASTTIMERCLK 0x00004000 -#define TX3912_CLK_CTRL_SIBMCLKDIR 0x00002000 -#define TX3912_CLK_CTRL_RESERVED 0x00001000 -#define TX3912_CLK_CTRL_ENSIBMCLK 0x00000800 -#define TX3912_CLK_CTRL_SIBMCLKDIV_MASK 0x00000700 -#define TX3912_CLK_CTRL_SIBMCLKDIV_SHIFT 8 -#define TX3912_CLK_CTRL_CSERSEL 0x00000080 -#define TX3912_CLK_CTRL_CSERDIV_MASK 0x00000070 -#define TX3912_CLK_CTRL_CSERDIV_SHIFT 4 -#define TX3912_CLK_CTRL_ENCSERCLK 0x00000008 -#define TX3912_CLK_CTRL_ENIRCLK 0x00000004 -#define TX3912_CLK_CTRL_ENUARTACLK 0x00000002 -#define TX3912_CLK_CTRL_ENUARTBCLK 0x00000001 - - - - -/****************************************************************************** -* -* 07 CHI module -* -******************************************************************************/ - -#define CHIControl REG_AT(0x1D8) -#define CHIPointerEnable REG_AT(0x1DC) -#define CHIReceivePtrA REG_AT(0x1E0) -#define CHIReceivePtrB REG_AT(0x1E4) -#define CHITransmitPtrA REG_AT(0x1E8) -#define CHITransmitPtrB REG_AT(0x1EC) -#define CHISize REG_AT(0x1F0) -#define CHIReceiveStart REG_AT(0x1F4) -#define CHITransmitStart REG_AT(0x1F8) -#define CHIHoldingReg REG_AT(0x1FC) - -/* CHI Control Register */ -/* */ -#define CHI_RXEN BIT(2) -#define CHI_TXEN BIT(1) -#define CHI_ENCHI BIT(0) - -/****************************************************************************** -* -* 08 Interrupt module -* -******************************************************************************/ - -/* Register locations */ - -#define IntStatus1 REG_AT(0x100) -#define IntStatus2 REG_AT(0x104) -#define IntStatus3 REG_AT(0x108) -#define IntStatus4 REG_AT(0x10c) -#define IntStatus5 REG_AT(0x110) -#define IntStatus6 REG_AT(0x114) - -#define IntClear1 REG_AT(0x100) -#define IntClear2 REG_AT(0x104) -#define IntClear3 REG_AT(0x108) -#define IntClear4 REG_AT(0x10c) -#define IntClear5 REG_AT(0x110) -#define IntClear6 REG_AT(0x114) - -#define IntEnable1 REG_AT(0x118) -#define IntEnable2 REG_AT(0x11c) -#define IntEnable3 REG_AT(0x120) -#define IntEnable4 REG_AT(0x124) -#define IntEnable5 REG_AT(0x128) -#define IntEnable6 REG_AT(0x12c) - -/* Interrupt Status Register 1 at offset 100 */ -#define INT1_LCDINT BIT(31) -#define INT1_DFINT BIT(30) -#define INT1_CHIDMAHALF BIT(29) -#define INT1_CHIDMAFULL BIT(28) -#define INT1_CHIDMACNTINT BIT(27) -#define INT1_CHIRXAINT BIT(26) -#define INT1_CHIRXBINT BIT(25) -#define INT1_CHIACTINT BIT(24) -#define INT1_CHIERRINT BIT(23) -#define INT1_SND0_5INT BIT(22) -#define INT1_SND1_0INT BIT(21) -#define INT1_TEL0_5INT BIT(20) -#define INT1_TEL1_0INT BIT(19) -#define INT1_SNDDMACNTINT BIT(18) -#define INT1_TELDMACNTINT BIT(17) -#define INT1_LSNDCLIPINT BIT(16) -#define INT1_RSNDCLIPINT BIT(15) -#define INT1_VALSNDPOSINT BIT(14) -#define INT1_VALSNDNEGINT BIT(13) -#define INT1_VALTELPOSINT BIT(12) -#define INT1_VALTELNEGINT BIT(11) -#define INT1_SNDININT BIT(10) -#define INT1_TELININT BIT(9) -#define INT1_SIBSF0INT BIT(8) -#define INT1_SIBSF1INT BIT(7) -#define INT1_SIBIRQPOSINT BIT(6) -#define INT1_SIBIRQNEGINT BIT(5) - -/* Interrupt Status Register 2 at offset 104 */ -#define INT2_UARTARXINT BIT(31) -#define INT2_UARTARXOVERRUN BIT(30) -#define INT2_UARTAFRAMEINT BIT(29) -#define INT2_UARTABREAKINT BIT(28) -#define INT2_UARTATXINT BIT(26) -#define INT2_UARTATXOVERRUN BIT(25) -#define INT2_UARTAEMPTY BIT(24) - -#define INT2_UARTBRXINT BIT(21) -#define INT2_UARTBRXOVERRUN BIT(20) -#define INT2_UARTBFRAMEINT BIT(29) -#define INT2_UARTBBREAKINT BIT(18) -#define INT2_UARTBTXINT BIT(16) -#define INT2_UARTBTXOVERRUN BIT(15) -#define INT2_UARTBEMPTY BIT(14) - -#define INT2_UARTA_RX (BIT(31) | BIT(30) | BIT(29) | BIT(28) | BIT(27)) -#define INT2_UARTA_TX (BIT(26) | BIT(25) | BIT(24)) -#define INT2_UARTA_DMA (BIT(23) | BIT(22)) - -#define INT2_UARTB_RX (BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17)) -#define INT2_UARTB_TX (BIT(16) | BIT(15) | BIT(14)) -#define INT2_UARTB_DMA (BIT(13) | BIT(12)) - -/* Interrupt Status Register 5 */ -#define INT5_RTCINT BIT(31) -#define INT5_ALARMINT BIT(30) -#define INT5_PERIODICINT BIT(29) -#define INT5_POSPWRINT BIT(27) -#define INT5_NEGPWRINT BIT(26) -#define INT5_POSPWROKINT BIT(25) -#define INT5_NEGPWROKINT BIT(24) -#define INT5_POSONBUTINT BIT(23) -#define INT5_NEGONBUTINT BIT(22) -#define INT5_SPIAVAILINT BIT(21) /* 0x0020 0000 */ -#define INT5_SPIERRINT BIT(20) /* 0x0010 0000 */ -#define INT5_SPIRCVINT BIT(19) /* 0x0008 0000 */ -#define INT5_SPIEMPTYINT BIT(18) /* 0x0004 0000 */ -#define INT5_IOPOSINT6 BIT(13) -#define INT5_IOPOSINT5 BIT(12) -#define INT5_IOPOSINT4 BIT(11) -#define INT5_IOPOSINT3 BIT(10) -#define INT5_IOPOSINT2 BIT(9) -#define INT5_IOPOSINT1 BIT(8) -#define INT5_IOPOSINT0 BIT(7) -#define INT5_IONEGINT6 BIT(6) -#define INT5_IONEGINT5 BIT(5) -#define INT5_IONEGINT4 BIT(4) -#define INT5_IONEGINT3 BIT(3) -#define INT5_IONEGINT2 BIT(2) -#define INT5_IONEGINT1 BIT(1) -#define INT5_IONEGINT0 BIT(0) - -#define INT5_IONEGINT_SHIFT 0 -#define INT5_IONEGINT_MASK (0x7F<