--- zzzz-none-000/linux-2.4.17/include/asm-mips64/io.h 2001-09-09 17:43:02.000000000 +0000 +++ sangam-fb-322/linux-2.4.17/include/asm-mips64/io.h 2004-11-24 13:21:49.000000000 +0000 @@ -22,6 +22,10 @@ #include #endif +#ifdef CONFIG_SGI_IP32 +#include +#endif + extern unsigned long bus_to_baddr[256]; /* @@ -30,13 +34,18 @@ #undef CONF_SLOWDOWN_IO /* + * Change "struct page" to physical address. + */ +#define page_to_phys(page) PHYSADDR(page_address(page)) + +/* * On MIPS, we have the whole physical address space mapped at all * times, so "ioremap()" and "iounmap()" do not need to do anything. * * We cheat a bit and always return uncachable areas until we've fixed * the drivers to handle caching properly. */ -extern inline void * +static inline void * ioremap(unsigned long offset, unsigned long size) { return (void *) (IO_SPACE_BASE | offset); @@ -46,13 +55,13 @@ * area. It's useful if some control registers are in such an area and write * combining or read caching is not desirable. */ -extern inline void * +static inline void * ioremap_nocache (unsigned long offset, unsigned long size) { return (void *) (IO_SPACE_BASE | offset); } -extern inline void iounmap(void *addr) +static inline void iounmap(void *addr) { } @@ -102,16 +111,19 @@ * Change virtual addresses to physical addresses and vv. * These are trivial on the 1:1 Linux/MIPS mapping */ -extern inline unsigned long virt_to_phys(volatile void * address) +static inline unsigned long virt_to_phys(volatile void * address) { return (unsigned long)address - PAGE_OFFSET; } -extern inline void * phys_to_virt(unsigned long address) +static inline void * phys_to_virt(unsigned long address) { return (void *)(address + PAGE_OFFSET); } +/* This is too simpleminded for more sophisticated than dumb hardware ... */ +#define page_to_bus page_to_phys + /* * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped * for the processor. This implies the assumption that there is only @@ -120,6 +132,26 @@ extern unsigned long isa_slot_offset; /* + * ISA space is 'always mapped' on currently supported MIPS systems, no need + * to explicitly ioremap() it. The fact that the ISA IO space is mapped + * to PAGE_OFFSET is pure coincidence - it does not mean ISA values + * are physical addresses. The following constant pointer can be + * used as the IO-area pointer (it can be iounmapped as well, so the + * analogy with PCI is quite large): + */ +#define __ISA_IO_base ((char *)(isa_slot_offset)) + +#define isa_readb(a) readb(__ISA_IO_base + (a)) +#define isa_readw(a) readw(__ISA_IO_base + (a)) +#define isa_readl(a) readl(__ISA_IO_base + (a)) +#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a)) +#define isa_writew(w,a) writew(w,__ISA_IO_base + (a)) +#define isa_writel(l,a) writel(l,__ISA_IO_base + (a)) +#define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c)) +#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c)) +#define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c)) + +/* * We don't have csum_partial_copy_fromio() yet, so we cheat here and * just copy it. The net code will then do the checksum later. */ @@ -147,7 +179,7 @@ */ #define __OUT1(s) \ -extern inline void __out##s(unsigned int value, unsigned long port) { +static inline void __out##s(unsigned int value, unsigned long port) { #define __OUT2(m) \ __asm__ __volatile__ ("s" #m "\t%0,%1(%2)" @@ -161,7 +193,7 @@ SLOW_DOWN_IO; } #define __IN1(t,s) \ -extern __inline__ t __in##s(unsigned long port) { t _v; +static inline t __in##s(unsigned long port) { t _v; /* * Required nops will be inserted by the assembler @@ -176,7 +208,7 @@ __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return _v; } #define __INS1(s) \ -extern inline void __ins##s(unsigned long port, void * addr, unsigned long count) { +static inline void __ins##s(unsigned long port, void * addr, unsigned long count) { #define __INS2(m) \ if (count) \ @@ -194,15 +226,15 @@ #define __INS(m,s,i) \ __INS1(s) __INS2(m) \ : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \ - : "$1");} \ + : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), \ + "I" (i));} \ __INS1(s##c) __INS2(m) \ : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \ - : "$1");} + : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), \ + "I" (i));} #define __OUTS1(s) \ -extern inline void __outs##s(unsigned long port, const void * addr, unsigned long count) { +static inline void __outs##s(unsigned long port, const void * addr, unsigned long count) { #define __OUTS2(m) \ if (count) \ @@ -220,12 +252,12 @@ #define __OUTS(m,s,i) \ __OUTS1(s) __OUTS2(m) \ : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \ - : "$1");} \ + : "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), \ + "I" (i));} \ __OUTS1(s##c) __OUTS2(m) \ : "=r" (addr), "=r" (count) \ - : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \ - : "$1");} + : "0" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), \ + "I" (i));} __IN(unsigned char,b,b) __IN(unsigned short,h,w) @@ -357,22 +389,7 @@ * be discarded. This operation is necessary before dma operations * to the memory. */ -#ifdef CONFIG_COHERENT_IO - -/* This is for example for IP27. */ -extern inline void dma_cache_wback_inv(unsigned long start, unsigned long size) -{ -} - -extern inline void dma_cache_wback(unsigned long start, unsigned long size) -{ -} - -extern inline void dma_cache_inv(unsigned long start, unsigned long size) -{ -} - -#else +#ifdef CONFIG_NONCOHERENT_IO extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); @@ -382,6 +399,12 @@ #define dma_cache_wback(start,size) _dma_cache_wback(start,size) #define dma_cache_inv(start,size) _dma_cache_inv(start,size) -#endif +#else /* Sane hardware */ + +#define dma_cache_wback_inv(start,size) do { (start); (size); } while (0) +#define dma_cache_wback(start,size) do { (start); (size); } while (0) +#define dma_cache_inv(start,size) do { (start); (size); } while (0) + +#endif /* CONFIG_NONCOHERENT_IO */ #endif /* _ASM_IO_H */