--- zzzz-none-000/linux-2.4.17/include/asm-ppc/dma.h 2001-05-21 22:02:06.000000000 +0000 +++ sangam-fb-322/linux-2.4.17/include/asm-ppc/dma.h 2004-11-24 13:21:50.000000000 +0000 @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.dma.h 1.8 05/17/01 18:14:24 cort + * BK Id: SCCS/s.dma.h 1.13 11/17/01 11:19:06 trini */ /* * linux/include/asm/dma.h: Defines for using and allocating dma channels. @@ -14,6 +14,7 @@ #include #include #include +#include #include /* @@ -27,7 +28,7 @@ * not valid for the PReP platform. Take what you read * with a grain of salt. */ - + #ifndef _ASM_DMA_H #define _ASM_DMA_H @@ -38,13 +39,12 @@ /* The maximum address that we can perform a DMA transfer to on this platform */ /* Doesn't really apply... */ -#define MAX_DMA_ADDRESS 0xFFFFFFFF +#define MAX_DMA_ADDRESS 0xFFFFFFFF /* in arch/ppc/kernel/setup.c -- Cort */ extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ; extern unsigned long ISA_DMA_THRESHOLD; - #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER #define dma_outb outb_p #else @@ -69,7 +69,7 @@ * - page registers for 5-7 don't use data bit 0, represent 128K pages * - page registers for 0-3 use bit 0, represent 64K pages * - * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory. + * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory. * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing. * Note that addresses loaded into registers must be _physical_ addresses, * not logical addresses (which may differ if paging is active). @@ -80,7 +80,7 @@ * | ... | | ... | | ... | * | ... | | ... | | ... | * | ... | | ... | | ... | - * P7 ... P0 A7 ... A0 A7 ... A0 + * P7 ... P0 A7 ... A0 A7 ... A0 * | Page | Addr MSB | Addr LSB | (DMA registers) * * Address mapping for channels 5-7: @@ -89,7 +89,7 @@ * | ... | \ \ ... \ \ \ ... \ \ * | ... | \ \ ... \ \ \ ... \ (not used) * | ... | \ \ ... \ \ \ ... \ - * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 + * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 * | Page | Addr MSB | Addr LSB | (DMA registers) * * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses @@ -98,23 +98,15 @@ * * Transfer count (_not # bytes_) is limited to 64K, represented as actual * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, - * and up to 128K bytes may be transferred on channels 5-7 in one operation. + * and up to 128K bytes may be transferred on channels 5-7 in one operation. * */ -/* used in nasty hack for sound - see prep_setup_arch() -- Cort */ +/* see prep_setup_arch() for detailed informations */ +#if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_ALL_PPC) extern long ppc_cs4232_dma, ppc_cs4232_dma2; -#if defined(CONFIG_CS4232) -#if defined(CONFIG_ALL_PPC) #define SND_DMA1 ppc_cs4232_dma #define SND_DMA2 ppc_cs4232_dma2 -#else /* !CONFIG_ALL_PPC */ -#define SND_DMA1 -1 -#define SND_DMA2 -1 -#endif /* CONFIG_ALL_PPC */ -#elif defined(CONFIG_MSS) -#define SND_DMA1 CONFIG_MSS_DMA -#define SND_DMA2 CONFIG_MSS_DMA2 #else #define SND_DMA1 -1 #define SND_DMA2 -1 @@ -127,67 +119,67 @@ /* DMA controller registers */ #define DMA1_CMD_REG 0x08 /* command register (w) */ #define DMA1_STAT_REG 0x08 /* status register (r) */ -#define DMA1_REQ_REG 0x09 /* request register (w) */ +#define DMA1_REQ_REG 0x09 /* request register (w) */ #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ #define DMA1_MODE_REG 0x0B /* mode register (w) */ #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ -#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ +#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ -#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ -#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ +#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ +#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ #define DMA2_CMD_REG 0xD0 /* command register (w) */ #define DMA2_STAT_REG 0xD0 /* status register (r) */ -#define DMA2_REQ_REG 0xD2 /* request register (w) */ +#define DMA2_REQ_REG 0xD2 /* request register (w) */ #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ #define DMA2_MODE_REG 0xD6 /* mode register (w) */ #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ -#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ +#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ -#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ -#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ +#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ +#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ -#define DMA_ADDR_0 0x00 /* DMA address registers */ -#define DMA_ADDR_1 0x02 -#define DMA_ADDR_2 0x04 -#define DMA_ADDR_3 0x06 -#define DMA_ADDR_4 0xC0 -#define DMA_ADDR_5 0xC4 -#define DMA_ADDR_6 0xC8 -#define DMA_ADDR_7 0xCC - -#define DMA_CNT_0 0x01 /* DMA count registers */ -#define DMA_CNT_1 0x03 -#define DMA_CNT_2 0x05 -#define DMA_CNT_3 0x07 -#define DMA_CNT_4 0xC2 -#define DMA_CNT_5 0xC6 -#define DMA_CNT_6 0xCA -#define DMA_CNT_7 0xCE - -#define DMA_LO_PAGE_0 0x87 /* DMA page registers */ -#define DMA_LO_PAGE_1 0x83 -#define DMA_LO_PAGE_2 0x81 -#define DMA_LO_PAGE_3 0x82 -#define DMA_LO_PAGE_5 0x8B -#define DMA_LO_PAGE_6 0x89 -#define DMA_LO_PAGE_7 0x8A - -#define DMA_HI_PAGE_0 0x487 /* DMA page registers */ -#define DMA_HI_PAGE_1 0x483 -#define DMA_HI_PAGE_2 0x481 -#define DMA_HI_PAGE_3 0x482 -#define DMA_HI_PAGE_5 0x48B -#define DMA_HI_PAGE_6 0x489 -#define DMA_HI_PAGE_7 0x48A +#define DMA_ADDR_0 0x00 /* DMA address registers */ +#define DMA_ADDR_1 0x02 +#define DMA_ADDR_2 0x04 +#define DMA_ADDR_3 0x06 +#define DMA_ADDR_4 0xC0 +#define DMA_ADDR_5 0xC4 +#define DMA_ADDR_6 0xC8 +#define DMA_ADDR_7 0xCC + +#define DMA_CNT_0 0x01 /* DMA count registers */ +#define DMA_CNT_1 0x03 +#define DMA_CNT_2 0x05 +#define DMA_CNT_3 0x07 +#define DMA_CNT_4 0xC2 +#define DMA_CNT_5 0xC6 +#define DMA_CNT_6 0xCA +#define DMA_CNT_7 0xCE + +#define DMA_LO_PAGE_0 0x87 /* DMA page registers */ +#define DMA_LO_PAGE_1 0x83 +#define DMA_LO_PAGE_2 0x81 +#define DMA_LO_PAGE_3 0x82 +#define DMA_LO_PAGE_5 0x8B +#define DMA_LO_PAGE_6 0x89 +#define DMA_LO_PAGE_7 0x8A + +#define DMA_HI_PAGE_0 0x487 /* DMA page registers */ +#define DMA_HI_PAGE_1 0x483 +#define DMA_HI_PAGE_2 0x481 +#define DMA_HI_PAGE_3 0x482 +#define DMA_HI_PAGE_5 0x48B +#define DMA_HI_PAGE_6 0x489 +#define DMA_HI_PAGE_7 0x48A -#define DMA1_EXT_REG 0x40B -#define DMA2_EXT_REG 0x4D6 +#define DMA1_EXT_REG 0x40B +#define DMA2_EXT_REG 0x4D6 -#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ -#define DMA_AUTOINIT 0x10 +#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ +#define DMA_AUTOINIT 0x10 -extern spinlock_t dma_spin_lock; +extern spinlock_t dma_spin_lock; static __inline__ unsigned long claim_dma_lock(void) { @@ -206,27 +198,23 @@ { unsigned char ucDmaCmd=0x00; - if (dmanr != 4) - { - dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */ - dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */ + if (dmanr != 4) { + dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */ + dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */ } - if (dmanr<=3) - { - dma_outb(dmanr, DMA1_MASK_REG); - dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */ + if (dmanr <= 3) { + dma_outb(dmanr, DMA1_MASK_REG); + dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */ } else - { - dma_outb(dmanr & 3, DMA2_MASK_REG); - } + dma_outb(dmanr & 3, DMA2_MASK_REG); } static __inline__ void disable_dma(unsigned int dmanr) { - if (dmanr<=3) - dma_outb(dmanr | 4, DMA1_MASK_REG); + if (dmanr <= 3) + dma_outb(dmanr | 4, DMA1_MASK_REG); else - dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); + dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); } /* Clear the 'DMA Pointer Flip Flop'. @@ -238,19 +226,19 @@ */ static __inline__ void clear_dma_ff(unsigned int dmanr) { - if (dmanr<=3) - dma_outb(0, DMA1_CLEAR_FF_REG); + if (dmanr <= 3) + dma_outb(0, DMA1_CLEAR_FF_REG); else - dma_outb(0, DMA2_CLEAR_FF_REG); + dma_outb(0, DMA2_CLEAR_FF_REG); } /* set mode (above) for a specific DMA channel */ static __inline__ void set_dma_mode(unsigned int dmanr, char mode) { - if (dmanr<=3) - dma_outb(mode | dmanr, DMA1_MODE_REG); + if (dmanr <= 3) + dma_outb(mode | dmanr, DMA1_MODE_REG); else - dma_outb(mode | (dmanr&3), DMA2_MODE_REG); + dma_outb(mode | (dmanr & 3), DMA2_MODE_REG); } /* Set only the page register bits of the transfer address. @@ -263,41 +251,41 @@ switch(dmanr) { case 0: dma_outb(pagenr, DMA_LO_PAGE_0); - dma_outb(pagenr>>8, DMA_HI_PAGE_0); + dma_outb(pagenr >> 8, DMA_HI_PAGE_0); break; case 1: dma_outb(pagenr, DMA_LO_PAGE_1); - dma_outb(pagenr>>8, DMA_HI_PAGE_1); + dma_outb(pagenr >> 8, DMA_HI_PAGE_1); break; case 2: dma_outb(pagenr, DMA_LO_PAGE_2); - dma_outb(pagenr>>8, DMA_HI_PAGE_2); + dma_outb(pagenr >> 8, DMA_HI_PAGE_2); break; case 3: dma_outb(pagenr, DMA_LO_PAGE_3); - dma_outb(pagenr>>8, DMA_HI_PAGE_3); + dma_outb(pagenr >> 8, DMA_HI_PAGE_3); break; - case 5: - if (SND_DMA1 == 5 || SND_DMA2 == 5) + case 5: + if (SND_DMA1 == 5 || SND_DMA2 == 5) dma_outb(pagenr, DMA_LO_PAGE_5); else dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5); - dma_outb(pagenr>>8, DMA_HI_PAGE_5); + dma_outb(pagenr >> 8, DMA_HI_PAGE_5); break; case 6: - if (SND_DMA1 == 6 || SND_DMA2 == 6) + if (SND_DMA1 == 6 || SND_DMA2 == 6) dma_outb(pagenr, DMA_LO_PAGE_6); else dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6); - dma_outb(pagenr>>8, DMA_HI_PAGE_6); + dma_outb(pagenr >> 8, DMA_HI_PAGE_6); break; case 7: if (SND_DMA1 == 7 || SND_DMA2 == 7) dma_outb(pagenr, DMA_LO_PAGE_7); else dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7); - dma_outb(pagenr>>8, DMA_HI_PAGE_7); - break; + dma_outb(pagenr >> 8, DMA_HI_PAGE_7); + break; } } @@ -307,20 +295,19 @@ */ static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys) { - if (dmanr <= 3) { - dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - } else { - if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { - dma_outb( phys & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - dma_outb( (dmanr&3), DMA2_EXT_REG); - } else { - dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - } + if (dmanr <= 3) { + dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE ); + dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE); + } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { + dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE ); + dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) + + IO_DMA2_BASE); + dma_outb((dmanr & 3), DMA2_EXT_REG); + } else { + dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE); + dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE); } - set_dma_page(dmanr, phys>>16); + set_dma_page(dmanr, phys >> 16); } @@ -334,22 +321,23 @@ */ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) { - count--; - if (dmanr <= 3) { - dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - } else { - if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { - dma_outb( count & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - dma_outb( (count>>8) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - } else { - dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - } - } + count--; + if (dmanr <= 3) { + dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE); + dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 + + IO_DMA1_BASE); + } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { + dma_outb( count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE); + dma_outb( (count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 + + IO_DMA2_BASE); + } else { + dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 + + IO_DMA2_BASE); + dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 + + IO_DMA2_BASE); + } } - /* Get DMA residue count. After a DMA transfer, this * should return zero. Reading this while a DMA transfer is * still in progress will return unpredictable results. @@ -360,27 +348,32 @@ */ static __inline__ int get_dma_residue(unsigned int dmanr) { - unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE - : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; + unsigned int io_port = (dmanr <= 3) ? + ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE + : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE; /* using short to get 16-bit wrap around */ unsigned short count; count = 1 + dma_inb(io_port); count += dma_inb(io_port) << 8; - + return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2) - ? count : (count<<1); + ? count : (count<<1); + } /* These are in kernel/dma.c: */ -extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ -extern void free_dma(unsigned int dmanr); /* release it again */ + +/* reserve a DMA channel */ +extern int request_dma(unsigned int dmanr, const char * device_id); +/* release it again */ +extern void free_dma(unsigned int dmanr); #ifdef CONFIG_PCI -extern int isa_dma_bridge_buggy; -#else -#define isa_dma_bridge_buggy (0) +extern int isa_dma_bridge_buggy; +#else +#define isa_dma_bridge_buggy (0) #endif #endif /* _ASM_DMA_H */ #endif /* __KERNEL__ */