--- zzzz-none-000/linux-2.4.17/include/asm-ppc/irq.h 2001-05-21 22:02:06.000000000 +0000 +++ sangam-fb-322/linux-2.4.17/include/asm-ppc/irq.h 2004-11-24 13:21:50.000000000 +0000 @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.irq.h 1.9 05/17/01 18:14:24 cort + * BK Id: SCCS/s.irq.h 1.16 11/28/01 13:34:05 paulus */ #ifdef __KERNEL__ #ifndef _ASM_IRQ_H @@ -14,7 +14,7 @@ extern void enable_irq(unsigned int); #if defined(CONFIG_4xx) - +#include /* * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has * 32 possible interrupts, a majority of which are not implemented on @@ -29,23 +29,19 @@ * */ -#define NR_IRQS 32 +#define NR_AIC_IRQS 32 +#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS) + +static __inline__ int +irq_cannonicalize(int irq) +{ + return (irq); +} -#define AIC_INT0 (0) -#define AIC_INT4 (4) -#define AIC_INT5 (5) -#define AIC_INT6 (6) -#define AIC_INT7 (7) -#define AIC_INT8 (8) -#define AIC_INT9 (9) -#define AIC_INT10 (10) -#define AIC_INT11 (11) -#define AIC_INT27 (27) -#define AIC_INT28 (28) -#define AIC_INT29 (29) -#define AIC_INT30 (30) -#define AIC_INT31 (31) +#elif defined (CONFIG_NP405) +#define NR_AIC_IRQS 32 +#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS) static __inline__ int irq_cannonicalize(int irq) @@ -55,6 +51,10 @@ #elif defined(CONFIG_8xx) +/* Now include the board configuration specific associations. +*/ +#include + /* The MPC8xx cores have 16 possible interrupts. There are eight * possible level sensitive interrupts assigned and generated internally * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. @@ -63,10 +63,22 @@ * * On some implementations, there is also the possibility of an 8259 * through the PCI and PCI-ISA bridges. + * + * We are "flattening" the interrupt vectors of the cascaded CPM + * and 8259 interrupt controllers so that we can uniquely identify + * any interrupt source with a single integer. */ #define NR_SIU_INTS 16 +#define NR_CPM_INTS 32 +#ifndef NR_8259_INTS +#define NR_8259_INTS 0 +#endif + +#define SIU_IRQ_OFFSET 0 +#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS) +#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) -#define NR_IRQS (NR_SIU_INTS + NR_8259_INTS) +#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS) /* These values must be zero-based and map 1:1 with the SIU configuration. * They are used throughout the 8xx I/O subsystem to generate @@ -91,10 +103,6 @@ #define SIU_IRQ7 (14) #define SIU_LEVEL7 (15) -/* Now include the board configuration specific associations. -*/ -#include - /* The internal interrupts we can configure as we see fit. * My personal preference is CPM at level 2, which puts it above the * MBX PCI/ISA/IDE interrupts. @@ -124,48 +132,6 @@ } #else /* CONFIG_4xx + CONFIG_8xx */ - -#if defined(CONFIG_APUS) -/* - * This structure is used to chain together the ISRs for a particular - * interrupt source (if it supports chaining). - */ -typedef struct irq_node { - void (*handler)(int, void *, struct pt_regs *); - unsigned long flags; - void *dev_id; - const char *devname; - struct irq_node *next; -} irq_node_t; - -/* - * This structure has only 4 elements for speed reasons - */ -typedef struct irq_handler { - void (*handler)(int, void *, struct pt_regs *); - unsigned long flags; - void *dev_id; - const char *devname; -} irq_handler_t; - -/* count of spurious interrupts */ -extern volatile unsigned int num_spurious; - -extern int sys_request_irq(unsigned int, - void (*)(int, void *, struct pt_regs *), - unsigned long, const char *, void *); -extern void sys_free_irq(unsigned int, void *); - -/* - * This function returns a new irq_node_t - */ -extern irq_node_t *new_irq_node(void); - -/* Number of m68k interrupts */ -#define SYS_IRQS 8 - -#endif /* CONFIG_APUS */ - /* * this is the # irq's for all ppc arch's (pmac/chrp/prep) * so it is the max of them all @@ -189,17 +155,55 @@ */ #define NR_SIU_INTS 64 -/* There are many more than these, we will add them as we need them. -*/ +#define SIU_INT_ERROR ((uint)0x00) +#define SIU_INT_I2C ((uint)0x01) +#define SIU_INT_SPI ((uint)0x02) +#define SIU_INT_RISC ((uint)0x03) #define SIU_INT_SMC1 ((uint)0x04) #define SIU_INT_SMC2 ((uint)0x05) +#define SIU_INT_IDMA1 ((uint)0x06) +#define SIU_INT_IDMA2 ((uint)0x07) +#define SIU_INT_IDMA3 ((uint)0x08) +#define SIU_INT_IDMA4 ((uint)0x09) +#define SIU_INT_SDMA ((uint)0x0a) +#define SIU_INT_TIMER1 ((uint)0x0c) +#define SIU_INT_TIMER2 ((uint)0x0d) +#define SIU_INT_TIMER3 ((uint)0x0e) +#define SIU_INT_TIMER4 ((uint)0x0f) +#define SIU_INT_TMCNT ((uint)0x10) +#define SIU_INT_PIT ((uint)0x11) +#define SIU_INT_IRQ1 ((uint)0x13) +#define SIU_INT_IRQ2 ((uint)0x14) +#define SIU_INT_IRQ3 ((uint)0x15) +#define SIU_INT_IRQ4 ((uint)0x16) +#define SIU_INT_IRQ5 ((uint)0x17) +#define SIU_INT_IRQ6 ((uint)0x18) +#define SIU_INT_IRQ7 ((uint)0x19) #define SIU_INT_FCC1 ((uint)0x20) #define SIU_INT_FCC2 ((uint)0x21) #define SIU_INT_FCC3 ((uint)0x22) +#define SIU_INT_MCC1 ((uint)0x24) +#define SIU_INT_MCC2 ((uint)0x25) #define SIU_INT_SCC1 ((uint)0x28) #define SIU_INT_SCC2 ((uint)0x29) #define SIU_INT_SCC3 ((uint)0x2a) #define SIU_INT_SCC4 ((uint)0x2b) +#define SIU_INT_PC15 ((uint)0x30) +#define SIU_INT_PC14 ((uint)0x31) +#define SIU_INT_PC13 ((uint)0x32) +#define SIU_INT_PC12 ((uint)0x33) +#define SIU_INT_PC11 ((uint)0x34) +#define SIU_INT_PC10 ((uint)0x35) +#define SIU_INT_PC9 ((uint)0x36) +#define SIU_INT_PC8 ((uint)0x37) +#define SIU_INT_PC7 ((uint)0x38) +#define SIU_INT_PC6 ((uint)0x39) +#define SIU_INT_PC5 ((uint)0x3a) +#define SIU_INT_PC4 ((uint)0x3b) +#define SIU_INT_PC3 ((uint)0x3c) +#define SIU_INT_PC2 ((uint)0x3d) +#define SIU_INT_PC1 ((uint)0x3e) +#define SIU_INT_PC0 ((uint)0x3f) #endif /* CONFIG_8260 */ @@ -211,19 +215,14 @@ static __inline__ int irq_cannonicalize(int irq) { if (ppc_md.irq_cannonicalize) - { return ppc_md.irq_cannonicalize(irq); - } - else - { - return irq; - } + return irq; } #endif #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) -/* pendatic: these are long because they are used with set_bit --RR */ +/* pedantic: these are long because they are used with set_bit --RR */ extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; extern atomic_t ppc_n_lost_interrupts;