--- zzzz-none-000/linux-4.4.60/Documentation/devicetree/bindings/arm/coresight.txt 2017-04-08 07:53:53.000000000 +0000 +++ scorpion-1750e-727/linux-4.4.60/Documentation/devicetree/bindings/arm/coresight.txt 2021-02-04 17:41:59.000000000 +0000 @@ -19,6 +19,7 @@ - "arm,coresight-etm3x", "arm,primecell"; - "arm,coresight-etm4x", "arm,primecell"; - "qcom,coresight-replicator1x", "arm,primecell"; + - "arm,coresight-stm", "arm,primecell"; * reg: physical base address and length of the register set(s) of the component. @@ -36,15 +37,30 @@ layout using the generic DT graph presentation found in "bindings/graph.txt". + * coresight-name: unique descriptive name of the component. + * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators: - * compatible: Currently supported value is (note the absence of the + * compatible: Currently supported values are (note the absence of the AMBA markee): - "arm,coresight-replicator" + - "qcom,coresight-csr" + - "arm,coresight-cti" + - "qcom,coresight-tpda" + - "qcom,coresight-tpdm" + - "qcom,coresight-remote-etm" + - "qcom,coresight-qpdi" + - "qcom,coresight-hwevent" + - "qcom,coresight-dummy" * port or ports: same as above. + * coresight-name: unique descriptive name of the component. + +* Optional properties for all components: + * reg-names: names corresponding to each reg property value. + * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management @@ -58,6 +74,55 @@ * arm,buffer-size: size of contiguous buffer space for TMC ETR (embedded trace router) + * arm,default-sink: represents the default compile time CoreSight sink + + * coresight-ctis: represents flush and reset CTIs for TMC buffer + + * qcom,force-reg-dump: enables TMC reg dump support + + * arm,sg-enable : indicates whether scatter gather feature is enabled + by default for TMC ETR configuration. + +* Required property for TPDAs: + + * qcom,tpda-atid: must be present. Specifies the ATID for TPDA. + +* Optional properties for TPDAs: + + * qcom,bc-elem-size: specifies the BC element size supported by each + monitor connected to the aggregator on each port. Should be specified + in pairs (port, bc element size). + + * qcom,tc-elem-size: specifies the TC element size supported by each + monitor connected to the aggregator on each port. Should be specified + in pairs (port, tc element size). + + * qcom,dsb-elem-size: specifies the DSB element size supported by each + monitor connected to the aggregator on each port. Should be specified + in pairs (port, dsb element size). + + * qcom,cmb-elem-size: specifies the CMB element size supported by each + monitor connected to the aggregator on each port. Should be specified + in pairs (port, cmb element size). + +* Optional properties for TPDM: + + * qcom,clk-enable: specifies whether additional clock bit needs to be + set for M4M TPDM. + + * qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed + after enabling the subunit. + +* Required property for Remote ETMs: + + * qcom,inst-id: must be present. QMI instance id for remote ETMs. + +* Optional properties for QPDI: + + * qcom,pmic-carddetect-gpio: indicates the hotplug capabilities of the + qpdi driver + + * qcom,skip-ldo: set to skip LDO management. Example: @@ -174,6 +239,42 @@ }; }; + tpda_mss: tpda@7043000 { + compatible = "qcom,coresight-tpda"; + reg = <0x7043000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda-mss"; + + qcom,tpda-atid = <67>; + qcom,dsb-elem-size = <0 32>; + qcom,cmb-elem-size = <0 32>; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_mss_out_funnel_in1: endpoint { + remote-endpoint = + <&funnel_in1_in_tpda_mss>; + }; + }; + port@1 { + reg = <0>; + tpda_mss_in_tpdm_mss: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_mss_out_tpda_mss>; + }; + }; + }; + }; + 3. Sources ptm@2201c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; @@ -202,3 +303,55 @@ }; }; }; + + stm: stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + arm,primecell-periphid = <0x0003b962>; + + reg = <0x6002000 0x1000>, + <0x16280000 0x180000>; + reg-names = "stm-base", "stm-data-base"; + + coresight-name = "coresight-stm"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "apb_pclk", "core_a_clk"; + + port{ + stm_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_stm>; + }; + }; + }; + + tpdm_mss: tpdm@7042000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7042000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-mss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_mss_out_tpda_mss: endpoint { + remote-endpoint = <&tpda_mss_in_tpdm_mss>; + }; + }; + }; + +4. CTIs + cti0: cti@6010000 { + compatible = "arm,coresight-cti"; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + };