--- zzzz-none-000/linux-3.10.107/arch/blackfin/mach-bf609/clock.c 2017-06-27 09:49:32.000000000 +0000 +++ scorpion-7490-727/linux-3.10.107/arch/blackfin/mach-bf609/clock.c 2021-02-04 17:41:59.000000000 +0000 @@ -73,24 +73,6 @@ bfin_write32(reg, val2); } -static void clk_reg_set_bits(u32 reg, uint32_t mask) -{ - u32 val; - - val = bfin_read32(reg); - val |= mask; - bfin_write32(reg, val); -} - -static void clk_reg_clear_bits(u32 reg, uint32_t mask) -{ - u32 val; - - val = bfin_read32(reg); - val &= ~mask; - bfin_write32(reg, val); -} - int wait_for_pll_align(void) { int i = 10000; @@ -120,6 +102,7 @@ } EXPORT_SYMBOL(clk_disable); + unsigned long clk_get_rate(struct clk *clk) { unsigned long ret = 0; @@ -131,7 +114,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) { - long ret = -EIO; + long ret = 0; if (clk->ops && clk->ops->round_rate) ret = clk->ops->round_rate(clk, rate); return ret; @@ -220,6 +203,12 @@ } } +unsigned long dummy_get_rate(struct clk *clk) +{ + clk->parent->rate = clk_get_rate(clk->parent); + return clk->parent->rate; +} + unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate) { unsigned long max_rate; @@ -283,6 +272,10 @@ .round_rate = sys_clk_round_rate, }; +static struct clk_ops dummy_clk_ops = { + .get_rate = dummy_get_rate, +}; + static struct clk sys_clkin = { .name = "SYS_CLKIN", .rate = CONFIG_CLKIN_HZ, @@ -364,6 +357,24 @@ .parent = &pll_clk, }; +static struct clk ethclk = { + .name = "stmmaceth", + .parent = &sclk0, + .ops = &dummy_clk_ops, +}; + +static struct clk ethpclk = { + .name = "pclk", + .parent = &sclk0, + .ops = &dummy_clk_ops, +}; + +static struct clk spiclk = { + .name = "spi", + .parent = &sclk1, + .ops = &dummy_clk_ops, +}; + static struct clk_lookup bf609_clks[] = { CLK(sys_clkin, NULL, "SYS_CLKIN"), CLK(pll_clk, NULL, "PLLCLK"), @@ -375,6 +386,9 @@ CLK(sclk1, NULL, "SCLK1"), CLK(dclk, NULL, "DCLK"), CLK(oclk, NULL, "OCLK"), + CLK(ethclk, NULL, "stmmaceth"), + CLK(ethpclk, NULL, "pclk"), + CLK(spiclk, NULL, "spi"), }; int __init clk_init(void)